MOTOROLA MC74ACT323DWR2, MC74ACT323M Datasheet
5-1
FACT DATA
Advance Information
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The MC74AC323/74ACT323 is an 8-bit universal shift/storage register with
3-state outputs. Its function is similar to the MC74AC299/74ACT299 with the
exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate serial inputs and outputs are provided
for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
• Common Parallel I/O for Reduced Pin Count
• Additional Serial Inputs and Outputs for Expansion
• Four Operating Modes: Shift Left, Shift Right, Load and Store
• 3-State Outputs for Bus-Oriented Applications
• Outputs Source/Sink 24 mA
• ′ACT323 Has TTL Compatible Inputs
1920 18 17 16 15 14
21 3 4 5 6 7
V
CC
13
8
12
9
11
10
S1DS7Q7I/O7I/O5I/O3I/O1CP DS
0
S0OE
1OE2
I/O6I/O4I/O2I/O0Q0SR
GND
PIN NAMES
CP Clock Pulse Input
DS
0
Serial Data Input for Right Shift
DS
7
Serial Data Input for Left Shift
S0, S
1
Mode Select Inputs
SR
Synchronous Master Reset
OE
1,
OE23-State Output Enable Inputs
I/O0–I/O7Multipled Parallel Data Inputs or
3-State Parallel Data Outputs
Q0, Q
7
Serial Outputs
This document contains information on a new product. Specifications and information herein are subject to change without notice.
8-INPUT UNIVERSAL SHIFT/
STORAGE REGISTER WITH
SYNCHRONOUS RESET
AND COMMON I/O PINS
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
DS
0
DS
7
Q
7
S
0
S
1
CP
OE
SR Q0I/O
0
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
7
1
2
MC74AC323 MC74ACT323
5-2
FACT DATA
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
CP
S
0
OE
1OE2
I/O
6
I/O
4
I/O
2
I/O
0
Q
0
S
1
DS
7
Q
7
I/O
7
I/O
5
I/O
3
DS
0
I/O
1
CP
CP
CP
CP
CP
CP
CP
CP
SR
MC74AC323 MC74ACT323
5-3
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC323/74ACT323 contains eight edgetriggered D-type flip-flops and the interstage logic necessary
to perform synchronous reset, shift left, shift right, parallel load
and hold operations. The type of operation is determined by S
0
and S1 as shown in the Mode Select T able. All flip-flop outputs
are brought out through 3 state buffers to separate I/O pins that
also serve as data inputs in the parallel load mode. Q0 and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR
overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP . All other
state changes are also initiated by the LOW-to-HIGH CP
transition. Inputs can change when the clock is in either state
provided only that the recommended setup and hold times,
relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE2 disables the 3-state
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can still
occur. The 3-state buffers are also disabled by HIGH signals
on both S0 and S1 in preparation for a parallel load operation.
TRUTH TABLE
Inputs
SR S1S0CP
Response
L X X Synchronous Reset; Q0 – Q7 = LOW
H H H Parallel Load; I/On → Q
n
H L H Shift Right; DS0 → Q0, Q0 → Q1, etc.
H H L Shift Left; DS7 → Q7, Q7 → Q6, etc.
H L L X Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Sink/Source Current, per Pin ±50 mA
I
CC
DC VCC or GND Current per Output Pin ±50 mA
T
stg
Storage Temperature –65 to +150 °C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
′AC 2.0 5.0 6.0
VCCSupply Voltage
′ACT 4.5 5.0 5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
VCC @ 3.0 V 150
tr, t
f
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
VCC @ 4.5 V 40 ns/V
r
, t
f
′AC Devices except Schmitt Inputs
VCC @ 5.5 V 25
Input Rise and Fall Time (Note 2)
VCC @ 4.5 V 10
tr, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 5.5 V 8.0
ns/V
T
J
Junction Temperature (PDIP) 140 °C
T
A
Operating Ambient Temperature Range –40 25 85 °C
I
OH
Output Current — High –24 mA
I
OL
Output Current — Low 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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