Motorola MC74ACT163D, MC74ACT161N, MC74ACT163N, MC74AC163D, MC74AC161N Datasheet

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5-1

FACT DATA

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The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/ 74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.

• Synchronous Counting and Loading

• High-Speed Synchronous Expansion

• Typical Count Rate of 125 MHz

• Outputs Source/Sink 24 mA

• ′ACT161 and ′ACT163 Have TTL Compatible Inputs

1516 14 13 12 11 10

21 3 4 5 6 7

TC Q0Q1Q2Q3CET PE

*R CP P0P1P2P3CEP GND

PIN NAMES

CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR (′161) Asynchronous Master Reset Input SR

(′163) Synchronous Reset Input P0–P3Parallel Data Inputs PE Parallel Enable Input Q0–Q3Flip-Flop Outputs TC Terminal Count Output

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

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SYNCHRONOUS

PRESETTABLE

BINARY COUNTER

N SUFFIX

CASE 648-08

PLASTIC

D SUFFIX

CASE 751B-05

PLASTIC

LOGIC SYMBOL

*MR for ′161 *SR

for ′163

PE P0P1P

CEP

CET CP

*R Q0Q1Q2Q

MC74AC161 MC74ACT161 MC74AC163 MC74ACT163

5-2

FACT DATA

FUNCTIONAL DESCRIPTION

The MC74AC161/74ACT161 and MC74AC163/74ACT163 count modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ′161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (′161), synchronous reset (′163), parallel load, count-up and hold. Five control inputs — Master Reset (MR

, ′161), Synchronous Reset (SR, ′163),

Parallel Enable (PE

), Count Enable Parallel (CEP) and Count Enable Trickle (CET)  determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR

overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP . A LOW signal on PE

overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP . With PE

and MR

(′161) or SR (′163) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The MC74AC161/74ACT161 and MC74AC163/74ACT163

use D-type edge-triggered flip-flops and changing the SR

, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The T erminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the MC74AC568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.

Logic Equations:Count Enable = CEP

•CET•PE

TC = Q

0•Q1•Q2•Q3

•CET

MODE SELECT TABLE

*SR

CET CEP

Action on the Rising Clock Edge ( )

L X X X Reset (Clear) H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold)

*For ′163 only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

STATE DIAGRAM

1 2 3

11 10 9

CEP

CET

MR ′161

′163

′

163

ONLY

′163

DETAIL A

DETAIL A DETAIL A DETAIL A

D CP D

Q Q

LOGIC DIAGRAM

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

′

161

ONLY

′161

MC74AC161 MC74ACT161 MC74AC163 MC74ACT163

5-3

FACT DATA

MAXIMUM RATINGS*

Symbol Parameter Value Unit

DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V

DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V

out

DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V

DC Input Current, per Pin ±20 mA

out

DC Output Sink/Source Current, per Pin ±50 mA

DC VCC or GND Current per Output Pin ±50 mA

stg

Storage Temperature –65 to +150 °C

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended

Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

′AC 2.0 5.0 6.0

VCCSupply Voltage

′ACT 4.5 5.0 5.5

Vin, V

out

DC Input Voltage, Output Voltage (Ref. to GND) 0 V

VCC @ 3.0 V 150

Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs

VCC @ 4.5 V 40 ns/V

, t

′AC Devices except Schmitt Inputs

VCC @ 5.5 V 25 VCC @ 4.5 V 10

tr, t

Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs

VCC @ 5.5 V 8.0

ns/V

Junction Temperature (PDIP) 140 °C

Operating Ambient Temperature Range –40 25 85 °C

Output Current — High –24 mA

Output Current — Low 24 mA

1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

tr, t

Input Rise and Fall Time (Note 2)

MC74AC161 MC74ACT161 MC74AC163 MC74ACT163

5-4

FACT DATA

DC CHARACTERISTICS

74AC 74AC

Symbol

Parameter

(V)

TA = +25°C

TA =

–40°C to +85°C

Unit

Conditions

Typ Guaranteed Limits

3.0 1.5 2.1 2.1 V

OUT

= 0.1 V

4.5 2.25 3.15 3.15 V or VCC – 0.1 V

5.5 2.75 3.85 3.85

3.0 1.5 0.9 0.9 V

OUT

= 0.1 V

4.5 2.25 1.35 1.35 V or VCC – 0.1 V

5.5 2.75 1.65 1.65

3.0 2.99 2.9 2.9 I

OUT

= –50 µA

4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4 *VIN = VIL or V

3.0 2.56 2.46

–12 mA

4.5 3.86 3.76

–24 mA

5.5 4.86 4.76 –24 mA

3.0 0.002 0.1 0.1 I

OUT

= 50 µA

4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1 *VIN = VIL or V

3.0 0.36 0.44

12 mA

4.5 0.36 0.44

24 mA

5.5 0.36 0.44 24 mA

5.5

±0.1

±1.0

µA

VI = VCC, GND

OLD

5.5 75 mA V

OLD

= 1.65 V Max

OHD

Output Current

5.5 –75 mA V

OHD

= 3.85 V Min

5.5

8.080µA

VIN = VCC or GND

* All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

Minimum High Level Input Voltage

Maximum Low Level Input Voltage

Minimum High Level Output Voltage

Maximum Low Level Output Voltage

Maximum Input Leakage Current

†Minimum Dynamic

Maximum Quiescent Supply Current

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