Motorola MC68VZ328 User Manual

MC68VZ328 Integrated Processor

User’s Manual

MC68VZ328UM/D

Rev. 0, 02/2000

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Contents

About This Book

Audience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix

Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx

Chapter 1

Introduction

1.1 Features of the MC68VZ328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.2.1 CPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2.2 Data and Address Mode Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.2.3 FLX68000 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3 Modules of the MC68VZ328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.1 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.2 Clock Generation Module and Power Control Module . . . . . . . . . . . . . . . . . . . . . . 1-8

1.3.3 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.4 Chip-Select Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.5 DRAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.6 LCD Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.7 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.3.8 General-Purpose I/O (GPIO) Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.9 Real-Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.10 General-Purpose Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.11 Serial Peripheral Interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.12 Universal Asynchronous Receiver/Transmitter (UART) Modules . . . . . . . . . . . . 1-10

1.3.13 Pulse-Width Modulators (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.3.14 In-Circuit Emulation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.3.15 Bootstrap Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Chapter 2

Signal Descriptions

2.1 Signals Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 Clock and System Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4 Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5 Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.6 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

 Table of Contents iii

2.7 Interrupt Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.8 LCD Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.9 UART 1 and UART 2 Controller Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.10 Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.11 Pulse-Width Modulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.12 Serial Peripheral Interface 1 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.13 Serial Peripheral Interface 2 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.14 Chip-Select and EDO RAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.15 SDRAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.16 In-Circuit Emulation (ICE) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Chapter 3

Memory Map

3.1 Programmer’s Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Chapter 4

Clock Generation Module and Power Control Module

4.1 Introduction to the Clock Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 CGM Operational Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 Detailed CGM Clock Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1 CLK32 Clock Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2 PLLCLK Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2.1 PLLCLK Initial Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.2.2 PLL Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.2.3 PLLCLK Frequency Selection Programming Example . . . . . . . . . . . . . . . . . . . 4-6

4.3.2.4 Programming Considerations When Changing Frequencies . . . . . . . . . . . . . . . 4-7

4.4 CGM Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.2 PLL Frequency Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.5 Introduction to the Power Control Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.5.1 Operating the PCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.5.1.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.5.1.2 Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.5.1.3 Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.5.1.4 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5.2 CGM Operation During Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5.3 Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5.4 Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Chapter 5

System Control

5.1 System Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Bus Monitors and Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2.1 System Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

iv MC68VZ328 User’s Manual 

5.2.2 Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.3 ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.2.4 I/O Drive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Chapter 6

Chip-Select Logic

6.1 Overview of the CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2 Chip-Select Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2.1 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2.2 Programmable Data Bus Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.3 Overlapping Chip-Select Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3.1 Chip-Select Group Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3.2 Chip-Select Upper Group Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.3.3 Chip-Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.3.4 Emulation Chip-Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.3.5 Chip-Select Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.3.6 Chip-Select Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.3.7 Chip-Select Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Chapter 7

DRAM Controller

7.1 Introduction to the DRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 DRAM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.1 Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.2 DTACK Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.2.3 Refresh Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.2.4 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.2.5 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.2.6 Low-Power Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.2.7 Data Retention During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.2.8 Data Retention Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

7.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.3.1 DRAM Memory Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.3.2 DRAM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.3.3 SDRAM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.3.4 SDRAM Power-down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Chapter 8

LCD Controller

8.1 LCD Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 LCD Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.2.1 Connecting the LCD Controller to an LCD Panel . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.1.1 Panel Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.2 Controlling the Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

 Table of Contents v

8.2.2.1 Format of the LCD Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.2.2 Format of the Cursor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.2.2.3 Mapping the Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.2.4 Generating Grayscale Tones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.3 Using Low-Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2.4 Using the DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2.4.1 Bus Bandwidth Calculation Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2.5 Self-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.2.5.1 Entering Self-Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.2.5.2 Canceling Self-Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.3.1 LCD Screen Starting Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.3.2 LCD Virtual Page Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.3.3 LCD Screen Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.3.4 LCD Screen Height Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.3.5 LCD Cursor X Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.3.6 LCD Cursor Y Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.3.7 LCD Cursor Width and Height Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14

8.3.8 LCD Blink Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14

8.3.9 LCD Panel Interface Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

8.3.10 LCD Polarity Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

8.3.11 LACD Rate Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

8.3.12 LCD Pixel Clock Divider Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

8.3.13 LCD Clocking Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.14 LCD Refresh Rate Adjustment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.15 LCD Panning Offset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.3.16 LCD Frame Rate Control Modulation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

8.3.17 LCD Gray Palette Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.3.18 PWM Contrast Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.3.19 Refresh Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.3.20 DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.4 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

Chapter 9

Interrupt Controller

9.1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2 Exception Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.3.1 Operation Mode Selection During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.3.2 Data Bus Width for Boot Device Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.4 Interrupt Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.4.1 Interrupt Priority Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.4.2 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.5 Vector Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.6 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.6.1 Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.6.2 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

vi MC68VZ328 User’s Manual 

9.6.3 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

9.6.4 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.6.5 Interrupt Pending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

9.6.6 Interrupt Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19

9.7 Keyboard Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

9.8 Pen Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

Chapter 10

I/O Ports

10.1 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.2 Status of I/O Ports During Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2.1 Warm Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2.2 Power-up Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.2.3 Summary of Port Behavior During Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3 I/O Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3.1 Data Flow from the I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3.2 Data Flow to the I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3.3 Operating a Port as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3.4 Port Pull-up and Pull-down Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4.1 Port A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4.1.1 Port A Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4.1.2 Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4.1.3 Port A Pull-up Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.4.2 Port B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.4.2.1 Port B Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.4.2.2 Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.4.2.3 Port B Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

10.4.2.4 Port B Pull-up Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

10.4.2.5 Port B Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.4.3 Port C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.4.3.1 Port C Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.4.3.2 Port C Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.4.3.3 Port C Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

10.4.3.4 Port C Pull-down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

10.4.3.5 Port C Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

10.4.4 Port D Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.4.5 Port D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

10.4.5.1 Port D Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

10.4.5.2 Port D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

10.4.5.3 Port D Interrupt Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.4.5.4 Port D Pull-up Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.4.5.5 Port D Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

10.4.5.6 Port D Polarity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

10.4.5.7 Port D Interrupt Request Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

10.4.5.8 Port D Keyboard Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

10.4.5.9 Port D Interrupt Request Edge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20

 Table of Contents vii

10.4.6 Port E Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10.4.6.1 Port E Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10.4.6.2 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

10.4.6.3 Port E Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

10.4.6.4 Port E Pull-up Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

10.4.6.5 Port E Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

10.4.7 Port F Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

10.4.7.1 Port F Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

10.4.7.2 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25

10.4.7.3 Port F Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26

10.4.7.4 Port F Pull-up/Pull-down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

10.4.7.5 Port F Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

10.4.8 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.4.8.1 Port G Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.4.8.2 Port G Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

10.4.8.3 Port G Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29

10.4.8.4 Port G Operational Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

10.4.8.5 Port G Pull-up Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

10.4.8.6 Port G Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

10.4.9 Port J Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

10.4.9.1 Port J Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

10.4.9.2 Port J Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

10.4.9.3 Port J Dedicated I/O Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

10.4.9.4 Port J Pull-up Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33

10.4.9.5 Port J Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33

10.4.10 Port K Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

10.4.10.1 Port K Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

10.4.10.2 Port K Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

10.4.10.3 Port K Dedicated I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35

10.4.10.4 Port K Pull-up/Pull-down Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36

10.4.10.5 Port K Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36

10.4.11 Port M Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37

10.4.11.1 Port M Direction Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37

10.4.11.2 Port M Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38

10.4.11.3 Port M Dedicated I/O Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39

10.4.11.4 Port M Pull-up/Pull-down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39

10.4.11.5 Port M Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40

Chapter 11

Real-Time Clock

11.1 RTC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.1.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.1.2 Time-of-Day Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.1.3 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.1.4 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.1.5 Real-Time Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.1.6 Minute Stopwatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

viii MC68VZ328 User’s Manual 

11.1.6.1 Minute Stopwatch Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.1 RTC Time Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.2 RTC Day Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.2.3 RTC Alarm Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

11.2.4 RTC Day Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.2.5 Watchdog Timer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

11.2.6 RTC Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.2.7 RTC Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.2.8 RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

11.2.9 Stopwatch Minutes Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

Chapter 12

General-Purpose Timers

12.1 GP Timer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1.1 Clock Source and Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.1.2 Timer Events and Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.1.2.1 Restart Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.1.2.2 Free-Running Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.1.3 Timer Capture Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.1.4 TOUT/TIN/PB6 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.1.5 Cascaded Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.1.5.1 Compare and Capture Using Cascaded Timers . . . . . . . . . . . . . . . . . . . . . . . . 12-4

12.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

12.2.1 Timer Control Registers 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

12.2.2 Timer Prescaler Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.2.3 Timer Compare Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.2.4 Timer Capture Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.2.5 Timer Counter Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.2.6 Timer Status Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

Chapter 13

Serial Peripheral Interface 1 and 2

13.1 SPI 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2 SPI 1 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2.1 Using SPI 1 as Master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2.2 Using SPI 1 as Slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2.3 SPI 1 Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.2.4 SPI 1 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.3 SPI 1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.3.1 SPI 1 Receive Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.3.2 SPI 1 Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.3.3 SPI 1 Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.3.4 SPI 1 Interrupt Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13.3.5 SPI 1 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.3.6 SPI 1 Sample Period Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

 Table of Contents ix

13.4 SPI 2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

13.5 SPI 2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12

13.5.1 SPI 2 Phase and Polarity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13

13.5.2 SPI 2 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13

13.6 SPI 2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.6.1 SPI 2 Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.6.2 SPI 2 Data Register Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.6.3 SPI 2 Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15

Chapter 14

Universal Asynchronous Receiver/Transmitter 1 and 2

14.1 Introduction to the UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.2 Serial Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2.1 NRZ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2.2 IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.2.3 Serial Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.3 UART Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3.1 Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3.1.1 TxFIFO Buffer Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.3.1.2 CTS Signal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.3.2 Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.3.2.1 Rx FIFO Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.3.3 Baud Rate Generator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.3.3.1 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.3.3.2 Non-Integer Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.3.3.3 Integer Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

14.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

14.4.1 UART 1 Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

14.4.2 UART 1 Baud Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.4.3 UART 1 Receiver Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

14.4.4 UART 1 Transmitter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14

14.4.5 UART 1 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

14.4.6 UART 1 Non-Integer Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.4.7 Non-Integer Prescaler Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19

14.4.8 UART 2 Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20

14.4.9 UART 2 Baud Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

14.4.10 UART 2 Receiver Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23

14.4.11 UART 2 Transmitter Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24

14.4.12 UART 2 Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

14.4.13 UART 2 Non-Integer Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

14.4.14 FIFO Level Marker Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29

Chapter 15

Pulse-Width Modulator 1 and 2

15.1 Introduction to PWM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1.1 PWM Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

x MC68VZ328 User’s Manual 

15.2 PWM 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.3 PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.3.1 Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.3.1.1 Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.3.1.2 D/A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.4.1 PWM 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.4.2 PWM 1 Sample Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.4.3 PWM 1 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.4.4 PWM 1 Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.5 PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.5.1 PWM 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.5.2 PWM 2 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

15.5.3 PWM 2 Pulse Width Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10

15.5.4 PWM 2 Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10

Chapter 16

In-Circuit Emulation

16.1 ICE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.1.1 Entering Emulation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.1.2 Detecting Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2

16.1.2.1 Execution Breakpoints vs. Bus Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.1.3 Using the Signal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.1.4 Using the Interrupt Gate Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.1.5 Using the A-Line Insertion Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2.1 In-Circuit Emulation Module Address Compare and Mask Registers. . . . . . . . . . 16-4

16.2.2 In-Circuit Emulation Module Control Compare and Mask Register . . . . . . . . . . . 16-6

16.2.3 In-Circuit Emulation Module Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.2.4 In-Circuit Emulation Module Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.3 Typical Design Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.3.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

16.3.2 Dedicated Debug Monitor Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

16.3.3 Emulation Memory Mapping FPGA and Emulation Memory. . . . . . . . . . . . . . . 16-12

16.3.4 Optional Extra Hardware Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.3.5 Optional Trace Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.4 Plug-in Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.5 Application Development Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14

Chapter 17

Bootstrap Mode

17.1 Bootstrap Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1

17.1.1 Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.1.2 Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.1.2.1 Data B-Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.1.2.2 Execution B-Record Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

 Table of Contents xi

17.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.1.4 Changing the Speed of Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3

17.1.5 System Initialization Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.1.6 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

17.1.7 Example of Instruction Buffer Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.2 Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.3 Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8

Chapter 18

Application Guide

18.1 Design Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.1 Determining the Chip ID and Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.2 8-Bit Bus Width Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1

18.1.3 Clock and Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.1.4 Bus and I/O Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

Chapter 19

Electrical Characteristics

19.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.1 CLKO Reference to Chip-Select Signals Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3.2 Chip-Select Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.3.3 Chip-Select Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

19.3.4 Chip-Select Flash Write Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

19.3.5 Chip-Select Timing Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master). . . . . . . . . . . . . . . . . . . . . . 19-8

19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master) . . . . . . . . . . . . . . . . . . . . 19-10

19.3.8 DRAM Hidden Refresh Cycle (Normal Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11

19.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode). . . . . . . . . . . . . . . . . . . . . . . 19-12

19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State) . . . . . . . . . 19-13

19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master). 19-14

19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master) . . 19-16

19.3.13 LCD Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17

19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . 19-19

19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . . . 19-20

19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency = 1) . . . . . . . . . . . 19-21

19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . 19-22

19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency = 1) . . . . . . . . . . . . . . . . . . 19-23

19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency = 1) . . . . . . 19-24

19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency = 1, Bit APEN of

SDRAM Power-down Register = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25

19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency = 1, Bit RM of DRAM

Control Register = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control

xii MC68VZ328 User’s Manual 

19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency = 1) . . . . . . . . 19-28

19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency = 1) . . . . . . . . . 19-29

19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency = 1) . . . . . . . . . . . . . . . 19-30

19.3.26 SPI 1 and SPI 2 Generic Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32

19.3.27 SPI 1 Master Using DATA_READY Edge Trigger. . . . . . . . . . . . . . . . . . . . . . . 19-32

19.3.28 SPI 1 Master Using DATA_READY Level Trigger . . . . . . . . . . . . . . . . . . . . . . 19-33

19.3.29 SPI 1 Master “Don’t Care” DATA_READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33

19.3.30 SPI 1 Slave FIFO Advanced by Bit Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33

19.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge . . . . . . . . . . . . . . . . . . . . . . . . . 19-34

19.3.32 Normal Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

19.3.33 Emulation Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

19.3.34 Bootstrap Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36

Chapter 20

Mechanical Data and Ordering Information

20.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

20.2 TQFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2

20.3 TQFP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.4 MAPBGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

20.5 MAPBGA Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.6 PCB Finish Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

Index

 Table of Contents xiii

xiv MC68VZ328 User’s Manual 

List of Figures

Figure 1-1 MC68VZ328 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Figure 1-2 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-3 Supervisor Programming Model Supplement. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 2-1 Signals Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2 Typical Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 3-1 MC68VZ328 System Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Figure 4-1 Clock Generation Module (CGM) Simplified Block Diagram . . . . . . . . . . . . . 4-3

Figure 4-2 Example of External Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-3 Initial Power-up Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 4-4 Power Control Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Figure 4-5 Power Control Operation in Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Figure 6-1 Size Selection and Memory Protection for CSB0 and CSB1. . . . . . . . . . . . . . . 6-3

Figure 7-1 DRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Figure 7-2 LCD Controller and DRAM Controller Interface. . . . . . . . . . . . . . . . . . . . . . . . 7-8

Figure 7-3 Data Retention for the Reset Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Figure 8-1 LCD Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Figure 8-2 LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths. . . . . . . . . . . . . . . . . . 8-4

Figure 8-3 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-4 Mapping Memory Data on the Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 9-1 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Figure 10-1 I/O Port Warm Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Figure 10-2 I/O Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Figure 10-3 Interrupt Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

Figure 11-1 Real-Time Clock Module Simplified Block Diagram . . . . . . . . . . . . . . . . . . . 11-1

Figure 12-1 General-Purpose Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Figure 12-2 Compare Routine for 32-Bit Cascaded Timers. . . . . . . . . . . . . . . . . . . . . . . . . 12-5

Figure 13-1 SPI 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

Figure 13-2 SPI 1 Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

Figure 13-3 SPI 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11

Figure 13-4 SPI 2 Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12

Figure 14-1 UART Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Figure 14-2 NRZ ASCII “A” Character with Odd Parity . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Figure 14-3 IrDA ASCII “A” Character with Odd Parity . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Figure 14-4 Baud Rate Generator Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

 List of Figures xv

Figure 15-1 PWM 1 and PWM 2 System Configuration Diagram . . . . . . . . . . . . . . . . . . . 15-1

Figure 15-2 PWM 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

Figure 15-3 Audio Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

Figure 15-4 PWM 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

Figure 16-1 In-Circuit Emulation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 16-1

Figure 16-2 Typical Emulator Design Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

Figure 16-3 Plug-in Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13

Figure 16-4 Application Development System Design Example. . . . . . . . . . . . . . . . . . . . 16-14

Figure 17-1 Bootstrap Mode Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

Figure 17-2 Bootloader Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

Figure 19-1 CLKO Reference to Chip-Select Signals Timing Diagram . . . . . . . . . . . . . . . 19-3

Figure 19-2 Chip-Select Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

Figure 19-3 Chip-Select Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

Figure 19-4 Chip-Select Flash Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 19-7

Figure 19-5 Chip-Select Timing Trim Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

Figure 19-6 DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Diagram. . . . . 19-9

Figure 19-7 DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Diagram . . . 19-10

Figure 19-8 DRAM Hidden Refresh Cycle (Normal Mode) Timing Diagram . . . . . . . . . 19-12

Figure 19-9 DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Diagram . . . . . . 19-12

Figure 19-10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Diagram . . . . 19-13

Figure 19-11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14

Figure 19-12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16

Figure 19-13 LCD Controller Timing Diagram (Normal Mode). . . . . . . . . . . . . . . . . . . . . 19-17

Figure 19-14 LCD Controller Timing Diagram (Self-Refresh Mode). . . . . . . . . . . . . . . . . 19-18

Figure 19-15 Page-Miss SDRAM CPU Read Cycle Timing Diagram . . . . . . . . . . . . . . . . 19-19

Figure 19-16 Page-Hit SDRAM CPU Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . 19-20

Figure 19-17 Page-Hit CPU Read Cycle for 8-Bit SDRAM Timing Diagram . . . . . . . . . . 19-21

Figure 19-18 Page-Miss SDRAM CPU Write Cycle Timing Diagram . . . . . . . . . . . . . . . . 19-22

Figure 19-19 Page-Hit SDRAM CPU Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . 19-23

Figure 19-20 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM Timing Diagram . . . . . 19-24

Figure 19-21 Page-Hit CPU Read Cycle in Power-down Mode Timing Diagram . . . . . . . 19-25

Figure 19-22 Exit Self-Refresh Due to CPU Read Cycle Timing Diagram. . . . . . . . . . . . . 19-26

Figure 19-23 Enter Self-Refresh Due to No Activity Timing Diagram. . . . . . . . . . . . . . . . 19-27

Figure 19-24 Page-Miss at Starting of LCD DMA for SDRAM Timing Diagram . . . . . . . 19-28

Figure 19-25 Page-Miss at Start and in Middle of LCD DMA Timing Diagram . . . . . . . . 19-29

Figure 19-26 Page-Hit LCD DMA Cycle for SDRAM Timing Diagram . . . . . . . . . . . . . . 19-30

Figure 19-27 SPI 1 and SPI 2 Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32

xvi MC68VZ328 User’s Manual 

Figure 19-28 SPI 1 Master Using DATA_READY Edge Trigger Timing Diagram . . . . . . 19-32

Figure 19-29 SPI 1 Master Using DATA_READY Level Trigger Timing Diagram . . . . . 19-33

Figure 19-30 SPI 1 Master “Don’t Care” DATA_READY Timing Diagram . . . . . . . . . . . 19-33

Figure 19-31 SPI 1 Slave FIFO Advanced by Bit Count Timing Diagram . . . . . . . . . . . . . 19-33

Figure 19-32 SPI 1 Slave FIFO Advanced by SS Rising Edge Timing Diagram . . . . . . . . 19-34

Figure 19-33 Normal Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

Figure 19-34 Emulation Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35

Figure 19-35 Bootstrap Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36

Figure 20-1 MC68VZ328 TQFP Pin Assignments—Top View . . . . . . . . . . . . . . . . . . . . . 20-2

Figure 20-2 MC68VZ328 TQFP Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

Figure 20-3 MC68VZ328 MAPBGA Pin Assignments—Top View. . . . . . . . . . . . . . . . . . 20-4

Figure 20-4 MC68VZ328 MAPBGA Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . 20-5

 List of Figures xvii

xviii MC68VZ328 User’s Manual 

List of Tables

Table 1-1 Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Table 1-2 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Table 2-1 Signal Function Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Table 3-1 Programmer’s Memory Map (Sorted by Address) . . . . . . . . . . . . . . . . . . . . . . . 3-2

Table 3-2 Programmer’s Memory Map (Sorted by Register Name) . . . . . . . . . . . . . . . . . 3-8

Table 4-1 CGM Clock Signal Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Table 4-2 PLL Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-3 WKSEL Field (PLLCR) Delay Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Table 4-4 PLL Frequency Select Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-5 Power Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

Table 5-1 System Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Table 5-2 Peripheral Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Table 5-3 ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Table 5-4 I/O Drive Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Table 6-1 Chip-Select and Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-2 Chip-Select Group A Base Address Register Description . . . . . . . . . . . . . . . . . 6-4

Table 6-3 Chip-Select Group B Base Address Register Description . . . . . . . . . . . . . . . . . 6-5

Table 6-4 Chip-Select Group C Base Address Register Description . . . . . . . . . . . . . . . . . 6-5

Table 6-5 Chip-Select Group D Base Address Register Description . . . . . . . . . . . . . . . . . 6-6

Table 6-6 Chip-Select Upper Group Base Address Register Description . . . . . . . . . . . . . 6-6

Table 6-7 Chip-Select Register A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Table 6-8 Chip-Select Register B Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-9 Chip-Select Register C Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Table 6-10 Chip-Select Register D Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Table 6-11 Emulation Chip-Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Table 6-12 Chip-Select Control Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

Table 6-13 Chip-Select Control Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Table 6-14 Chip-Select Control Register 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Table 7-1 DRAM Address Multiplexing Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

Table 7-2 16 Mbit SDRAM—256 (16-Bit) and 512 (8-Bit) Page Size . . . . . . . . . . . . . . . 7-5

Table 7-3 64 Mbit SDRAM—256 (16-Bit) and 512 (8-Bit) Page Size . . . . . . . . . . . . . . . 7-5

Table 7-4 128 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page Size . . . . . . . . . . . . . 7-6

Table 7-5 256 Mbit SDRAM—512 (16-Bit) and 1024 (8-Bit) Page Size . . . . . . . . . . . . . 7-6

Table 7-6 DRAM Memory Configuration Register Description . . . . . . . . . . . . . . . . . . . 7-12

 List of Tables xix

Table 7-7 DRAM Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-8 SDRAM Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Table 7-9 SDRAM Bank Address Programming Examples. . . . . . . . . . . . . . . . . . . . . . . 7-17

Table 7-10 SDRAM Power-down Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Table 8-1 Grey Palette Density. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

Table 8-2 LCD Screen Starting Address Register Description. . . . . . . . . . . . . . . . . . . . . 8-10

Table 8-3 LCD Virtual Page Width Register Description . . . . . . . . . . . . . . . . . . . . . . . . 8-11

Table 8-4 LCD Screen Width Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

Table 8-5 LCD Screen Height Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

Table 8-6 LCD Cursor X Position Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

Table 8-7 LCD Cursor Y Position Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

Table 8-8 LCD Cursor Width and Height Register Description. . . . . . . . . . . . . . . . . . . . 8-14

Table 8-9 LCD Blink Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15

Table 8-10 LCD Panel Interface Configuration Register Description . . . . . . . . . . . . . . . . 8-15

Table 8-11 LCD Polarity Configuration Register Description . . . . . . . . . . . . . . . . . . . . . . 8-16

Table 8-12 LACD Rate Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

Table 8-13 LCD Pixel Clock Divider Register Description . . . . . . . . . . . . . . . . . . . . . . . . 8-17

Table 8-14 LCD Clocking Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Table 8-15 LCD Refresh Rate Adjustment Register Description. . . . . . . . . . . . . . . . . . . . 8-18

Table 8-16 LCD Panning Offset Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19

Table 8-17 LCD Gray Palette Mapping Register Description . . . . . . . . . . . . . . . . . . . . . . 8-20

Table 8-18 PWM Contrast Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

Table 8-19 Refresh Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

Table 8-20 DMA Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

Table 9-1 Exception Vector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

Table 9-2 Interrupt Vector Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Table 9-3 Interrupt Vector Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

Table 9-4 Interrupt Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

Table 9-5 Interrupt Mask Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Table 9-6 Interrupt Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

Table 9-7 Interrupt Pending Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

Table 9-8 Interrupt Level Register Field Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19

Table 10-1 Dedicated I/O Functions of Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

Table 10-2 MC68VZ328 I/O Port Status During the Reset Assertion Time Length . . . . . 10-4

Table 10-3 Pull-up and Pull-down Resistors by Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-4 Port A Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Table 10-5 Port A Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

Table 10-6 Port A Pull-up Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

Table 10-7 Port B Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

xx MC68VZ328 User’s Manual 

Table 10-8 Port B Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Table 10-9 Port B Dedicated Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10

Table 10-10 Port B Pull-up Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

Table 10-11 Port B Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

Table 10-12 Port C Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

Table 10-13 Port C Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

Table 10-14 Port C Dedicated Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

Table 10-15 Port C Pull-down Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . 10-13

Table 10-16 Port C Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

Table 10-17 Port D Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16

Table 10-18 Port D Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

Table 10-19 Port D Dedicated Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17

Table 10-20 Port D Pull-up Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

Table 10-21 Port D Select Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

Table 10-22 Port D Polarity Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

Table 10-23 Port D Interrupt Request Enable Register Description. . . . . . . . . . . . . . . . . . 10-20

Table 10-24 Port D Keyboard Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . 10-20

Table 10-25 Port D Interrupt Request Edge Register Description . . . . . . . . . . . . . . . . . . . 10-21

Table 10-26 Port E Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

Table 10-27 Port E Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

Table 10-28 Port E Dedicated Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

Table 10-29 Port E Pull-up Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

Table 10-30 Port E Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23

Table 10-31 Port F Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

Table 10-32 Port F Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25

Table 10-33 Port F Dedicated I/O Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 10-26

Table 10-34 Port F Pull-up/Pull-down Enable Register Description . . . . . . . . . . . . . . . . . 10-27

Table 10-35 Port F Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27

Table 10-36 Port G Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28

Table 10-37 Port G Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29

Table 10-38 Port G Dedicated I/O Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 10-29

Table 10-39 Port G Pull-up Enable Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

Table 10-40 Port G Select Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

Table 10-41 Port J Direction Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

Table 10-42 Port J Data Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

Table 10-43 Port J Dedicated I/O Function Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . 10-32

Table 10-44 Port J Pull-up Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33

Table 10-45 Port J Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33

Table 10-46 Port K Direction Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34

 List of Tables xxi

Table 10-47 Port K Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35

Table 10-48 Port K Dedicated I/O Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 10-35

Table 10-49 Port K Pull-up/Pull-down Enable Register Description. . . . . . . . . . . . . . . . . 10-36

Table 10-50 Port K Select Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36

Table 10-51 Port M Direction Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37

Table 10-52 Port M Data Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38

Table 10-53 Port M Dedicated I/O Function Assignments. . . . . . . . . . . . . . . . . . . . . . . . . 10-39

Table 10-54 Port M Pull-up/Pull-down Enable Register Description. . . . . . . . . . . . . . . . . 10-39

Table 10-55 Port M Select Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40

Table 11-1 RTC Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

Table 11-2 RTC Hours, Minutes, and Seconds Register Description. . . . . . . . . . . . . . . . . 11-5

Table 11-3 RTC Day Counter Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

Table 11-4 RTC Alarm Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Table 11-5 RTC Day Alarm Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Table 11-6 Watchdog Timer Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Table 11-7 RTC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

Table 11-8 RTC Interrupt Status Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

Table 11-9 Real-Time Interrupt Frequency Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

Table 11-10 RTC Interrupt Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13

Table 11-11 Stopwatch Minutes Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

Table 12-1 Cascade Timer Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

Table 12-2 Timer Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6

Table 12-3 Timer Prescaler Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

Table 12-4 Timer Compare Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

Table 12-5 Timer Capture Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

Table 12-6 Timer Counter Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

Table 12-7 Timer Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

Table 13-1 SPI 1 Receive Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

Table 13-2 SPI 1 Transmit Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

Table 13-3 SPI 1 Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

Table 13-4 SPI 1 Interrupt Control/Status Register Description. . . . . . . . . . . . . . . . . . . . . 13-8

Table 13-5 SPI 1 Test Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

Table 13-6 SPI 1 Sample Period Control Register Description . . . . . . . . . . . . . . . . . . . . 13-11

Table 13-7 SPI 2 Data Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

Table 13-8 SPI 2 Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15

Table 14-1 Non-Integer Prescaler Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Table 14-2 Non-Integer Prescaler Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Table 14-3 Selected Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

Table 14-4 UART 1 Status/Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 14-10

xxii MC68VZ328 User’s Manual 

Table 14-5 UART 1 Baud Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

Table 14-6 UART 1 Receiver Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

Table 14-7 UART 1 Transmitter Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14

Table 14-8 UART 1 Miscellaneous Register Description . . . . . . . . . . . . . . . . . . . . . . . . 14-16

Table 14-9 UART 1 Non-Integer Prescaler Register Description . . . . . . . . . . . . . . . . . . 14-18

Table 14-10 UART 2 Status/Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 14-20

Table 14-11 UART 2 Baud Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

Table 14-12 UART 2 Receiver Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23

Table 14-13 UART 2 Transmitter Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24

Table 14-14 UART 2 Miscellaneous Register Description . . . . . . . . . . . . . . . . . . . . . . . . 14-26

Table 14-15 UART 2 Non-Integer Prescaler Register Description . . . . . . . . . . . . . . . . . . 14-28

Table 14-16 FIFO Level Marker Interrupt Register Description . . . . . . . . . . . . . . . . . . . . 14-29

Table 14-17 FIFO Level Marker Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30

Table 15-1 PWM 1 Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

Table 15-2 PWM 1 Sample Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

Table 15-3 PWM 1 Period Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

Table 15-4 PWM 1 Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

Table 15-5 PWM 2 Control Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

Table 15-6 PWM 2 Period Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

Table 15-7 PWM 2 Pulse Width Control Register Description . . . . . . . . . . . . . . . . . . . . 15-10

Table 15-8 PWM 2 Counter Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10

Table 16-1 ICE Module Address Compare and Mask Registers Description. . . . . . . . . . . 16-5

Table 16-2 ICE Module Control Compare Register Description . . . . . . . . . . . . . . . . . . . . 16-6

Table 16-3 ICE Control Mask Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

Table 16-4 ICE Module Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

Table 16-5 Emulation Mode Hard Coded Memory Locations . . . . . . . . . . . . . . . . . . . . . . 16-9

Table 16-6 ICE Module Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

Table 17-1 Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

Table 19-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

Table 19-2 Maximum and Minimum DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

Table 19-3 CLKO Reference to Chip-Select Signals Timing Parameters . . . . . . . . . . . . . 19-3

Table 19-4 Chip-Select Read Cycle Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

Table 19-5 Chip-Select Write Cycle Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

Table 19-6 Chip-Select Flash Write Cycle Timing Parameters . . . . . . . . . . . . . . . . . . . . . 19-7

Table 19-7 Chip-Select Timing Trim Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 19-8

Table 19-8 DRAM Read Cycle 16-Bit Access (CPU Bus Master) Timing Parameters. . . 19-9 Table 19-9 DRAM Write Cycle 16-Bit Access (CPU Bus Master) Timing Parameters . 19-11

Table 19-10 DRAM Hidden Refresh Cycle (Normal Mode) Timing Parameters . . . . . . . 19-12

Table 19-11 DRAM Hidden Refresh Cycle (Low-Power Mode) Timing Parameters . . . . 19-13

 List of Tables xxiii

Table 19-12 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access Timing Parameters . . 19-14 Table 19-13 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)

Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15

Table 19-14 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)

Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16

Table 19-15 LCD Controller Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

Table 19-16 Timing Parameters for Figure 19-15 Through Figure 19-26 . . . . . . . . . . . . . 19-31

Table 19-17 Timing Parameters for Figure 19-27 Through Figure 19-32 . . . . . . . . . . . . . 19-34

Table 19-18 Timing Parameters for Figure 19-33 Through Figure 19-35 . . . . . . . . . . . . . 19-36

Table 20-1 MC68VZ328 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

xxiv MC68VZ328 User’s Manual 

List of Examples

Example 4-1 Configuring the PLLCLK Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Example 4-2 Shutdown Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Example 6-1 Unprotected Memory Size Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Example 6-2 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Example 7-1 Calculating REF Field Values for Refresh Times . . . . . . . . . . . . . . . . . . . . . . 7-13

Example 8-1 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

Example 14-1 Sample Divisor Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

Example 17-1 System Initialization Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

Example 17-2 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5

Example 17-3 Using Instruction Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

 List of Examples xxv

xxvi MC68VZ328 User’s Manual 

About This Book

This user’s manual describes the features and operation of the MC68VZ328 (DragonBall™ VZ) microprocessor, t he thi rd ge neration of t he Dr agonBal l initialize, configure, and program the MC68VZ328. The manual presumes basic knowledge of 68000 architecture.

family of products. It prov ides t he det ails of how to

Audience

The MC68VZ328 user’s manual is intended to provide a design engineer with the necessary data to successfully in tegrate the MC68 VZ328 into a wide vari ety of appl icatio ns. It is assumed that the reader ha s a good working knowledge of the 68000 CPU. For programming information about the 68000, see the documents listed in the Suggested Reading section of this preface.

Organization

The MC68VZ328 user’s manua l is o rganized into 20 chapter s that cover t he oper ation an d progra mming of the DragonBall VZ device. Summaries of the chapters follow.

Chapter 1 Introduction: This chapter contains a device overview, system block diagrams,

and an operational overview of 68000 CPU operation.

Chapter 2 Signal Descriptions: Thi s chapter contains lis tings of the MC68VZ328 input an d

output signals, organized into functional groups.

Chapter 3 Memory Map: This chapter summarizes the memory organization,

programming information, and registers’ addresses and reset values.

Chapter 4 Clock Generation Module and Power Contr ol Module: Thi s chapter pro vides

detailed information about the operation and programming of the clock generation module as well as the recommended circuit schematics for external clock circuits. It als o describes and provide s programming in formation ab out the operation of the power control module and the system power states.

Chapter 5 System Control: This chapter describes the operation of and programming

models for the system control, peripheral control, ID, an d I/O drive control registers.

Chapter 6 Chip-Select Logic: This chapter describes the operation and programming of the

chip-select logic. It includes information related to the operation of the DRAM controller and other memory-related applications.

Chapter 7 DRAM Controller: The operati on and progr amming of the DRAM cont roller is

described in this chapter. This module p rovides a glueles s interface to 8-b it or 16-bit DRAM supporting EDO RAM, F ast Page Mo de, and synchronous DRAM.

Chapter 8 LCD Controller: This chapter describes the operation and programming of the

LCD controller, which provides display data for external LCD drivers or for an LCD panel.

 About This Book xxvii

Chapter 9 Interrupt Controller: This chapter provides a description and operational

considerations for interrupt controller operation. It includes a description of the vector generator and pen and keyboard interrupts.

Chapter 10 I/O Ports: This chapter covers all 76 GPIO lines found in the MC68VZ328.

Because each pin is individually configurable, a detailed description of the operation of and programming information for each pin is provided.

Chapter 11 Real-Time Clock: This chap ter describes th e operation of the real-time clock

(R TC) module, which is composed of a prescal er, ti me-of-day (TOD) clock, TOD alarm, programmable real-ti me interrup t, w atchdog timer, and min ute stopw atch as well as co ntrol registers and bus interface hardware.

Chapter 12 General-Purpose T i mers : This chapter describes the two 16-bit timers that can

be used as both watchdogs and alarms. It also describes how the timers can be combined into a single 32-bit timer.

Chapter 13 Serial Peripheral Interface 1 and 2: This chapter describes the features of the

DragonBall VZ’s two serial peripheral interfaces and how they are used to communicate with external devices.

Chapter 14 Universal Asynchronous Receiver/Transmitter 1 and 2: The tw o universal

asynchronous recei ver/ transmitter (U AR T) por ts allo w the incor poration of se rial communication in existing and new designs. This section describes how data is transported in character blocks using the standard “start-stop” format. It also discusses how to configure and program the UART modules.

Chapter 15 Pulse-Width Modulat or 1 and 2: This chapter describes both pulse-width

modulators. Programming information is also provided.

Chapter 16 In-Circuit Emulation: This cha pter describes the in-circui t emulation (ICE)

module and how it is used to support low-cost emulator designs for the MC68VZ328 microprocessor.

Chapter 17 Bootstrap Mode: The operation of bootstrap models is described in detail in this

chapter. This chapter describes programming information necessary to allow a system to initialize a target system and download a program or data to the target system’s RAM using the UART 1 or UART 2 controller.

Chapter 18 Application Guide: This chapter c ontains info rmation that will assist dur ing the

integration of the MC68VZ328 into an existing or a new design. It includes a design checklist and instructions for using the MC68VZ328 Application Development System (ADS) board to get started with the design process.

Chapter 19 Electrical Characteristics: This chapter describes the electrical characteristics

of the MC68VZ328 integrated processor.

Chapter 20 Mechanical Data and Ordering Information: This chapter provides

mechanical data, including illustrations, and ordering information.

xxviii MC68VZ328 User’s Manual 

1.1 Features of the MC68VZ328

The features of the DragonBall VZ include the following:

• Static FLX68000 CPU—identical to the MC68EC000 microprocessor — Full compatibility with MC68000 and MC68EC000 — 32-bit internal address bus — Static design that allows processor clock to be stopped to provide power savings — 5.4 MIPS performance at 33 MHz processor clock — External M68000 bus interface with selectable bus sizing for 8-bit and 16-bit data ports

• System integration module (SIM) that incorporates many functions typically related to external array logic, reducing parts counts in design, with functions that include the following:

— System configuration and programmable address mapping — Glueless interface to SRAM, DRAM, SDRAM, EPROM, and flash memory — Eight prog r ammable chip-selects with wait-state generation logic — Four programmable interrupt I/Os, with keyboard interrupt capability

1-2 MC68VZ328 User’s Manual 

Features of the MC68VZ328

— Five general-purpose, programmable edge/level/polarity interrupt IRQs — Other programmable I/O, multiplexed with peripheral functions of up to 76 GPIO lines — Programmable interrupt vector response for on-chip peripheral modules — Low-power mode control

• DRAM controller — Support for CAS — Support for 8-bit and 16-bit port DRAM and synchronous DRAM — EDO RAM or automatic Fast Pa ge Mode for LCD access — Programmable refresh rate — Support for up to two banks of DRAM and EDO RAM — Programmable column address size

• 76 GPIO lines grouped into 10 ports

• Two UART ports

• Two serial peripheral interface (SPI) p orts

• Two 16-bit general-purpose counters/timers — Automatic interrupt generation — 30 ns resolution at 33 M Hz system clock — Timer input/output pin

• Real-time clock/sampling timer — Separate power supply for the RTC — One programmable alarm — Capability of counting up to 512 days

-before-RAS refresh cycles and self-refresh mode DRAM

— Sampling timer with selectable frequency (4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz, 256 Hz, 512 Hz,

1kHz)

— Interrupt generation for digitizer sampling or keyboard debouncing

• LCD controller — Software-progr ammable screen size (up to 640

and color STN panels

— Capability of dire ctly driving popul ar LCD drive rs and modules from Motorola, Shar p, Hitachi,

Toshiba, and numerous other manufacturers — Support for up to 16 gray levels out of a palette of 16 density levels — Utilization of system memory as display memory — LCD contrast control using 8-bit PWM

• Two pulse-width modulator (PWM) modules — Audio effects support — 16- and 8-bit resolution — 5-byte FIFO that provides more fl exibility on perfo rmance — Sound and melody generation

× 512) to support single ( nonsplit) monochrome

 Introduction 1-3

CPU

• Built-in emulation function — Dedicated memory space for emulator debug monitor with chip-select — Dedicated interrupt (interrupt level 7) for in-circuit emulation (ICE) — One address-signal comparator and one control-signal comparator, with masking to support

single or multiple hardware execution — Breakpoint — One breakpoint instruction insertion unit

• Bootstrap mode function — Capability to initialize system and download programs and data to system memory through

UART — Acceptance of execution command to run program stored in system memory — 8-byte-long instruction buffer for 68000 instruction storage and execution

• Power management — Fully static HCMOS technology — Programmable clock synthesizer using 32.768 kHz or 38.4 kHz external crystal for full

frequency control — Low-power stop capabilities — Modules that can be individually shut down — Operation from DC to 33 MHz (processor clock) — Operating voltage of 2.7 V to 3.3 V — Compact 144-lead thin quad flat pack (TQFP) and MAPBGA

1.2 CPU

The FLX68000 CPU in the MC68VZ328 is an update d implementation of t he 68000 32-bit micr oprocessor architecture. The main features of the CPU are the following:

• Low-power, fully static HCMOS implementation

• 32-bit address bus and 16-bit data bus

• Sixteen 32-bit data and address registers

• 56 powerful instruction types that support high-level development languages

• 14 addressing modes and 5 main data types

• Seven priority levels for interrupt control

The CPU is completely code compatible with other members of the M68000 families, which means it has access to a broad base of established real-time kernels, operating systems, languages, applications, and development tools.

1-4 MC68VZ328 User’s Manual 

CPU

1.2.1 CPU Programming Model

The CPU has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2. The first eight

registers (D7–D0) are data registers that are used for byte (8-bit), word (16-bit), and long-word (32-bit) operations. When being used to manipulate data, the data re gis te rs a ff ect the sta tus reg is ter (SR) . The next seven registers ( A6–A0) and the user stack poin ter (USP) can function as software stack pointers a nd bas e address registers. The se registe rs can be used for wor d and long-word operations , but they do not affe ct the status register. The D7–D0 and A6–A0 registers can be used as index registers.

31 16 15

31 1615 0

31 0

Figure 1-2. User Programming Model

D0 D1 D2 D3 D4 D5 D6 D7

0151631

A0 A1 A2 A3 A4 A5 A6

PC Program Counter

Data Registers

Address Registers

User Stack PointerA7 (USP)

Status RegisterSR

In supervisor mode, t he upper byte of the status register and the s upervisor stack poin te r ( SSP) can also be programmed, as shown in Figure 1-3.

31 1615 0

SR Status Register

Figure 1-3. Supervisor Programming Model Supplement

Supervisor StackA7 (SSP) Pointer

The status register contains the interrupt mask with seven available levels, as well as an extend (X), negative (N), zero (Z), overflow (V), and carry (C) condition code. The T bit in dic at es when the processor is in trace mode, and the S bit indicates when it is in supervisor o r user mode.

 Introduction 1-5

CPU

1.2.2 Data and Address Mode Types

The CPU supports five types of data and six main types of address modes. The five types of data are bits, binary-coded decimal (BCD) digits, bytes, words, and long words. The six types of address modes are shown in Table 1-1.

Table 1-1. Address Modes

Address Mode Syntax

• Data register direct

• Address register direct

Absolute data address

• Absolute short

• Absolute long

Program counter relative address

• Relative with offset

• Relative with index offset

• Register indirect

• Postincrement register indirect

• Predecrement register indirect

• Register indirect with offset

• Indexed register indirect with offset

Dn An

xxx.W

xxx.L

(PC, Xn)

(An) (An)+ –(An)

(An, Xn)

(PC)

(An)

Immediate data address

• Immediate

• Quick immediate

Implied address

• Implied register SR/USP/SP/PC

Note: Dn = Data register An = Address register Xn = Address or data register used as index register SR = Status register PC = Program counter SP = Stack pointer USP = User stack pointer ( ) = Effective address

= 8-bit offset (displacement)

= 16-bit offset (displacement)

#xxx = Immediate data

#xxx

#1–#8

1.2.3 FLX68000 Instruction Set

The FLX68000 CPU instruction set supports high-level languages that facilitate programming. Almost every instruction o perates o n bytes, word s, and long wor ds, and mo st of them can us e any of th e 14 addres s modes. Combining instruct ion typ es, dat a types , and addres s modes pr ovides acces s to ove r 1,000 po ssibl e instructions. Thes e instr uctions, shown in Table 1-2 on page 1-7, include signed and unsi gned multipl y and divide, quick arithmetic operations, binary-coded decimal (BCD) arithmetic, and expanded operations (through traps).

1-6 MC68VZ328 User’s Manual 

Table 1-2. Instruction Set

Mnemonic Description Mnemonic Description

ABCD Add decimal with extend MOVEM Move multiple registers ADD Add MOVEP Move peripheral data ADDA Add address MOVEQ Move quick ADDQ Add quick MOVE from SR Move from status register ADDI Add immediate MOVE to SR Move to status register ADDX Add with extend MOVE to CCR Move to condition codes AND Logical AND MOVE USP Move user stack pointer ANDI AND immediate MULS Signed multiply ANDI to CCR AND immediate to condition codes MULU Unsigned multiply ANDI to SR AND immediate to status register NBCD Negate decimal with extend ASL Arithmetic shift left NEG Negate

CPU

ASR Arithmetic shift right NEGX Negate with extend Bcc Branch conditionally NOP No operation BCHG Bit test and change NOT One’s-complement

BCLR Bit test and clear OR Logical OR BRA Branch always ORI OR immediate BSET Bit test and set ORI to CCR OR immediate to co ndi tio n code s BSR Branch to subroutine ORI to SR OR immediate to status register BTST Bit test PEA Push effective address CHK Check register against bounds RESET Reset external devices CLR Clear operand ROL Rotate left without extend CMP Compare ROR Rotate right without extend CMPA Compare address ROXL Rotate left with extend CMPM Compare memory ROXR Rotate right with extend CMPI Compare immediate RTE Return from exception DBcc Test conditionally, decrement, and branch RTR Return and restore DIVS Signed divide RTS Return from subroutine DIVU Unsigned divide SBCD Subtract decimal with extend EOR Exclusive OR Scc Set conditional

 Introduction 1-7

Modules of the MC68VZ328

Table 1-2. Instruction Set (Continued)

Mnemonic Description Mnemonic Description

EORI Ex clusive OR immediate STOP Stop EORI to CCR Exclusive OR immediate to condition codes SUB Subtract EORI to SR Exclusive OR immediate to status register SUBA Subtract address EXG Exchange registers SUBI Subtract immediate EXT Sign extend SUBQ Subtract quick JMP Jump SUBX Subtract with extend JSR Jump to subroutine SWAP Swap data register halves LEA Load effective address TAS Test and set operand LINK Link stack TRAP Trap LSL Logical shift left TRAPV Trap on overflow LSR Logical shift right TST Test MOVE Move UNLK Unlink MOVEA Move address

1.3 Modules of the MC68VZ328

In addition to the powerful 68000 processor, the DragonBall VZ contains a wide variety of peripheral interface and control modules. The following subsections provide brief descriptions of these modules and how they operate.

1.3.1 Memory Controller

The memory controller provide s a glueless int erface to most memory chips on the market. It suppor ts flash, ROM, SRAM, different DRAM types (EDO RAM and Fast Page Mode ), a nd synchronous DRAM. Either one or two banks of DRAM may be used, and each bank can be a maximum of 32 Mbyte. For a more complete explanation of how memory is configured and controlled, see Chapter 3, “Memory Map.”

1.3.2 Clock Generation Module and Power Control Module

The module containing the clock synthesizer operates with either an external crystal or an external oscillator to provide a stable clock source for the internal clock generation module (CGM). The output frequency can be adjusted by writing to the CGM frequency select register. The CGM can be disabled to shut down the system clo ck divider chain fo r maximum power s aving, whil e the real- time cloc k (RTC) and DRAM controller remain act ive. The po wer control module can be conf igured to control the CPU cycles t o optimize power consumption. The power control module offers three power-saving modes: normal, doze,

1-8 MC68VZ328 User’s Manual 

Modules of the MC68VZ328

and sleep. When in sleep mode, the CGM wakes up aut omaticall y when any un maske d exter nal or inte rnal

interrupt occurs. Se e Chapter 4, “Clock Generation Module and Power Control Module,” for more detaile d information.

1.3.3 System Control

The primary function of the system control module is to provide configuration control of several other modules in the DragonBall VZ. These registers grant permission for access to many of the internal peripheral registers. In addition, the module controls address space of the internal peripheral registers and the bus time-out control and status (bus error generator). System control also is used to program the drive current of the GPIO lines. See Chapter 5, “S ystem Control,” for more infor mation.

1.3.4 Chip-Select Logic

The MC68VZ328 provides eight programmable general-purpose chip-select signals to allow the selection of a wide variety of memory or external peripherals. Each chip-select signal provides a write-protect option, internal and external DTACK generation, and 8-bit and 16-bit data port size selection. For more detailed information about using the chip-select logic, see Chapter 6, “Chip-Select Logic.”

1.3.5 DRAM Controller

The DRAM controller provides a glueless interface for either 8-bit or 16-bit DRAM. It supports EDO RAM, Fast Page Mode, and synchronous DRAM. The DRAM controller provides row address strobe

) and column address strobe (CAS ) sig nals fo r up to a maxi mum of two ba nks of DRAM. In addi tion

(RAS to controlling DRAM, the DRAM controller supports access for LCD controller burst accesses. See Chapter 7, “DRAM Controller,” for more information about this module.

1.3.6 LCD Controller

The LCD controller provides display data for exte rnal LCD drivers or for an LCD panel. The LCD controller fetches display data directly from system memory through periodic DMA transfer cycles. For this reason, an understandi ng of the DRAM controller is recommended. For more information, ple ase refer to Chapter 7, “DRAM Controller,” as well as Chapter 8, “LCD Controller.”

1.3.7 Interrupt Controller

The interrupt controller prioritizes internal and external interrupt requests and generates a vector number during the CPU inter ru pt-acknowledge cycle. I nterrupt nesting is al so provided so that an i nterrupt service routine of a lower-priority interrupt may be su spended by a higher-priority interrupt request. The o n-chip interrupt controller features prioritized interrupts, a fully nested interrupt environment, programmable vector generatio n, and unique vector number generati on for each inte rrupt lev el. For addit ional infor mation about this module, see Chapter 9, “Interrupt Controller.”

 Introduction 1-9

Modules of the MC68VZ328

1.3.8 General-Purpose I/O (GPIO) Lines

The MC68VZ328 supports a maximum of 76 GPIO lines grouped together in ports A–G, J, K, and M. These ports can be configured as GPIO pins or dedicated peripheral interface pins. Each pin can be independently progr ammed as a GPIO pin ev en when other pins rela te d to that on- chip per iphera l are u sed as dedicated pins. For detailed information about programming these GPIO lines, see Chapter 10, “I/O Ports.”

1.3.9 Real-Time Clock

A real-time clock provides the time of day with 1-second resolution. Using an external crystal (either

32.768 kHz or 38.4 kHz) as a clock source, it keeps time as long as power i s applied t o the chip, e ven when it is in sleep or doze mode. The watchdog clock timer protects against system failures by providing a way of escape from unexpected input conditions, external events, or programming errors. Once started, this timer must be cleared by software on a regular basis so that it never reaches its time-out value. When it does reach its time-out value, the watchdog timer assumes that a system failure has occurred and the software watchdog logic resets or interrupts the CPU. For detailed information about configuring and programming this module, refer to Chapter 11, “Real-Time Clock.”

1.3.10 General-Purpose Timer

The MC68VZ328 has two 16-bit timers that can be used in various modes to capture the timer value with an external event, to trigger an external event or interrupt when the timer reaches a set value, or to count external events. Each timer has an 8-bit prescaler to allow a programmable clock input frequency to be derived from the system clock. The two timers can also be cascaded together as one 32-bit timer. This module is described in detail in Chapter 12, “General-Purpose Timers.”

1.3.11 Serial Peripheral Interfaces (SPI)

The MC68VZ328 contains two serial peripheral interface (SPI) modules, SPI 1 and SPI 2. The serial peripheral interfaces are mainly used for controlling external peripherals. The passed data is synchronized with the SPI clock, and it is transmitted and received with the same SPI clock. One SPI module (SPI 2) only operates in master mode, which initiates SPI transfers from the MC68VZ328 to the peripheral. The other SPI (SPI 1) may be configured as either master or slave. Chapter 13, “Serial Peripheral Interface 1 and 2,” provides detailed information about the configuration and operation of the SPIs.

1.3.12 Universal Asynchronous Receiver/Transmitter (UART)

Modules

The two UART ports in the MC68VZ328 may be used to communicate with external serial devices. UART 1 is identical to the UART i n the Drag onBal l EZ processor, while UART 2 represen ts an enh anc ed version of UART 1. One of the enhancements to the UART 2 design consists of an enlarged RxFIFO and TxFIFO to reduce the number of software interr upt s. An improv ement to bot h UARTs is the sys te m clock input frequency, which is 33.16 MHz, doubling the 16.58 MHz frequency of the MC68EZ328. For a

33.16 MHz system clock, software written for the MC68EZ328 version of the chip is not compatible

unless the divider and prescaler are adjusted to compensate for the increased clock speed. For more information about the programming and configuration of these two modules, see Chapter 14, “Universal Asynchronous Receiver/Transmitter 1 and 2.”

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Modules of the MC68VZ328

1.3.13 Pulse-Width Modulators (PWM)

The MC68VZ328 has two pulse-width modulator s (PWMs). Each of the pul se-wid th modulat ors has thr ee

modes of operation— playba ck, t one, a nd digital -to- analog (D/A) conve rsion . Us ing t hese three modes, the PWM can be used to play back high-quality digital sounds, produce simple tones, or convert digital data into analog waveforms. The 8-bit PWM contains a 5-byte FIFO that enhances the system performance by reducing the numb er of int errupt s to the CPU. The 16-bit PWM provi des h igher reso lutio n for bett er s ound quality. Users can enable both PWMs at the sa me time to genera te a mixed PWMO signa l. See Chapter 15, “Pulse-Width Modulator 1 and 2,” for more detailed information about the configuration and operation of these devices.

1.3.14 In-Circuit Emulation Module

The in-circuit emulati on module is designed fo r low-cost emulat or development pu rposes. System me mory space, which is 0xFFFC0000 t o 0xFFFCFFFF, is covered by the EMUCS the emulator debug monitor. However, the EMUCS system I/O port. Keep in mind that if the monitor ROM is selected, the system must boot up in emulator mode. Refer to Chapter 16, “In-Circuit Emulation,” for more details.

signal can be used to select the monitor ROM or

signal and primar ily dedi cated to

1.3.15 Bootstrap Mode

The bootstra p mode is design ed to allow the initialization of a target syst em and the ability to downloa d programs or data to the target system RAM using either the UART 1 or UART 2 controller. See Chapter 14, “Universal Asynchronous Receiver/Transmitter 1 and 2,” for information on operating and programming the UART controllers. Once a program is downloaded to the MC68VZ328, it can be executed, providin g a simple debugging env ironment for fail ure analys is and a chan nel to up date progr ams stored in flash memory. Simple hardware debug func tions may be performed on the t arget s ystem using the bootstrap utility program BBUGV.EXE, which is available on the following World Wide Web site: http://www.Motorola.com/DragonBall. See Chapter 17, “Bootstrap Mode,” for more information about this mode.

 Introduction 1-11

Modules of the MC68VZ328

1-12 MC68VZ328 User’s Manual 

Chapter 2

Signal Descriptions

This chapter describes the MC68VZ328’s input and output signals, which are organized into functional groups, as illustrated in Figure 2-1 on page 2-2. The MC68VZ328 uses a standard M68000 bus to communicate with on-chip and external peripherals. This single continuous bus exists both on and off the chip. CPU read cycles to internal memory- ma pped r egi st er s of the device ar e i nvi si bl e on the external bus, but write cycles to internal or external memory-mapped locations are visible.

 Signal Descriptions 2-1

Signals Grouped by Function

PA[7:0]/D[7:0]

MA[15:0/A[16:1]

PG0/BUSW/DTACK

PK[2:1]/UDS/LDS/RW

PF[6:3]/A[23:20]

PF2/CLKO

PF1/IRQ5 PD0/INT0

PD1/INT1 PD2/INT2

PD3/INT3 PD4/IRQ1 PD5/IRQ2 PD6/IRQ3 PD7/IRQ6

PG2/EMUIRQ

PG3/HIZ/P/D PG4/EMUCS

PG5/EMUBRK

D[15:8]

A[19:17]

PG1/A0

/LB

LWE

UWE/UB

EXTAL

XTAL

RESET

Port A

Port F

Port D

Port G

FLX68000

Static

CPU

8/16-Bit

68000

Bus

Interface

System

Integration

Module

Interrupt

Controller

Clock

Synthesizer

Power

Control

Real-Time

Clock

Processor

Control

Emulation

Bootstrap

Voltage

Regulator

Memory

Controller

Chip-Select

16-Bit Timer

8/16-Bit

PWM

16-Bit Timer

68000 Internal Bus

LCD

Controller

Master

SPI

UART with

IRDA1.0

UART

M/S SPI

with FIFO

LV V

DD SS

Port M

Port B

Ports C, F, & KPort EPorts J & K

PM0/SDCLK PM1/SDCE PM2/DQMH PM3/DQML PM4/SDA10 PM5/DMOE

CSA0 PF7/CSA1

PB0/CSB0 PB1/CSB1/SDWE PB2/CSC0/RAS0 PB3/CSC1/RAS1 PB4/CSD0/CAS0 PB5/CSD1/CAS1

PB6/TOUT/TIN

PB7/PWMO1

PC[3:0]/LD[3:0] PC4/LFLM PC5/LLP PC6/LCLK PC7/LACD PF0/LCONTRAST PK[7:4]/LD[7:4]

PE0/SPITXD PE1/SPIRXD PE2/SPICLK2 PE3/DWE PE4/RXD1 PE5/TXD1 PE6/RTS1 PE7/CTS1

PJ0/MISO PJ1/MOSI PJ2/SPICLK1 PJ3/SS PJ4/RXD2 PJ5/TXD2 PJ6/RTS2 PJ7/CTS2 PK0/DATA_READY/PWMO2

/UCLK

Figure 2-1. Signals Grouped by Function

2.1 Signals Grouped by Function

Table 2-1 on page 2-3 groups the MC68VZ328 signals according to their function.

2-2 MC68VZ328 User’s Manual 

Table 2-1. Signal Function Groups

Function Group Signals

Signals Grouped by Function

Number of Pins

TQFP PBGA

Power V Ground V Regulator output LV Clocks/PCIO XTAL, EXTAL, CLKO/PF2 3 3 System control RESET Address bus/PFIO PF[3:6]/A[23:20], A[19:14], A0/PG1,

Lower data bus/PAIO PA[7:0]/D[7:0] 8 8 Upper data bus D[15:8] 8 8 Bus control/PCIO/PEIO/

PKIO Interrupt controller/PMIO INT0/PD0, INT1/PD1, INT2/PD2, INT3/PD3,

LCD controller/PCIO LACD/PC7, LCLK/PC6, LLP/PC5, LFLM/PC4,

MA[15:0]/A[16:1]

BUSW/DTACK PE3/DWE

/PD4, IRQ2/PD5, IRQ3/PD6, IRQ6/PD7,

IRQ1 IRQ5

/PF1

LD[7:4]/PK[7:4], LD[3:0]/PC[3:0], LCONTRAST/PF0

/PG0, OE, LWE/LB, UWE/UB,

/UCLK, PK2/LDS, PK3/UDS, PK1/RW

16 28

24 24

13 13

UART1/PEIO, UART2/PJIO PE4/RXD1, PE5/TXD1, PE6/RTS1

PJ4/RXD2, PJ5/TXD2, PJ6/RTS2 Timer/PBIO TOUT/TIN/PB6 1 1 Pulse-width modulator/PBIO PWMO1/PB7 (PM5/DATA_READY/PWMO2) 1 1 Master SPI/PEIO, config-

urable SPI/PJIO/PKIO

Chip-select, EDO RAM/PBIO, PMIO

SDRAM/PMIO PM0/SDCLK, PM1/SDCE, PM2/DQMH,

Emulator pins EMUIRQ/PG2, EMUBRK/PG5, HIZ/P/D/PG3,

No connect pins NC 4 0

SPITXD/PE0, SPIRXD/PE1, SPICLK2/PE2,

PJ0/MOSI, PJ1/MISO, PJ2/SPICLK1, PJ3/SS,

PK0/DATA_READY

[1:0]/PF7, CSB[1:0]/PB[1:0]/SDWE,

CSA

CSC

[1:0]/PB[3:2]/RAS[1:0], [1:0]/PB[5:4]/CAS[1:0], PM5/DMOE

CSD

PM3/DQML, PM4/SDA10, (SDWE, SDCAS[1:0],

SDRAS

nals

EMUCS

[1:0] )—multiplexed with chip-select sig-

/PG4

/PWMO2

, PE7/CTS1,

, PJ7/CTS2

 Signal Descriptions 2-3

Clock and System Control Signals

2.2 Power and Ground Signals

The MC68VZ328 microprocessor has three types of power pins. They are VDD, VSS, and LVDD.

•V

—External power supply to drive all I/O pins and for the internal voltage regulator. It is

recommended to place a 0.1 µF bypass capacitor close to each of these pins.

•V

•LV

—Signal return pin for both digital and analog circuits.

—Internal v oltage regu lator output s ignal that is used b y the internal circuitry. The L VDD pins

should not be used as an external circuit power supply due to current supply limitations. Each package has unique bypass capacitor requirements. The TQFP package requires that an external bypass capacito r circuit of 0.01

µF and 0.0001 µF (in parallel) be placed clo se to each of the LV

pins, except pin 35, which requires a 270 nF and a 0.0001 µF bypass capacitor. The PBGA has a single LV

pin (M1) requiring only a 270 nF and a 0.0001 µF bypass capacitor.

NOTE:

For maximum noise immunity, ensure that external bypass capacitors are placed as close to the pins as possible.

2.3 Clock and System Control Signals

There are four clock and system control signals.

• EXT AL—External Clock/Crys tal. This i nput signal con nects to th e e xternal lo w freq uency c rystal. The MC68VZ328 microprocessor supports both a 32.768 kHz and a 38.4 kHz crystal frequency. For a 32.768 kHz input, the internal phase-locked loop generates a PLLCLK signal that passes through two prescalers, and the resulting output (DMACLK and SYSCLK) clock is 16.58 MHz. Figure 2-2 illustrates how a crystal is usually connected to the MC68VZ328. For specific circuit design values, see Figure 4-2 on page 4-4.

32.768 kHz or 38.4 kHz

EXTAL

Figure 2-2. Typical Crystal Connection

XTAL

• XTAL—Crystal. This output signal connects the on-chip oscillator output to an external crystal.

• CLKO/PF2—Clock Out or bit 2 of Port F . This output clock signal is derive d from the on-chip clock oscillator and is internally connected to the clock output of the internal CGM. This signal is provided for external reference. The outp ut can be disa bled in the PLL control regis ter to reduce power consumption and electromagnetic emission. See Section 4.4.1, “PLL Control Register,” on page 4-8 for more information. The CLKO/PF2 signal defaults t o t he Port F pin 2 in put sig nal . Fo r detailed information, refer to Section 10.4.7.3, “Port F Dedicated I/O Functions,” on page 10-26.

ESET—Reset. This active low, Schmitt trigger input signal resets the entire MC68VZ328

•R processor (CPU and peripherals). The threshold of this Schmitt trigger device is 1.2 V high and

0.8 V low. Af ter the MC68VZ328 po wers up, this re set input signa l should be dri ven lo w for at le ast

2-4 MC68VZ328 User’s Manual 

Data Bus Signals

1.2 s before its voltage is higher than 1.2 V to ensure that the crystal oscill ator star ts and stabil izes. See Section 4.3.1, “CLK32 Clock Signal,” on page 4-4 for details about selecting circuit values.

This signal is inactive while the CPU is executing the RESET instruction.

NOTE:

When an R/C circuit is being used to generate the RESET signal to the MC68VZ328, the R/C circuit must be placed as close to the chip as possible.

2.4 Address Bus Signals

The address bus pins A[23:0] are the address lines driven by the CPU or LCD controller for panel refresh DMA. In sleep mode, all address signals are in an active state of the last bus cycle. Refer to Section 4.5.1.4, “Sleep Mode,” on page 4-12 for more detailed information.

• A0/PG1—Address 0 or Port G bit 1. After system reset, this signal defaults to A0.

• MA[15:0]/A[16:1]—Multiplexed DRAM bits 15–0 or Address bits 16–1. These address output lines are multiplexed with the DRAM row and column address signals. The MA signal is selected on DRAM access cycles.

• A[19:17]—Address lines 19–17.

• A[23:20]/PF[6:3]—Address bit s 23–20 or Po rt F bits 6 –3. These a ddress lines are mult iplex ed with Port F. These signals default to address functions after reset.

2.5 Data Bus Signals

The flexible data bus interface design of the MC68VZ328 microprocessor allows programming of the lower byte of the data bus (in an 8-bit-only system) to operate as general-purpose I/O signals. In sleep mode, all of the data bus pins (D15–D0) are individually pulled up with 1-megaohm resistors. Refer to Section 4.5.1.4, “Sleep Mode,” on page 4-12 for more detailed information.

• D[15:8]—Data bits 15–8. The upper byte of the data bus is not multiplexed with any other signal. In pure 8-bit systems, this is the data bus. In mixed 8- and 16-bit systems, 8-bit memory blocks or peripherals should be connected to this bus.

• D[7:0]/P A[7:0]—Data bits 7–0 or Port A bits 7–0. This bu s is the lower data by te or general-purpose I/O. In pure 8-bit systems, th is b us can serv e as a general -purpose I /O. The WDTH8 bit in the SCR register (0xFFF000) should be set to 1 by software before the port can be used. See Section 5.2.1, “System Control Register,” on page 5-2 for details on setting this bit. In 16-bit or mixed 8- and 16-bit systems, these pins must function as the lower data byte.

 Signal Descriptions 2-5

Interrupt Controller Signals

2.6 Bus Control Signals

The bus control signals are used for both the configuration and operation of the MC68VZ328 bus. The following descriptions provide detailed information about programming the signals and their use.

WE/LB, UWE/UB—Lower Byte Write-Enable and Uppe r Byte Write-Enable , or Lower Byte and

•L

Upper Byte data strobe s. For all chip-select cycles excep t CSB

WE. They are used as lower and upper write-enable signals to a 16-bit port. If the chip-select is

U set to 8-bit port (the BSW bit is clea r), use only the UWE be used as a DRAM write-enab le if DRAM refresh does not re quire that UWE

should be used. For CSB [1:0] cycles, if the SR16 bit is clear in the CSCTRL1 register, these

DWE two pins are LWE pins are UB of the 16-bit memory chip.

WE/UCLK/PE3—DRAM Write-Enable, UA R T Cl ock, or Port E bit 3. Use the D WE signal with

•D

DRAM, which requires an independent write-enable signal rather than one that is shared with

. This signal stays high during re fresh cycles . This pin defaults to a PE3 inp ut signal. T o se lect

UWE the DWE

bit of the DRAMC register, which is described in Section 7.3.2, “DRAM Control Register,” on page 7-14. If this bit is not enabled, the UCLK signal function is selected, which is an input clock to the UART module. For a description of the UCLK signal, refer to Section 14.2.3, “Serial Interface Signals,” on page 14-3. This pin defaults to GPIO input pulled high.

function, program Port E to DWE and enable the DWE signal by wr itin g a 1 to th e DWE

and UWE and function as previo usl y d escribed. If the SR16 bit is set, these two

and LB. These two data strobe signa ls ar e nor mal ly us ed to connect to UDS and LDS

[1:0], these two pins are LWE and

signal for wri te-enabl e contro l. UWE can

stay high. Otherwise,

• BUSW/DTACK

default bus width for the CSA0 signal. The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the RESET of BUSW on reset means t hat CSA0 on reset means that CSA0 DTACK If it is input, only those chip-select cycles using external DTACK cycles of internal DTACK system reset. For a 16-bit CSA0 pulled up, externally.

•O

microprocessor, which enables the output of either ROM or SRAM.

•U These pins default to GPIO input pulled high.

•RW GPIO input pulled high.

signal. Its mode will determine the defa ult bus width for CSA0. For example, a logic low

input signal. DTACK can be conf igured as output b y programming the Port G DIR regis ter .

E—Output Enable. This active low signal is asserted during a read cycle of the MC68VZ328

DS/PK3, LDS/PK2—Data strobes or GPIO. UDS and LDS are 68000 CPU data strobe signals.

/PK1—Read/Write or Port K bit 1. R W is the 68000 CPU read/wri te signal. Th is pin def aults to

/PG0—Bus Width, Data Transfer Acknowledge, or Port G bit 0. BUSW is the

signal. The DTACK signal is the external input data acknowledge

connects to an 8-bit memory de vice, and a logic hi gh of BUSW

connects to a 16-bit memory device. After reset, this pin defaults to the

will ignore the input status. This pin can be configured to GPIO after

-selected memory device, it is recommended that this signal be

2.7 Interrupt Controller Signals

will be affected. Chip-select

This section describes signals that are used by the MC68VZ328 interrupt controller.

NT[3:0], IRQ[3:1 ], IRQ6/PD[7:0]—Interrupt bits 3–0, Interrupt Request bits 3-1, or Port D bits

•I

NT[3:0], IRQ[3:1], and IRQ6 can be configured as edge or level trigger interrupt signals. To

7–0. I support keyboard applications, the I/O function can be used with interrupt capabilities, which are described in Chapter 9, “Interrupt Controller.” These pins default to GPIO input pulled high.

2-6 MC68VZ328 User’s Manual 

LCD Controller Signals

•IRQ5/PF1—Interrupt Request 5 or Port F bit 1. This signal can be programmed as GPIO or as an interrupt input. When conf igured as an inter rupt input, the signal may be pro grammed as a leve l high or level low trigger interrupt. This pin defaults to GPIO input pulled high.

•EMIQ—Emulator Interrupt Status

EMUIRQ

sources—two br eak point interrupts fr om the in-circuit emul ation module and an external interrupt from EMUIRQ ICEMSR register to identify the interrupt source and write a 1 to the corresponding bit in the ICEMSR. See Section 9.6.4, “Interrupt Status Register,” on page 9-12 for more information.

pin is reque sting a level 7 interrupt. This bit can be generated from three interrupt

, which is an active low, edge-sensitive interrupt. To clear this interrupt, read the

. This bit indicates that the in-circuit emulation module or

2.8 LCD Controller Signals

The MC68VZ328 contains all necessary circuitry to support an external LCD display panel. This section describes the signals used by the LCD controller. It also provides some programming information about the use of these signals.

• LD[3:0]/PC[3:0], LD[7:4]/PK[7:4]—LCD Data Bus bits 7–0, or Port C bits 3–0 and Port K bits 7–4. LD signals output bus transfers of pixel data to the LCD panel to which it will be displayed. The pixel data is arranged to accommodate the programmable panel mode data width selection. Panel interfaces of 1, 2, 4, or 8 bits are supported.

NOTE:

The MC68VZ328’ s LCD inte rface data b us uses th e LSB (LD0) to display pixel 0,0. Some LCD panel manufacturers program their LCD panel data bus so that the MSB of the panel displays pixel 0,0. For these panels, the connection between the MC68VZ328’ s LCD data b us and the LCD p anel’ s data bus ma y hav e a re ver sed bit signi fica nce. F or a 4-bit LCD panel of t his type, connect the MC68VZ328’s LD0 signal to the LCD panel’s data bit 3, and then connect LD1 to LCD data 2, LD2 to LCD data 1, and LD3 to LCD data 0. The four pins can also be programmed as I/O ports from Port C. These signals default as GPIO input with Port C being pulled low and Port K pulled high.

• LFLM/PC4—First Line Marker or Port C bit 4. This signal indicates the start of a new display frame. LFLM becomes act iv e af ter the firs t line pulse of the f rame and r emains active until the next line pulse, at which point it deasserts and remains inactive until the next frame. LFLM can be programmed to be an active high or an activ e low signal. It can also be programmed as an I /O port . This pin defaults to GPIO input pulled low.

• LLP/PC5—LCD Line Pulse or Port C bit 5. The LLP signal is used to latch a line of shifted data onto an LCD panel. The LLP can be programmed to be an active high or active low signal in software. See Section 8.3.10, “LCD Polarity Configuration Register,” on page 8-16 for more information.

• LCLK/PC6—LCD Shift Clock or Port C bit 6. This is t he clock output to which th e out put dat a t o the LCD panel is synchronized. LCLK can be programmed to be either an active high or an active low signal. This pin can a lso b e prog rammed as an I /O port. This pin d efa ults to GPI O input pull ed low .

• LACD/PC7 —LCD Alternate Crystal Direction or Port C bit 7. This output is toggled to alte rnate the crystal polarization on the panel. This signal can be programmed to toggle at a period of 1 to 128 frames or lines. Th is pin also can also be pr ogrammed as an I/O por t. This pin d efaults to GPIO input pulled low.

 Signal Descriptions 2-7

Timer Signals

• LCONTRAST/PF0—LCD Contrast and Port F bit 0. This output is generated by the pulse-width modulator (PWM) inside the LCD controller to adjust the supply voltage to the LCD panel. This pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled high.

2.9 UART 1 and UART 2 Controller Signals

There are two Universal Asynchronous Receive Transmit (UART) modules in the MC68VZ328. This section describes the signals that are used to interface with external serial devices.

• RXD1/PE4, RXD2/PJ4—UART 1 and UAR T 2 Receive Data or Port E bit 4 and Port J bit 4. RXD is the receiver serial input. During normal operation, NRZ data is expected, but in IrDA mode, a narrow pulse of 1.6 µs minimum is expected for each zero bit received. External circuitry must be used to con vert the IrD A sign al to an elec trical signa l. RS-232 applica tions need an externa l RS-232 receiver to convert voltage levels. These pin s default to GPIO input pulle d high.

• TXD1/PE5, TXD2/PJ5—UART 1 and UAR T 2 Transmit Data or Port E bit 5 and Port J bit 5. TXD is the transmitter serial output. During normal operation, they output NRZ data signals. In IrDA mode, they output a selectable pulse width of three-sixteenths bit period or 1.6 µs minimum bit period for each zero bit transmitted. For RS-232 applications, this pin must be connected to an RS-232 transmitter. For IrDA applications, this pin can directly drive an IrDA LED. These pins default to GPIO input pulled high.

TS1/PE6, R TS2/PJ6—UART 1 and U ART 2 Request to Send or Port E bit 6 and Port J bit 6. RTS

•R indicates that i t is ready to receive data by as ser ti ng this pin (low). This pin would be connected to the far-end transmitter’s CTS These pins default to GPIO input pulled high.

TS1/PE7, CTS2/PJ7—UART 1 and UART 2 Clear to Send or Port E bit 7 and Port J bit 7. CTS

•C controls th e transmitte r. Normally, the transmitter waits until this sign al is active (low) before a character is transmitted. If the NOCTSx bit is set in the UTX register, the transmitter sends a character whenever a character is ready to transmit. These pins default to GPIO input pulled high.

pin. When the recei ver detects a pending overrun, it negates th is pi n.

2.10 Timer Signals

There are several external timer and clock signal functions available using the MC68VZ328. This section describes the signals and how they are programmed.

• TOUT/TIN/PB6—Timer 1 Output, Timer 1 Input, or Port B bit 6. TOUT can be programmed to toggle or generate a pulse of 1-system-clock duration when the timer/counter reaches a reference value. TIN is used as the external clock source of Timer 1 or used as a capture function. This pin defaults to GPIO input pulled high.

• UCLK/DWE function is selected when DWE controlled by the UCLKDIR bit of UART 1 and UART 2. For UCLK output, the UCLK bit of peripheral control register selects the clock output signal from UART 1 or UART 2. This pin defaults to GPIO input pulled high.

/PE3—UART Clock input/output, DRAM Write-Enable, or Port E bit 3. The UCLK

is disabled and PESEL3 is written 0. The direction of UCLK is

2-8 MC68VZ328 User’s Manual 

Serial Peripheral Interface 2 Signals

2.11 Pulse-Width Modulator Signals

There are two pulse-width modulator (PWM) modules in the MC68VZ328. This section describes the signals available to communicate with these PWM modules.

• PWMO1/PB7—Pulse-Width Modula tor Output 1 or Port B bit 7. PWMO1 is an output signal from the logical operation (AND or OR) of both the PWM 1 and PWM 2 modules. This pin defaults to GPIO input pulled high.

• PWMO2/DATA_READY PWMO2 is an output signal from the PWM 2 module. If this pin is configured for dedicated I/O function and PKDIR0 is 1, the PWMO2 signal is selected. If PKDIR0 is 0, SPI Data Ready (DATA_READY

) is selected. This pin defaults to GPIO input pulled high.

/PK0—Pulse-W idth Modulator Output 2, SPI Data Ready , or Port K bit 0.

2.12 Serial Peripheral Interface 1 Signals

There are two serial peripheral interface (SPI) modules in the MC68VZ328. This section describes the signals that are used with SPI 1 to interface with external devices.

• MOSI/PJ0—SPI Transmi t Data or Port J bit 0. MOSI is the maste r outpu t/sla ve input signa l for t he SPI shift register. This pin defaults to GPIO input pulled high.

• MISO/PJ1—SPI Receive Data or Por t J bi t 1. MISO is the maste r in put/s lave output sig nal for the SPI shift register. This pin defaults to GPIO input pulled high.

• SPICLK1/PJ2—SPI Clock or Port J bit 2. SPICLK1 is the master clock output/slave clock input signal for SPI. In polarity = 0 mode, this signal is low while the serial peripheral interface master is idle. In polarity = 1 mode, this signal is high during idle. This pin defaults to GPIO input pulled high.

S/PJ3—SPI Slav e Select or Port J bit 3. SS is the master out put/sla ve input chip- select signal. Thi s

•S pin defaults to GPIO input pulled high.

• DATA_READY master mode to signal the SPI master to clock out data. To select the DATA_READY PKDIR0 and PKSEL0 bits are written 0. This pin defaults to GPIO input pulled high.

/PWMO2/PK0—SPI Data Ready or Port K bit 0. DATA_READY can be used in

function, the

2.13 Serial Peripheral Interface 2 Signals

This section describes the signals that are used with SPI 2, the second serial peripheral interface (SPI) module in the MC68VZ328, to interface with external devices.

• SPITXD/PE0—SPI Master Transmit Data or Port E bit 0. SPITXD is the master SPI shift register output signal. This pin defaults to GPIO input pulled high.

• SPIRXD/PE1—SPI Master Receive Data or Port E bit 1. SPIRXD is the input to the master SPI shift register. This pin defaults to GPIO input pulled high.

• SPICLK2/PE2—SPI Master Clock or Port E bit 2. SPICLK2 is the clock output when the serial peripheral interface master is enabled. In polarity = 0 mode, this signal is low while the serial peripheral interface master is idle. In polarity = 1 mode, this signal is high during idle. This pin defaults to GPIO input pulled high.

 Signal Descriptions 2-9

SDRAM Interface Signals

2.14 Chip-Select and EDO RAM Interface Signals

Chip-select logic is used to provide maximum compatibility with a wide variety of memory logic. This section and Section 2.15, “SDRAM Interface Signals,” describe the signals used to interface with RAM,

SDRAM, and EDO RAM.

SA0—Chip-Select A bit 0. CSA0 is a defau lt chip-sel ect signal aft er reset. It i s set to 6 wait st ates

•C

and decodes all a ddress ranges, e xcept internal register add ress space, emulat or space, and bootstrap space (0xFFFC0000–0xFFFFFFFF). It can be reprogrammed during the boot sequence to another

address range or dif ferent wait states. The default data bus width f or CSA0 of the BUSW signal.

SA1/PF7, CSB[1:0]/PB[1:0], CSC[1:0]/PB[3:2]/RAS[1:0], CSD[1:0]/PB[5:4]/CAS[1:0]—

•C Chip-Select A, B, C, and D bits 0 and 1, Port F bit 7, Port B bits 5–0, or row and column select signals. These pins comprise the remainder of the Group A, B, C, and D chip-selects and are individually programmable. Pins that are not needed as chip-selects can be programmed as general-purpose I/O. In addition, CSC and RAS

signals. These pins default to GPIO input pulled high.

[1:0] and CSD [1:0] are designed to support DRAM as CAS

is determined by the s tate

•PM5/DMOE

the OE memory read c ycles. In continuous p age mode, RAS or RAS and if OE contention. Therefore, a dedicated output enable, DMOE continuous page mode is enable d. Using th is mode will minimize t he number of clocks p er DRAM access. This pin defaults to GPIO input pulled high.

—Port M bit 5 or DRAM Continuous P age Mode Out put Ena ble. DMOE is si mila r to

signal. However , DMOE onl y goes act i v e on DRAM read cy cle s, while OE is active for all

is held low until a page-miss, refresh required,

duration time out. During an RAS low period there may be other memory access cycles,

is used to enable the DRAM data output, DRAM will drive data, producing bus

, is required, connecting to DRAM if

2.15 SDRAM Interface Signals

•CSD0, CSD1—These two signals are multiplexed with SDRAM CS0 and CS1. When SDRAM is enabled, CSD0

“Chip-Select Logic,” for more details.

•CSC0

•CSC1

•SDWE

—This signal is multiplexed with SDRAM RAS. When SDRAM is enabled, this signal

becomes an SDRAM RAS

“Chip-Select Logic.”

—This signal is multiplexed with SDRAM CAS. When SDRAM is enabled, this signal

becomes an SDRAM RAS

—SDRAM WE. When SDRAM is enabled, this signal becomes an SDRAM Write-Enable

signal. There is additi ona l pr ogr amming information about this sub je ct i n Chap ter 6, “Chip-Select Logic.”

and CSD1 are SDRAM bank 1 and bank 2 chi p- sel ec t sign als . Als o s ee Ch apt er 6,

signal. For additional information about this subject, see Chapter 6,

signal. For mo re details, see Chapter 6, “Chip-Select Logic.”

• PM0/SDCLK—Port M bit 0 or SDRAM Clock. This pin defaults to GPIO input pulled low.

• PM1/SDCE—Port M bit 1 or SDRAM Clock Enable. This pin defaults to GPIO pulled low.

• PM2/DQMH, PM3/DQML—Port M bits 2–3 or SDRAM input/output mask. The se pi ns def ault to GPIO pulled low.

•PM4/SDA10—Port M bit 4 or SDRAM Address A10. This pin defaults to GPIO input pulled low.

2-10 MC68VZ328 User’s Manual 

In-Circuit Emulation (ICE) Signals

2.16 In-Circuit Emulation (ICE) Signals

The ICE module is designed to sup port lo w-cost emula tor design s using t he MC68VZ328 mi cropr ocesso r. There are four interface signals that are extended to external pins.

IZ/P/D/PG3—High Impedance, Program/Data, or Port G bit 3. During system reset, a logic low

•H of this input signal will put the MC68VZ328 into Hi-Z mode, in which all MC68VZ328 pins are three-stated after reset release. For normal operation, this pin must be pulled high during system reset or left unconnected. This pin defaults to GPIO input pulled high, but can be programmed as the P/D or in data space during emulation mode.

•E input signal will put the MC68VZ328 into emulation mode, which is described in Chapter 16, “In-Circuit Emulation.” For normal operation, this pin must be pulled high during system reset or left unconnected. After system reset, this pin defaults to an EMUIRQ emulation mode. EMUIRQ

•E input signal will put the MC68VZ328 into bootstrap mode, which is described in Chapter 17, “Bootstrap Mode.” For normal operation, this pin must be pulled high during system reset or left unconnected. After system reset , this pin def aults to the EMUBRK used in emulation mode for breakpoint control.

function. P/D is a status signal tha t sho ws whether the curren t b us cycl e is in pr ogram space

MUIRQ/PG2—Emulator Interr upt Request or Port G b it 2. During syste m reset, a logic low of this

function in normal or

is an active low, level 7 interrupt input signal.

MUBRK/PG5—Emulator Breakpoint or Port G bit 5. During system reset, a logic low of this

function, which is an I/O signal

MUCS/PG4—Emulator Chip-Sel ect or Port G bit 4. EMUCS is an 8-bit data b us width chip-sel ect

•E signal that selects the dedicated memory space from 0xFFFC0000 to 0xFFFDFFFF. It cannot be used to select 16-bit data bus memory devices. EMUCS but in normal and bootstrap modes as well. See Chapter 16, “In-Circuit Emulation,” for more information about EMUCS

operation. This pin defaults to an EMUCS signal.

is not only activated in emulation mode,

 Signal Descriptions 2-11

In-Circuit Emulation (ICE) Signals

2-12 MC68VZ328 User’s Manual 

Chapter 3

Memory Map

The memory map is a guide to all on-chip resources. When you configure your chip, refer to Figure 3-1 and either Table 3-1 on page 3-2, which is sorted by address, or Table 3-2 on page 3-8, which is sorted alphabetically by register name.

Monitor Program

(Defined by User)

0x1FFFFFFF

0xFFFC0000 0xFFFDFFFF

0xFFFFF000

0xFFFFFDff 0xFFFFFF00 0xFFFFFfff

Supervisor Memory Map

System Memory

Emulator

MC68VZ328

Monitor

Bootstrap

User’s Memory Map

512 Mbyte

Program / Data

Memory

Reserved

Figure 3-1. MC68VZ328 System Memory Map

 Memory Map 3-1

Programmer’s Memory Map

3.1 Programmer’s Memory Map

On reset the base address used in the ta ble is 0xFFFFF000 (or 0xXXF FF000, where XX is “don’t car e”). If a double-mapped bit is cleared in the system control register, then the base address is 0xFFFFF000 only. Unpredictable result s occur if you write to any 4K regist er space not documented in Ta ble 3-1 or Table 3-2 on page 3-8.

Table 3-1. Programmer’s Memory Map (Sorted by Address)

Address Name Width Description Reset Value

0xFFFFF000 SCR 8 System control register 0x1C 5-2 0xFFFFF003 PCR 8 Peripheral control register 0x00 5-4 0xFFFFF004 IDR 32 Silicon ID register 0x56000000 5-5 0xFFFFF008 IODCR 16 I/O drive control register 0x1FFF 5-6 0xFFFFF100 CSGBA 16 Chip-select group A base register 0x0000 6-4 0xFFFFF102 CSGBB 16 Chip-select group B base register 0x0000 6-4 0xFFFFF104 CSGBC 16 Chip-select group C base register 0x0000 6-4 0xFFFFF106 CSGBD 16 Chip-select group D base register 0x0000 6-4 0xFFFFF108 CSUGBA 16 Chip-select upper group address

register 0xFFFFF10A CSCR 16 Chip-select control register 0x0000 6-16 0xFFFFF110 CSA 16 Group A chip-select register 0x00B0 6-8 0xFFFFF112 CSB 16 Group B chip-select register 0x0000 6-8

0x0000 6-6

Page

Number

0xFFFFF114 CSC 16 Group C chip-select register 0x0000 6-8 0xFFFFF116 CSD 16 Group D chip-select register 0x0200 6-8 0xFFFFF118 EMUCS 16 Emulation chip-select register 0x0060 6-16 0xFFFFF200 PLLCR 16 PLL control register 0x24B3 4-8 0xFFFFF202 PLLFSR 16 PLL frequency select register 0x0347 4-10 0xFFFFF204 RES —Reserved — —

0xFFFFF207 PCTLR 8 Power control register 0x1F 4-14 0xFFFFF300 IVR 8 Interrupt vector register 0x00 9-7 0xFFFFF302 ICR 16 Interrupt control register 0x0000 9-8 0xFFFFF304 IMR 32 Interrupt mask register 0x00FFFFFF 9-10 0xFFFFF308 RES 32 Reserved — —

0xFFFFF30C ISR 32 Interrupt status register 0x00000000 9-12

3-2 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued)

Address Name Width Description Reset Value

0xFFFFF310 IPR 32 Interrupt pending register 0x00000000 9-16 0xFFFFF314 ILCR 16 Interrupt level control regi ste r 0x6533 9 -19 0xFFFFF400 PADIR 8 Port A direction register 0x00 10-6 0xFFFFF401 PADATA 8 Port A data register 0xFF 10-6 0xFFFFF402 PAPUEN 8 Port A pull-up enable register 0xFF 10-6 0xFFFFF403 RES 8 Reserved ——

0xFFFFF408 PBDIR 8 Port B direction register 0x00 10-8 0xFFFFF409 PBDATA 8 Port B data register 0xFF 10-8

0xFFFFF40A PBPUEN 8 Port B pull-up enable register 0xFF 10-8 0xFFFFF40B PBSEL 8 Port B select register 0xFF 10-8

0xFFFFF410 PCDIR 8 Port C direction register 0x00 10-11 0xFFFFF411 PCDATA 8 Port C data register 0x00 10-11 0xFFFFF412 PCPDEN 8 Port C pull-down enable register 0xFF 10-11

Page

Number

0xFFFFF413 PCSEL 8 Port C select register 0xFF 10-11 0xFFFFF418 PDDIR 8 Port D direction register 0x00 10-16 0xFFFFF419 PDDATA 8 Port D data register 0xFF 10-16

0xFFFFF41A PDPUEN 8 Port D pull-up enable register 0xFF 10-16 0xFFFFF41B PDSEL 8 Port D select register 0xF0 10-16 0xFFFFF41C PDPOL 8 Port D polarity register 0x00 10-16 0xFFFFF41D PDIRQEN 8 Port D interrupt request enable

0xFFFFF41E PDKBEN 8 Port D keyboard enable register 0x00 10-16 0xFFFFF41F PDIRQEG 8 Port D interrupt request edge register 0x00 10-16

0xFFFFF420 PEDIR 8 Port E direction register 0x00 10-21 0xFFFFF421 PEDATA 8 Port E data register 0xFF 10-21 0xFFFFF422 PEPUEN 8 Port E pull-up enable register 0xFF 10-21 0xFFFFF423 PESEL 8 Port E select register 0xFF 10-21 0xFFFFF428 PFDIR 8 Port F direction register 0x00 10-24

0x00 10-16

0xFFFFF429 PFDATA 8 Port F data register 0xFF 10-25

 Memory Map 3-3

Programmer’s Memory Map

Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued)

Address Name Width Description Reset Value

0xFFFFF42A PFPUEN 8 Port F pull-up/pull-down enable

0xFFFFF42B PFSEL 8 Port F select register 0x87 10-27

0xFFFFF430 PGDIR 8 Port G direction register 0x00 10-28 0xFFFFF431 PGDATA 8 Port G data register 0x3F 10-28 0xFFFFF432 PGPUEN 8 Port G pull-up enable register 0x3D 10-30 0xFFFFF433 PGSEL 8 Port G select register 0x08 10-31 0xFFFFF438 PJDIR 8 Port J direction register 0x00 10-31 0xFFFFF439 PJDATA 8 Port J data register 0xFF 10-32

0xFFFFF43A PJPUEN 8 Port J pull-up enable register 0xFF 10-33 0xFFFFF43B PJSEL 8 Port J select register 0xEF 10-33

0xFFFFF440 PKDIR 8 Port K direction register 0x00 10-34 0xFFFFF441 PKDATA 8 Port K data register 0x0F 10-35

0xFF 10-27

Page

Number

0xFFFFF442 PKPUEN 8 Port K pull-up/pull-down enable

register 0xFFFFF443 PKSEL 8 Port K select register 0xFF 10-36 0xFFFFF448 PMDIR 8 Port M direction register 0x00 10-37 0xFFFFF449 PMDATA 8 Port M data register 0x20 10-38

0xFFFFF44A PMPUEN 8 Port M pull-up/pull-down enable regis-

ter

0xFFFFF44B PMSEL 8 Port M select register 0x3F 10-40

0xFFFFF500 PWMC1 16 PWM unit 1 control register 0x0020 15-4 0xFFFFF502 PWMS1 16 PWM unit 1 sample register 0xxxxx 15-6 0xFFFFF504 PWMP1 8 PWM unit 1 period register 0xFE 15-7 0xFFFFF505 PWMCNT1 8 PWM unit 1 counter register 0x00 15-7 0xFFFFF506 RES 16 Reserved ——

0xFFFFF510 PWMC2 16 PWM unit 2 control register 0x0000 15-8 0xFFFFF512 PWMP2 16 PWM unit 2 period register 0x0000 15-9

0xFF 10-36

0x3F 10-39

0xFFFFF514 PWMW2 16 PWM unit 2 width register 0x0000 15-10 0xFFFFF516 PWMCNT2 16 PWM unit 2 counter register 0x0000 15-10

3-4 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued)

Address Name Width Description Reset Value

0xFFFFF600 TCTL1 16 Timer unit 1 control register 0x0000 12-6 0xFFFFF602 TPRER1 16 Timer unit 1 prescaler register 0x0000 12-8 0xFFFFF604 TCMP1 16 Timer unit 1 compare register 0xFFFF 12-9 0xFFFFF606 TCR1 16 Timer unit 1 capture register 0x0000 12-10 0xFFFFF608 TCN1 16 Timer unit 1 counter register 0x0000 12-11

0xFFFFF60A TSTAT1 16 Timer unit 1 status register 0x0000 12-12

0xFFFFF610 TCTL2 16 Timer unit 2 control register 0x0000 12-6 0xFFFFF612 TPRER2 16 Timer unit 2 prescaler register 0x0000 12-8 0xFFFFF614 TCMP2 16 Timer unit 2 compare register 0xFFFF 12-9 0xFFFFF616 TCR2 16 Timer unit 2 capture register 0x0000 12-10 0xFFFFF618 TCN2 16 Timer unit 2 counter register 0x0000 12-10

0xFFFFF61A TSTAT2 16 Timer unit 2 status register 0x0000 12-12

0xFFFFF700 SPIRXD 16 SPI unit 1 receive data register 0x0000 13-4

Page

Number

0xFFFFF702 SPITXD 16 SPI unit 1 transmit data register 0x0000 13-5 0xFFFFF704 SPICONT1 16 SPI unit 1 control/status register 0x0000 13-6 0xFFFFF706 SPIINTCS 16 SPI unit 1 interrupt control/status

0xFFFFF70A SPISPC 16 SPI unit 1 sample period control

register 0xFFFFF800 SPIDATA2 16 SPI unit 2 data register 0x0000 13-14 0xFFFFF802 SPICONT2 16 SPI unit 2 control/status register 0x0000 13-15 0xFFFFF900 USTCNT1 16 UART unit 1 status/control register 0x0000 14-10 0xFFFFF902 UBAUD1 16 UART unit 1 baud control register 0x003F 14-12 0xFFFFF904 URX1 16 UART unit 1 receiver register 0x0000 14-13 0xFFFFF906 UTX1 16 UART unit 1 transmitter register 0x0000 14-14 0xFFFFF908 UMISC1 16 UART unit 1 miscellaneous register 0x0000 14-16

0xFFFFF90A NIPR1 16 UART unit 1 non-integer prescaler

0x0000 13-8

0x0000 13-11

0x0000 14-18

0xFFFFF910 USTCNT2 16 UART unit 2 status/control register 0x0000 14-10

 Memory Map 3-5

Programmer’s Memory Map

Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued)

Address Name Width Description Reset Value

0xFFFFF912 UBAUD2 16 UART unit 2 baud control register 0x003F 14-12 0xFFFFF914 URX2 16 UART unit 2 receiver register 0x0000 14-13 0xFFFFF916 UTX2 16 UART unit 2 transmitter register 0x0000 14-14 0xFFFFF918 UMISC2 16 UART unit 2 miscellaneous register 0x0000 14-16

0xFFFFF91A NIPR2 16 UART unit 2 non-integer prescaler

0xFFFFF91C HMARK 16 UART unit 2 FIFO half mark register 0x0102 14-29 0xFFFFFA00 LSSA 32 LCD screen starting address register 0x00000000 8-10 0xFFFFFA05 LVPW 8 LCD virtual page width register 0xFF 8-11 0xFFFFFA08 LXMAX 16 LCD screen width register 0x03F0 8-12 0xFFFFFA0A LYMAX 16 LCD screen height register 0x01FF 8-12 0xFFFFFA18 LCXP 16 LCD cursor X position register 0x0000 8-12 0xFFFFFA1A LCYP 16 LCD cursor Y position register 0x0000 8-13

0x0000 14-18

Page

Number

0xFFFFFA1C LCWCH 16 LCD cursor width and height register 0x0101 8-14 0xFFFFFA1F LBLKC 8 LCD blink control register 0 x7F 8-14 0xFFFFFA20 LPICF 8 LCD panel interface configuration

0xFFFFFA21 LPOLCF 8 LCD polarity configuration register 0x00 8-16 0xFFFFFA23 LACDRC 8 LACD rate control register 0x00 8-16 0xFFFFFA25 LPXCD 8 LCD pixel clock divider register 0x00 8-17 0xFFFFFA27 LCKCON 8 LCD clocking control register 0x00 8-18 0xFFFFFA29 LRRA 8 LCD refresh rate adjustment register 0xFF 8-18 0xFFFFFA2B RES 8 Reserved ——

0xFFFFFA2D LPOSR 8 LCD panning offset register 0x00 8-19 0xFFFFFA31 LFRCM 8 LCD frame rate control modulation

0xFFFFFA33 LGPMR 8 LCD gray palette mapping register 0x84 8-20 0xFFFFFA36 PWMR 16 PWM contrast control register 0x0000 8-20

0x00 8-15

0x00 8-19

0xFFFFFA38 RMCR 8 Refresh mode control register 0x00 8-21 0xFFFFFA39 DMACR 8 DMA control register 0x62 8-22

3-6 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-1. Programmer’s Memory Map (Sorted by Address) (Continued)

Address Name Width Description Reset Value

0xFFFFFB00 RTCTIME 32 RTC time of day register 0xXXXX00XX 11-3 0xFFFFFB04 RTCALRM 32 RTC alarm register 0x00000000 11-3 0xFFFFFB0A W ATCHDOG 16 Watchdog tim er registe r 0x00 01 11-4 0xFFFFFB0C RTCCTL 8 RTC control register 0x0080 11-10 0xFFFFFB0E RTCISR 16 RTC interrupt status register 0x 00 00 11-10 0xFFFFFB10 RTCIENR 16 RTC interrupt enable register 0x0000 11-12 0xFFFFFB12 STPWCH 8 Stopwatch minutes register 0x003F 11-14 0xFFFFFB1A DAYR 16 RTC day count registe r 0x0xxx 11-6 0xFFFFFB1C DAYALARM 16 RTC day alarm register 0x0000 11-8 0xFFFFFC00 DRAMMC 16 DRAM memory configuration register 0x0000 7-12 0xFFFFFC02 DRAMC 16 DRAM control register 0x0000 7-14 0xFFFFFC04 SDCTRL 16 SDRAM control register 0x003C 7-16 0xFFFFFC06 SDPWDN 16 SDRAM power down register 0x0000 7-18

Page

Number

0xFFFFFC80 RES —Reserved — — 0xFFFFFD00 ICEMACR 32 ICEM address compare register 0x00000000 16-4 0xFFFFFD04 ICEMAMR 32 ICEM address mask register 0x00000000 16-4 0xFFFFFD08 ICEMCCR 16 ICEM control compare register 0x0000 16-6

0xFFFFFD0A ICEMCMR 16 ICEM control mask register 0x0000 16-6 0xFFFFFD0C ICEMCR 16 ICEM control register 0x0000 16-8 0xFFFFFD0E ICEMSR 16 ICEM status r eg ister 0x0000 16-10

0xFFFFFExx Bootloader — Bootloader microcode spa ce — —

 Memory Map 3-7

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name)

Name Address Width Description Reset Value

Bootloader 0xFFFFFExx — Bootloader micro cod e s pa ce — —

CSA 0xFFFFF110 16 Group A chip-select register 0x00B0 6-8 CSB 0xFFFFF112 16 Group B chip-select register 0x0000 6-8

CSC 0xFFFFF114 16 Group C chip-select register 0x0000 6-8

CSCR 0xFFFFF10A 16 Chip-select control register 0x0000 6-16

CSD 0xFFFFF116 16 Group D chip-select register 0x0200 6-8 CSGBA 0xFFFFF100 16 Chip-select group A base register 0x0000 6-4 CSGBB 0xFFFFF102 16 Chip-select group B base register 0x0000 6-4 CSGBC 0xFFFFF104 16 Chip-select group C base register 0x0000 6-4 CSGBD 0xFFFFF106 16 Chip-select group D base register 0x0000 6-4

CSUGBA 0xFFFFF108 16 Chip-select upper group address

DAYALARM 0xFFFFFB1C 16 RTC day alarm register 0x0000 11-8

0x0000 6-6

Page

Number

DAYR 0xFFFFFB1A 16 RTC day count regis te r 0x0xxx 11-6 DMACR 0xFFFFFA39 8 DMA control register 0x62 8-22 DRAMC 0xFFFFFC02 16 DRAM control register 0x0000 7-14

DRAMMC 0xFFFFFC00 16 DRAM memory configuration register 0x0000 7-12

EMUCS 0xFFFFF118 16 Emulation chip-select register 0x0060 6-16 HMARK 0xFFFFF91C 16 UART unit 2 FIFO half mark register 0x0102 14-29

ICEMACR 0xFFFFFD00 32 ICEM address compare register 0x00000000 16-4

ICEMAMR 0xFFFFFD04 32 ICEM address mask register 0x00000000 16-4

ICEMCCR 0xFFFFFD08 16 ICEM control compare register 0x0000 16-6

ICEMCMR 0xFFFFFD0A 16 ICEM control mask register 0x0000 16-6

ICEMCR 0xFFFFFD0C 16 ICEM control register 0x0000 16-8 ICEMSR 0xFFFF FD0E 16 ICEM status reg ister 0x0000 16-10

ICR 0xFFFFF302 16 Interrupt control register 0x0000 9-8 IDR 0xFFFFF004 32 Silicon ID register 0x56000000 5-5

ILCR 0xFFFFF3 14 16 Interrupt level control register 0x6533 9-19

IMR 0xFFFFF304 32 Interrupt mask register 0x00FFFFFF 9-10

3-8 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued)

Name Address Width Description Reset Value

IODCR 0xFFFFF008 16 I/O drive control register 0x1FFF 5-6

IPR 0xFFFFF310 32 Interrupt pending register 0x00000000 9-16 ISR 0xFFFFF30C 32 Interrupt status register 0x00000000 9-12 IVR 0xFFFFF300 8 Interrupt vector register 0x00 9-7

LACDRC 0xFFFFFA23 8 LACD rate control register 0x00 8-16

LBLKC 0xFFFFFA1F 8 LCD blink control register 0x7F 8-14

LCKCON 0xFFFFFA27 8 LCD clocking control register 0x00 8-18

LCWCH 0xFFFFFA1C 16 LCD cursor width and height register 0x0101 8-14

LCXP 0xFFFFFA18 16 LCD cursor X position register 0x0000 8-12

LCYP 0xFFFFFA1A 16 LCD cursor Y position register 0x0000 8-13

LFRCM 0xFFFFFA31 8 LCD frame rate control modulation

LGPMR 0xFFFFFA33 8 LCD gray palette mapping register 0x84 8-20

0x00 8-19

Page

Number

LPICF 0xFFFFFA20 8 LCD panel interface configuration

LPOLCF 0xFFFFFA21 8 LCD polarity configuration register 0x00 8-16

LPOSR 0xFFFFFA2D 8 LCD panning offset register 0x00 8-19

LPXCD 0xFFFFFA25 8 LCD pixel clock divider register 0x00 8-17

LRRA 0xFFFFFA29 8 LCD refresh rate adjustment register 0xFF 8-18

LSSA 0xFFFFFA00 32 LCD screen starting address register 0x00000000 8-10

LVPW 0xFFFFFA05 8 LCD virtual page width register 0xFF 8-11

LXMAX 0xFFFFFA08 16 LCD screen width register 0x03F0 8-12 LYMAX 0xFFFFFA0A 16 LCD screen height register 0x01FF 8-12

NIPR1 0xFFFFF90A 16 UART unit 1 non-integer prescaler

NIPR2 0xFFFFF91A 16 UART unit 2 non-integer prescaler

PADATA 0xFFFFF401 8 Port A data register 0xFF 10-6

PADIR 0xFFFFF400 8 Port A direction register 0x00 10-6

0x00 8-15

0x0000 14-18

PAPUEN 0xFFFFF402 8 Port A pull-up enable register 0xFF 10-6

PBDATA 0xFFFFF409 8 Port B data register 0xFF 10-8

 Memory Map 3-9

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued)

Name Address Width Description Reset Value

PBDIR 0xFFFFF408 8 Port B direction register 0x00 10-8

PBPUEN 0xFFFFF40A 8 Port B pull-up enable register 0xFF 10-8

PBSEL 0xFFFFF40B 8 Port B select register 0xFF 10-8

PCDATA 0xFFFFF411 8 Port C data register 0x00 10-11

PCDIR 0xFFFFF410 8 Port C direction register 0x00 10-11

PCPDEN 0xFFFFF412 8 Port C pull-down enable register 0xFF 10-11

PCR 0xFFFFF003 8 Peripheral control register 0x00 5-4 PCSEL 0xFFFFF413 8 Port C select register 0xFF 10-11 PCTLR 0xFFFFF207 8 Power control register 0x1F 4-14

PDDATA 0xFFFFF419 8 Port D data register 0xFF 10-16

PDDIR 0xFFFFF418 8 Port D direction register 0x00 10-16 PDIRQEG 0xFFFFF41F 8 Port D interrupt request edge register 0x00 10-16 PDIRQEN 0xFFFFF41D 8 Port D interrupt request enable

0x00 10-16

Page

Number

PDKBEN 0xFFFFF41E 8 Port D keyboard enable register 0x00 10-16

PDPOL 0xFFFFF41C 8 Port D polarity register 0x00 10-16

PDPUEN 0xFFFFF41A 8 Port D pull-up enable register 0xFF 10-16

PDSEL 0xFFFFF41B 8 Port D select register 0xF0 10-16

PEDATA 0xFFFFF421 8 Port E data register 0xFF 10-21

PEDIR 0xFFFFF420 8 Port E direction register 0x00 10-21

PEPUEN 0xFFFFF422 8 Port E pull-up enable register 0xFF 10-21

PESEL 0xFFFFF423 8 Port E select register 0xFF 10-21

PFDATA 0xFFFFF429 8 Port F data register 0xFF 10-25

PFDIR 0xFFFFF428 8 Port F direction register 0x00 10-24

PFPUEN 0xFFFFF42A 8 Port F pull-up/pull-down enable

PFSEL 0xFFFFF42B 8 Port F select register 0x87 10-27

PGDATA 0xFFFFF431 8 Port G data register 0x3F 10-28

PGDIR 0xFFFFF430 8 Port G direction register 0x00 10-28

0xFF 10-27

PGPUEN 0xFFFFF432 8 Port G pull-up enable register 0x3D 10-30

3-10 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued)

Name Address Width Description Reset Value

PGSEL 0xFFFFF433 8 Port G select register 0x08 10-31

PJDATA 0xFFFFF439 8 Port J data register 0xFF 10-32

PJDIR 0xFFFFF438 8 Port J direction register 0x00 10-31

PJPUEN 0xFFFFF43A 8 Port J pull-up enable register 0xFF 10-33

PJSEL 0xFFFFF43B 8 Port J select register 0xEF 10-33

PKDATA 0xFFFFF441 8 Port K data register 0x0F 10-35

PKDIR 0xFFFFF440 8 Port K direction register 0x00 10-34

PKPUEN 0xFFFFF442 8 Port K pull-up/pull-down enable

PLLFSR 0xFFFFF202 16 PLL frequency select register 0x0347 4-10

PMDATA 0xFFFFF4 49 8 Port M data register 0x20 10-38

0xFF 10-36

Page

Number

PMDIR 0xFFFFF448 8 Port M direction register 0x00 10-37

PMPUEN 0xFFFFF44A 8 Port M pull-up/pull-down enable

PMSEL 0xFFFFF44B 8 Port M select register 0x3F 10-40 PWMC1 0xFFFFF500 16 PWM unit 1 control register 0x0020 15-4 PWMC2 0xFFFFF510 16 PWM unit 2 control register 0x0000 15-8

PWMCNT1 0xFFFFF505 8 PWM unit 1 counter register 0x00 15-7 PWMCNT2 0xFFFFF516 16 PWM unit 2 counter regist er 0x0000 15-10

PWMP1 0xFFFFF504 8 PWM unit 1 period register 0xFE 15-7 PWMP2 0xFFFFF512 16 PWM unit 2 period register 0x0000 15-9

PWMR 0xFFFFFA36 16 PWM contrast control register 0x0000 8-20

PWMS1 0xFFFFF502 16 PWM unit 1 sample register 0xxxxx 15-6

PWMW2 0xFFFFF514 16 PWM unit 2 width register 0x0000 15-10

RES 0xFFFFF204 —Reserved — —

RES 0xFFFFF308 32 Reserved — —

0x3F 10-39

RES 0xFFFFF403 8 Reserved — — RES 0xFFFFF506 16 Reserved — —

 Memory Map 3-11

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued)

Name Address Width Description Reset Value

RES 0xFFFFFA2B 8 Reserved —— RES 0xFFFFFC80 — Reserved — —

RMCR 0xFFFFFA38 8 Refresh mode control register 0x00 8-21

RTCALRM 0xFFFFFB04 32 RTC alarm register 0x00000000 11-3

RTCCTL 0xFFFFFB0C 8 RTC control register 0x0080 11-10

RTCIENR 0xFFFFFB10 16 RTC interrupt enable regi st er 0x0000 11-12

RTCISR 0xFFFFFB0E 16 RTC interrupt status register 0x0000 11-10

RTCTIME 0xFFFFFB00 32 RTC time of day register 0xXXXX00XX 11-3

SCR 0xFFFFF000 8 System control register 0x1C 5-2

SDCTRL 0xFFFFFC04 1 6 SDRAM control register 0x003C 7-16

SDPWDN 0xFFFFFC06 16 SDRAM power down register 0x0000 7-18 SPICONT1 0xFFFFF704 16 SPI unit 1 control/status register 0x0000 13-6 SPICONT2 0xFFFFF802 16 SPI unit 2 control/status register 0x0000 13-15

Page

Number

SPIDATA2 0xFFFFF800 16 SPI unit 2 data register 0x0000 13-14

SPIINTCS 0xFFFFF706 16 SPI unit 1 interrupt control/status

register SPIRXD 0xFFFFF700 16 SPI unit 1 receive data register 0x0000 13-4 SPISPC 0xFFFFF70A 16 SPI unit 1 sample period control

SPITEST 0xFFFFF708 16 SPI unit 1 test register 0x0000 13-10

SPITXD 0xFFFFF702 16 SPI unit 1 transmit data register 0x0000 13-5

STPWCH 0xFFFFFB12 8 Stopwatch minutes register 0x003F 11-14

TCMP1 0xFFFFF604 16 Timer unit 1 compare register 0xFFFF 12-9 TCMP2 0xFFFFF614 16 Timer unit 2 compare register 0xFFFF 12-9

TCN1 0xFFFFF608 16 Timer unit 1 counter register 0x0000 12-11 TCN2 0xFFFFF618 16 Timer unit 2 counter register 0x0000 12-10 TCR1 0xFFFFF606 16 Timer unit 1 capture register 0x0000 12-10 TCR2 0xFFFFF616 16 Timer unit 2 capture register 0x0000 12-10

0x0000 13-8

0x0000 13-11

TCTL1 0xFFFFF600 16 Timer unit 1 control register 0x0000 12-6 TCTL2 0xFFFFF610 16 Timer unit 2 control register 0x0000 12-6

3-12 MC68VZ328 User’s Manual 

Programmer’s Memory Map

Table 3-2. Programmer’s Memory Map (Sorted by Register Name) (Continued)

Name Address Width Description Reset Value

TPRER1 0xFFFFF602 16 Timer unit 1 prescaler register 0x0000 12-8 TPRER2 0xFFFFF612 16 Timer unit 2 prescaler register 0x0000 12-8

TSTAT1 0xFFFFF60A 16 Timer unit 1 status register 0x0000 12-12 TSTAT2 0xFFFFF61A 16 Timer unit 2 status register 0x0000 12-12

UBAUD1 0xFFFFF902 16 UART unit 1 baud control register 0x003F 14-12 UBAUD2 0xFFFFF912 16 UART unit 2 baud control register 0x003F 14-12

UMISC1 0xFFFFF908 16 UART unit 1 miscellaneous register 0x0000 14-16 UMISC2 0xFFFFF918 16 UART unit 2 miscellaneous register 0x0000 14-16

URX1 0xFFFFF904 16 UART unit 1 receiver register 0x0000 14-13

URX2 0xFFFFF914 16 UART unit 2 receiver register 0x0000 14-13 USTCNT1 0xFFFFF900 16 UART unit 1 status/control register 0x0000 14-10 USTCNT2 0xFFFFF910 16 UART unit 2 status/control register 0x0000 14-10

UTX1 0xFFFFF906 16 UART unit 1 transmitter register 0x0000 14-14

Page

Number

UTX2 0xFFFFF916 16 UART unit 2 transmitter register 0x0000 14-14

WATCHDOG 0xFFFFFB0A 16 Watchdog timer register 0x0001 11-4

 Memory Map 3-13

Programmer’s Memory Map

3-14 MC68VZ328 User’s Manual 

Chapter 4

Clock Generation Module and Power Control Module

This chapter describes the clock generation module (CGM) and power control module (PCM). The description of both modules comprises a single chapter because their operation is so closely integrated. The programmability of the individual clock signals makes the CGM a flexible clock source for the MC68VZ328 and its associated peripherals.

The CGM uses a low-frequency oscillator in conjunction with a multiplier/divider chain to produce the clock signals used throughout the MC68VZ328 integrated processor. The frequency of all clock signals (except the low-frequency reference) are individually selectable through software control. The MC68VZ328 has four different power modes to provide optimum power efficiency.

The PCM controls the power consumption of the CPU by applying clock signals to the CPU at reduced burst widths. For maximum power savings, the MC68VZ328 can be placed in sleep mode in which all clocks (except for the low-frequency clock) are disabled.

NOTE:

The CGM module is designated as the PLL module in earlier versions of the DragonBa ll family. The nomenclatu re change d from PLL to CGM to be consistent with Motorola naming and standards conventions. The term PLL is used only to describe the actual PLL circuit within the CGM.

 Clock Generation Module and Power Control Module 4-1

Introduction to the Clock Generation Module

4.1 Introduction to the Clock Generation Module

The CGM produces four clock signals:

• CLK32—A low-frequency reference clock used by almost every module

• DMACLK—Used to create the remaining two clocks, and serves as DMA clock for the LCD controller

• SYSCLK—Used by most modules, including the CPU

• LCDCLK—Used as reference by the LCD

The distribution of the clock signals generated by the CGM is shown in Table 4-1. With the exception of the CLK32 signal, the frequency of the clock signals can be individually programmed.

Table 4-1. CGM Clock Signal Distribution

Used by or Available To CLK32 SYSCLK DMACLK LCDCLK

CLKO/PF2 pin X DRAM controller X X X LCD controller X X PCM X PWM X X RTC X SPIs X Timers X X UARTs X

4-2 MC68VZ328 User’s Manual 

CGM Operational Overview

4.2 CGM Operational Overview

The CGM consists of six major parts, as shown in the simplified block diagram in Figure 4-1. The clock source for the CGM is a crystal oscillator that is comprised of an external crys tal connected to the internal XTAL oscillator circuit. The output of the XTAL oscillator is the CLK32 signal, whose frequency is determined by the frequency of the external crystal. The CLK32 clock signal serves as a source for the PLL and many other modules within the MC68VZ328.

The output frequency of the PLL (PLLCLK) is determined by the frequency of CLK32 and by the values of the PC and QC fields of the PLL frequency select register (PLLFSR). The output of the PLL is applied to a divider chain comp osed of two pr escal ers. The PLLCLK cl ock is fi rst in put i nto pres caler 1. Its output frequency is selected by the prescaler select 1 (PRESC1) bit in the PLLCR. The output of the prescaler 1 (PR1CLK) is applied to prescaler 2, whose output frequency (DMACLK) is controlled by the prescaler select 2 (PRESC2) bit in the PLLCR. The DMACLK signal is applied to the LCD controller in the MC68VZ328 and also serves as the clock source for the LCD clock divider and the SYSCLK divider.

The output of the LCD clock divider is LCDCLK, whose frequency is controlled by the LCD clock selection (LCDCLK) field in the PLLCR. The LCDCLK signal is only used by the LCD controller. The SYSCLK divider produces a SYSCLK clock signal that is used throughout the MC68VZ328. SYSCLK is also used as the CPU clock signal (CPUCLK) by the internal FLX68000 CPU. SYSCLK is the only CGM-generated clock signal that can be made available to external devices via the buffered output of the clock out/Port F bit 2 pin (CLKO/PF2). See Section 10.4.7.3, “Port F Dedicated I/O Functions,” on

page 10-26 for more information. The output is available when the clock enable bit of the PLLCR is enabled and bit 2 in the Port F select register (PFSEL) is cleared.

EXTAL

XTAL

PC QC

PLLFSR

XTAL

Oscillator

Figure 4-1. Clock Generation Module (CGM) Simplified Block Diagram

DSPL

PLL

CLK32

PRESC1

PLLCLK

Prescaler 1

PR1CLK

Prescaler 2

PLLCR

LCDCLK SEL SYSCLK SELPRESC2 CLKEN

LCD Clock

Divider

SYSCLK

Divider

Enable

Buffer

CLKO/

PF2

LCDCLK

DMACLK

SYSCLK

CLK32

 Clock Generation Module and Power Control Module 4-3

Detailed CGM Clock Descriptions

4.3 Detailed CGM Clock Descriptions

Section 4.3.1, “CLK32 Clock Signal,” and Section 4.3.2, “PLLCLK Clock Signal,” describe in detail the operation of each clock signal produced by the CGM.

4.3.1 CLK32 Clock Signal

The low-frequency output of th e XTAL oscil lato r (CLK32) i s avai lable withi n a few hun dred mil lise conds after initial power is applied to the circuit. The frequency of the CLK32 signal is determined by the frequency of the external crystal. The CGM supports either a 32.768 kHz or a 38.4 kHz crystal.

NOTE:

Regardless of the crystal frequency used, the output is always labeled CLK32.

Figure 4-2 represents a suggestion of how a crystal may be connected to the MC68VZ328. The values of C1 and C2 in Figure 4-2 are determined by using the crystal load capaci tance (CL) , PCB stray capacit ance, Cstray (measured or a ppr oxi mate d), and DragonBall input capa ci tan ce ( C dbvz << 1.0 pf) according to the following fo rmula:

CL = Cstray + Cdbvz + (C1 * C2) / (C1 + C2)

Eqn. 4-1

Typical design values are C1 = C2 = 20 pf. The user should consult the crystal manufacturer for appropriate circuit layout and circuit values.

The CLK32 clock signal is uni que in t hat whil e the o ther clock sources are dis abled whe n the MC68VZ328 is placed in sleep mode, the CLK32 clock is available as long as power is applied. See Section 4.5.1.4, “Sleep Mode,” for detailed information on sleep mode.

MC68VZ328

EXTAL

Crystal

32.768 kHz or

38.4 kHz XTAL

C1*

Figure 4-2. Example of External Crystal Connection

C2*

*See Equation 4-1 for design values.

4.3.2 PLLCLK Clock Signal

The PLL output frequency, PLL clock (PLLCLK), is determined by a combination of the CLK32 signal’s input frequency and the values in the PC and QC fields of the PLLFSR. Section 4.3.2.2, “PLL Frequency Selection,” describes the procedure for frequency selection.

4-4 MC68VZ328 User’s Manual 

Detailed CGM Clock Descriptions

4.3.2.1 PLLCLK Initial Power-up Sequence

Refer to Figure 4-3 for a graphical representation of the following power-up sequence description. When power is init ially applied to the MC68VZ328, the XTAL oscillator begins to oscillate. Due to the low-power design on the oscillator pads, the RESET ensure that the cryst al oscil lato r st arts and stabil izes. Thi s is a signifi cant cha nge from the 250 ms required with the previous DragonBall and DragonBall EZ processors. The length of the delay (1.2 s) is an approximate value and should only be used as a starting point. The RESET device with a threshold of 1.4 V high and 1.0 V low.

On power up, the RESET signal should be deasserted after the crystal has energized and its output has stabil ized, as sh own in Figure 4-3. While most crystal oscillators typically operate with a value of 1.2 seconds, the optimum value will be determined experimentally. Due to the inherent nature of crystals, refer to manufacturers documentation for optimum circuit design information.

signal must be asserted (low) for at least 1.2 s to

pin (input) is a Schmitt trigger

NOTE:

After RESET

is deasserted, the PLLCLK signal is available to the divider chain, resulting in the

availability of DMACLK from prescaler 2.

XTAL OSC

RESET

DMACLK

Figure 4-3. Initial Power-up Sequence Timing

1.2 s

 Clock Generation Module and Power Control Module 4-5

Detailed CGM Clock Descriptions

4.3.2.2 PLL Frequency Selection

Using the default settings for the PC and QC fields of the PLLFSR and a CLK32 input frequency of

32.768 kHz produces a PLLCLK output of 66.322 MHz. For a 38.400 kHz crystal, the same default settings produce a 77.722 M Hz PLLCLK. The PLLCLK clock is phase locked to the CLK32 clock input signal.

WARNING:

The value of prescaler 1 must always be set to divide-by-two to prevent DMACLK and SYSCLK from operating beyond their design limits.

The PLL uses a dual-modulus counter to multiply the CLK32 frequency before it is input to the prescaler and the rest of t he divider chain. Du al -modul us counters opera te di ff erently from other c ounters in that the overall multiplication ratio depends on two separate values, PC and QC.

In the follow ing equation, the value of Q is defined as 1 <

Q+1.

Multiplier 2 14 P 1+

For example, if Q = 3 and P = 71, then the following equations obtain:

Multiplier = 2 * (14 (71 + 1) + 3 + 1) = 2 * (1008 + 4) = 2024 2024 * 32.768 kHz = 66.322432 MHz

The default multiplier value is 2024. Using any multiplier equal to or greater than 794 (decimal) allows changing the PLLCLK in 32.768 kHz or 38.4 kHz steps. The minimum PC and QC values are P = 0x1B and Q = 0x04 (which produce a multiplier of 794 decimal

()

Q<14, and the value of P is defined as

Q1++

Eqn. 4-2

4.3.2.3 PLLCLK Frequency Selection Programming Example

Example 4-1 on page 4-7 demonstrates the recommended sequence of events to change the PLLCLK frequency. The assumptions are:

• All peripherals have been disabled using chip-select. See Chapter 6, “Chip-Select Logic,” for details.

• SYSCLK is operating at the highest possible frequency (SYSCLK SEL = 100).

In Example 4-1, the variable NEWFREQ is the new frequency value (P and Q values) to be programmed. The MC68VZ328 is placed in sleep mode before the stop command. See Section 4.5.1.4, “Sleep Mode,” for detailed information about sleep modes. This routine enables the timer to wake up the PLL after 96 CLK32 periods. When the P LL wake s up, it will be at the new frequency. The inte rr upt se rvi ce routine for the temporary timer interrupt should clear the timer interrupt and then return. In addition, the PLLCLK should only be changed during an early phase of the boot-up sequence.

NOTE:

Example 4-1 is designed for clarity, and is not necessarily efficient.

4-6 MC68VZ328 User’s Manual 

Detailed CGM Clock Descriptions

Example 4-1. Configuring the PLLCLK Frequency

NEWFREQ equ somevalue ;P and Q value of new f requency PLLCONTROL equ $FFFFF200 ;PLL Control Register PLLFREQ equ $FFFFF202 ;P LL Frequency Control Register TCOMPARE equ $FFFFF604 ;Timer Compare Value Register TCONTROL equ $FFFFF600 ;Timer Control Register IMR equ $FFFFF304 ;Interrupt Mask Register

move.l IMR,-(SP) ;save the Interrupt Mask register move.l #$fffffffd,IMR ;enable ONLY Timer interrupt move.w #$0001,TCOMPARE ;set compare value to 2 move.w #$0119,TCONTROL ;enable Timer 2 with CLK32 s ource

SYNC1 btst.b #$7,PLLFREQ ;synchronize to CLK32 high level SYNC2 btst.b #$7,PLLFREQ ;synchronize to CLK32 low level

; the PLL shuts down here an d waits for the Timer interrupt ; interrupt service for Time r occurs here

; The PLL has reacquired loc k and SYSCLK is stabl e

beq.s SYNC 1 ;CLK32 is still not high, go back bne.s SYNC2 ;CLK32 is still not low, go back

move.w #NEWFREQ,PLLFREQ ;load the new frequency ori.b #$8,PLLCONTROL+1 ;disable the PLL (in 30 cloc ks)-sleep mode stop #$2000 ;stop, enable all interrupts

move.w (SP)+,IMR ;restore the Interrupt Mask Register rts ;PLL is now at the new frequency

4.3.2.4 Programming Considerations When Changing Frequencies

The following information is provided to assist the user in programming the MC68VZ328.

• When programming the SYSCLK frequenc y, ensure that it does not e xceed 33.161 216 MHz at any time.

• Since the PRESC1 and PRESC2 bits are set to %1 by default, the DMACLK output is approximately 16 MHz.

• Because most of the modules—such as the U AR T , SPI, gene ral-purpose timers, and PWM—use t he SYSCLK for bit-rate generation, changi ng the PLLCLK fr equenc y will also cha nge SYSCLK and overall system timing (except for CLK32). Therefore, once a PLLCLK frequency is selected, it should not be changed during system operation.

• To reduce power consumption, the output of the PLL can be disabled using the DISPLL bit in the PLL control register, which places the chip in sleep mode. See Section 4.5.1.4, “Sleep Mode,” for more details. When the MC68VZ328 is awakened from sleep mode by a wake-up event, the PLL output (PLLCLK) is available after a delay determined by the setting in the WKSEL field of PLLCR. Unlike the initial power-up sequence, the crystal oscillator is already on, so the crystal startup time is not a factor.

 Clock Generation Module and Power Control Module 4-7

CGM Programming Model

4.4 CGM Programming Model

This section describes the two registers that enable and control the frequency of the CGM clocks.

4.4.1 PLL Control Register

The PLL control register (PLLCR) controls the frequency selection of the LCDCLK, SYSCLK, and DMACLK. It also enables the output of the PLL and clock out/Port F pin 2 (CLKO/PF2). The settings for each bit and field in the register are described in Table 4-2.

PLLCR PLL Control Register 0xFFFFF200

BIT

14 13 12 11 10 9 8 7 6 5 4 3 2 1

LCDCLK SEL SYSCLK SEL PRESC1 PRESC2 CLKEN DISPLL WKSEL

TYPE

RESET

0 0100100 1 0 1 1 0 011

rw rw rw rw rw rw rw rw rw rw rw rw

0x24B3

Table 4-2. PLL Control Register Description

Name Description Setting

Reserved Bits 15–14

LCDCLK SEL

Bits 13–11

SYSCLK SEL

Bits 10–8

Reserved These bits are reserved and should be set to

LCD Clock Select—This field controls the divide ratio used by the LCD clock divider to convert DMACLK to LCDCLK. This field can be changed at any time.

System Clock Select—This field controls the divide ratio used by the SYSCLK divider to convert DMACLK to SYSCLK. This field can be changed at any time.

000 = DMACLK ÷ 2. 001 = DMACLK ÷ 4. 010 = DMACLK ÷ 8. 011 = DMACLK ÷ 16. 1xx = DMACLK ÷ 1 (%100 after reset).

BIT

PRESC1

Bit 7 Reserved

Bit 6

PRESC2

Bit 5

CLKEN

Bit 4

Prescaler 1 Select—T his bit sel ects the di vide ratio of the prescaler 1.

Reserved This bit is reserved and should be set to 0.

Prescaler 2 Select—T his bit sel ects the di vide ratio used by the prescaler 2 to divide the output of prescaler 1, producing DMACLK. This field can be changed at any time.

Clock Enable—This bit enable s the buf fered output of the SYSCLK at the CLKO/PF2 pin when bit 2 of the PFSEL register is als o cleared.

0 = PLLCLK ÷ 1. 1 = PLLCLK ÷ 2 (default).

0 = PR1CLK ÷ 1. 1 = PR1CLK ÷ 2 (default).

0 = CLKO enabled. 1 = CLKO disabled (defaul t).

4-8 MC68VZ328 User’s Manual 

CGM Programming Model

Table 4-2. PLL Control Register Description (Continued)

Name Description Setting

DISPLL

Bit 3

Reserved Bit 2

WKSEL

Bits 1–0

Disable PLL—This bit, when set , disables the output of the PLL, placing the chip in sleep mode, its low est power state.

Reserved This bit is reserved and should be set to 0.

Wake-up Clock Select — Thi s field se lects the delay of the PLL output from the initiation of the wake up until an output is available. Since the delay time is calc ulated by coun ting CLK32 cycles, the frequency of the crystal oscillator will determine the amount of delay that each setting produces.

0 = PLL enabled (default). 1 = PLL disabled.

See Table 4-3 for delay settings.

Table 4-3. WKSEL Field (PLLCR) Delay Settings

Bits 1–0 CLK32 Periods

00 32 0.976 0.833 01 48 1.465 1.250 10 64 1.953 1.667 11 96 2.93 (default) 2.500 (default)

Delay in Milliseconds

(32.768 kHz)

Delay in Milliseconds

(38.4 kHz)

 Clock Generation Module and Power Control Module 4-9

Introduction to the Power Control Module

4.4.2 PLL Frequency Select Register

The PLL frequency select regis ter (PLLFSR) cont rols the two di viders of th e dual-modulus counter. It also contains the write-protect bit for the QC and PC counters and the CLK32 status bit. Although PLLFSR register can be acc essed in byt es, it should al ways be writt en as a 16- bit wor d. T he set tings for each bit an d field in the register is described in Table 4-4.

PLLFSR PLL Frequency Select Register 0x(FF)FFF202

BIT 15 14 13 12 11 10 987654321BIT 0

CLK32 PROT

TYPE r rw*

RESET

0 0 0 0 0 0 110100011 1

*This bit can be set by software but is cleared only by reset.

rw rw rw rw rw rw rw rw rw rw rw rw

Table 4-4. PLL Frequency Select Register Settings

Name Description Setting

QC PC

0x0347

CLK32

Bit 15

PROT

Bit 14

Reserved Bits 13–12

Bits 11–8

Bits 7–0

Clock32 Status—This read-only bit indicates the status of the CLK32 clock signal. The bit switches with each cycle of the CLK32 clock.

Protect Bit—This bit write protects the QC and PC fields of the PLLFSR. After this bit is set by software, the register is write protected until a reset clears this bit.

Reserved These bits are reserved and must remain at

Q Counter—This field contains the Q value that is used by the PLL to produce the PLLCLK.

P Counter—This field contains the P value that is used by the PLL to produce the PLLCLK.

0 = CLK32 low. 1 = CLK32 high.

0 = PLLFSR is not protect ed. 1 = PLLFSR is write protected.

their default value. Field value range is 1 <

Field value range is P >

Q<14.

Q+1.

4.5 Introduction to the Power Control Module

The purpose of the power control module (PCM) is to optimize the power consumption of the FLX68000 CPU by turning the CPU off for a programmed number of clock pulses. The CPU consumes more power than any comp onent in the MC68VZ328, so to conserve power while the CPU is relatively idle, the PCM can disable the CPU clock or apply the clock in bursts. When the MC68VZ328 is in one of these reduced-power modes, it is restored to normal operation by a wake-up eve nt. When this occ urs, the clock is immediately enabled, allowing the CPU to service the request. The DMA controller is not affected by the PCM having full access to the bus while the CPU is idle, keeping the LCD screen refreshed.

4-10 MC68VZ328 User’s Manual 

Introduction to the Power Control Module

4.5.1 Operating the PCM

The power control mod ule has f our modes of operation: normal, burst, d oze and sl eep. In nor mal mode, the PCM is off. The MC68VZ328 enters burst mode when the PCM is enabled. In burst mode, the PCM controls the burst width of the CPUCLK signal to the CPU. If the burst width of the CPU clock is reduced to zero, CPUCLK is disabled and the MC68VZ328 is in doze mode. The lowest power mode setting is sleep mode. It is entered by setting the disable PLL (DISPLL) bit in the PLLCR, which disables the PLL and thus disables ev ery clo ck si gnal i n the CGM ex cep t CLK32. Section 4.5.1.1, “Normal Mode,” through

Section 4.5.1.4, “Sleep Mode,” give detailed information about each of the four power modes.

4.5.1.1 Normal Mode

After reset, the PCM is disabled, the CPU clock runs continuously, and the MC68VZ328 consumes maximum power. This is normal mode.

4.5.1.2 Burst Mode

Setting the PCEN bit in the power control register (PCTRL) enables the PCM, causing the clock burst width of the CPU clock to be under the control of the PCTLR WIDTH settings in increments of 3 percent (one thirty-first of a cycle). Initially, the burst width is set to 100 percent. Software can then change the burst width to a lower value, and the clock is applied t o th e CPU in bur st s. The burs t-width register can be programmed for burst widths of any value between zero thirty-firsts and thirty-one thirty-firsts. This effectively produce s a sys te m clock with a variable burst width (an d power dis si pation) between 3 percent and 100 pe rcent in incremental steps of 3 percent.

When the PCM is enabled, if a wake-up event is received, the PCM is immediately disabled, restoring the continuous CPU clock. It is the responsibility of the wake-up service routine to reenable the PCM.

4.5.1.3 Doze Mode

Setting the width fiel d of PCTLR to %00000 reduces the burs t width of the CPU clock to zer o, causi ng the MC68VZ328 to enter doze mode. As with burst mode, the CPUCLK is immediately enabled when it receives a wake-up event. At the end of the service routine, the PCM can be reenabled with a width of %00000, putting the CPU back into doze mode. Once the CPU is placed in doze mode, only a wake-up event or h ardware reset will reenab le it.

NOTE:

The most effective power-control strategy is to run the CPU in normal mode until CPU action is not needed and then to enter doze mode by writing 0x80 into the PCTLR. This disables the CPU clock at the earliest possible moment, but allows the CPU to immediately respond to wake-up events. The peripheral devices, including the LCD controller, are not affected by the PCM.

 Clock Generation Module and Power Control Module 4-11

Introduction to the Power Control Module

4.5.1.4 Sleep Mode

Unlike burst or do ze mode, sleep mode disables all of th e clocks in the MC68VZ328 wit h the exception of the CLK32. The output of the PLL in th e CGM is disab led in slee p mode through sett ing the DISPLL b it in the PLLCR register. Only the 32 kHz clock works to keep the real-time clock operational. Wake-up events activate the PLL, and the system clock starts operating after a delay determined by the WKSEL setting in the PLLCR.

Other events that occur during sleep mode include:

• All Address Bus signals are in the active state of the last bus cycle.

• All data bus pins (D15–D0) are individually pulled up with 1-megaohm resistors.

• If CLK32 is selected as the c loc k sour ce, the gener al-pu rpo se ti mer oper ates even while the PLL is in sleep mode.

• The RTC interru pt status register ca n post interrupts while the system clock is in doze or sl eep mode.

4.5.2 CGM Operation During Sleep Mode

Shutting down the PLL to place the system in sleep mode is similar to the process used to change the frequency. The difference is that the system can be awakened only by a wake-up event or reset. Before shutting the PLL down, make sure that all peripheral devices are prepared for shutdown. The PLL shuts down 30 clock cycles of SYSCLK after the DISPLL bit is set in the PLLCR, allowing sufficient time to execute the stop instruction. When a wake-up event occurs, the PLL is enabled, and after a delay determined by the WKSEL set ting in th e PLLCR, the PLLCLK begin s, as do as th e rest of the c locks in t he divider chain of the CGM. The CPU executes an interrupt service routine for the level of the wake-up event.

After the rte instruction in the wake-up service routine, the CPU returns and starts execution on the instruction fo ll owing the stop ins tr uct ion. Example 4-2 illustrates a typi cal s hutdown sequence. It assumes that all peripherals have been shut down before the PLL is stopped.

Example 4-2. Shutdown Example

IRQMASK equ wake-up_mask_lev el ori.b #$8,PLLCONTROL+1 ;disable the PLL (in 30 clocks)

stop #IRQMASK ;stop, enable wake-up events ;the PLL shuts down here

;The PLL has reacquired lock and SYSCLK is stable ;interrupt service occurs he re

rts ;the system is operating

4.5.3 Burst Mode Operation

Figure 4-4 on page 4-13 shows a simplified block dia gram of the PCM. When operat ing at 100 perc ent, the SYSCLK input is unaf fecte d by burs t-widt h contr ol appear ing a s CPUCLK fr om the clock control . When a value has been placed in the width field of the PCTLR, the burst-width control allows the SYSCLK signal through to the clock control until the CPU clock’s time slot has expired and is to be disabled. At that time the clock control requests the bus from the CPU. After the bus is granted, the CPUCLK stops. A bus grant to the DMA controller is asserted, allowing the DMA controller complete access to the bus.

4-12 MC68VZ328 User’s Manual 

Introduction to the Power Control Module

CLK32

SYSCLK

CPU Bus

Request

Burst-Width

Control

Width

PCTLR

CPU Bus

Grant

CPU Interface

Wake-up

CPU Bus

Control

DMA Bus

Request

Clock

DMA Bus

CPUCLK

Grant

Figure 4-4. Power Control Module Block Diagram

If a wake-up event occurs while CPUCLK is disabled, the PCM is disabled and CPUCLK is immediately restored, allowing the CPU to process the event. The DMA controller always has priority, so if a DMA access is in progre ss , the CPU will wait u ntil the DMA cont ro ller has complet ed it s acces s bef ore s erv icing the wake-up routine. Note that the LCD DMA contro ller has access to the bus at all times and the SYSCLK (master clock to all peripherals) is continuously active.

Figure 4-5 illustrates how the PCM operates. As described previously, a width setting of %11111 represents 31 peri ods of CLK32, o r approxi mately 1 ms. In this example, th e width se tting i n the PCTLR is

00011. The clock bur sts are a pplie d a t a bu rst widt h of three th irty -fir sts, o r appr oximat ely at 1 0 perc ent on time, making the CPU active about 10 percent of the time. The remainder of the time, the CPU is in doze mode. When a wake-up event occurs, CPUCLK immediate ly returns to 100 perce nt so the CPU can service the wake-up event interrupt.

31 cycles

1 ms

CLK32

PCEN

SYSCLK

Clock Burst Width = %00011

CPUCLK

CPU Active CPU In activ e CPU Active Wake-up EventCPU Inactive

Figure 4-5. Power Control Operation in Burst Mode

Enabled Disabled

CPU Active

 Clock Generation Module and Power Control Module 4-13

Introduction to the Power Control Module

4.5.4 Power Control Register

The power control register (PCTLR) enabl es the p ower contr ol module and deter mines when t he CPUCLK signal is applied to the CPU. The settings for each bit and field in the register are described in Table 4-5.

PCTLR Power Control Register 0x(FF)FFF207

BIT 7654321BIT 0

PCEN

TYPE rw

RESET

00011111

rw rw rw rw rw

0x1F

Table 4-5. Power Control Register Description

Name Description Setting

WIDTH

PCEN

Bit 7

Reserved Bits 6–5

WIDTH

Bits 4–0

Power Control Enable—This bit controls the operation of the power control module. While this bit is low, the CPU clock is on continuously. When this bit is high, the pulse-width comparator presents the clock to the CPU in bursts or disables it. When this bit is high, a masked interrupt can disable the power control module.

Reserved These bits are reserve d and s hould rem ain se t

Width—This field controls the width of the CPU clock bursts in increments of one thirty-first. While this bit is set to 1 and the PCM is enabled, the clock is applied to the CPU in burst widths of one thirty-fir st (3 percent). When the width fi eld is 0x1 F, the cloc k is always on, and when it is 0, th e clock is always off. You can immediatel y wake it up ag ain without waiting for the PLL to reacquire lock. The contents of this field are not affected by the PCEN bit. When an interrupt disables the power control module, these bits are not changed.

0 = Power control is disabled (default). 1 = Power control is enabled.

to 0. 00000 = 0/31 clock burst width.

00001 = 1/31 clock burst width. 00010 = 2/31 clock burst width. . . . 11111 = 31/31 clock burst width.

4-14 MC68VZ328 User’s Manual 

Chapter 5

System Control

This chapter descr ibe s the system control r egi st er of t he MC68VZ328 microprocess or. The system control register enables system software to control and customize the following functions:

• Access permission from the internal peripheral registers

• Address space of the internal peripheral registers

• Bus time-out control and status (bus error generator)

5.1 System Control Operation

The on-chip resources use a reserved 4,096-byte block of address space for their registers. This block is mapped beginning a t location 0xFFFFF000 ( 32-bit) or 0xXXFFF00 0 (24-bi t, where XX i s “don’t care ”) on reset. The DMAP bit in the syst em control regis ter disab les double mapp ing in a 32-bi t system. If t his bit is cleared, the on-chip peripheral registers appear only at the top of the 4 Gbyte address range starting at 0xFFFFF000.

The system control register provides control of system operation functions such as bus interface and watchdog protection. The system control register contains status bits that allow exception handler code to interrogate the cause of both exceptions and resets. The bus time-out monitor and the watchdog timer provide system protection. The bus time-out monitor generates a bus error when a bus cycle is not terminated b y the DTACK

signal after 128 clock cycles have elapsed.

5.1.1 Bus Monitors and Watchdog Timers

The bus error time-out logic consists of a bus time-out monitor that, when enabled, begins to count clock cycles as the internal AS normally terminates the count, but if the count reaches terminal count before AS asserted until AS system control register. The BETO bit in the system control register is set after a bus time out, which may indicate a write-protect violation or privilege.

The watchdog timer resets the MC68VZ328 if it is enabled and not cleared or disabled before reaching terminal count. The watchdog timer is enabled at reset.

is deasserted. The bus error time-out logic consists of 1 control bit and 1 status bit in the

 System Control 5-1

pin is asserted for internal or external bus accesses. The deassertion of AS

is deasserted, BERR is

Programming Model

5.2 Programming Model

The following sections provide detailed programming information about the system control register and the other registers associated with its operation.

5.2.1 System Control Register

The 8-bit read/write system control register (SCR) resides at the address 0xFFFFF000 or 0xXXFFF000 (where XX is “don’t care”) after reset. The SCR and all other internal registers cannot be accessed in the

68000’s user mode if the SO bit is set to 1. The bit ass ign me nts for the re gis te r are shown in the fol lo w ing register display. The settings for the bits in the register are listed in Table 5-1.

SCR System Control Register 0x(FF)FFF000

BIT 7654321BIT 0

BETO WPV PRV BETEN SO DMAP

TYPE rw rw rw rw rw rw

RESET

00011100

0x1C

WDTH8

Table 5-1. System Control Register Description

Name Description Setting

BETO

Bit 7

WPV

Bit 6

PRV

Bit 5

Bus Error Time Out—This status bit indicates whether or not a bus-error-timer time out has occurred. When a bus cycle is not terminated by the DTACK elapsed, the BETO bit is set. However, the BETEN bit must be set for a bu s e rror time out to occur. This bit is cleared by writing a 1 (writing a 0 has no effect).

Write-Protect Violation—This status bit indicates that a write-protect violation has occurred. If a write-protec t v iolation occurs and the BETEN bit is not set, the current bus cycle will not terminate. The BETEN bit must be set for a bus error exception to occur during a write-protect violation. This bit is cleared by writing a 1 (writing a 0 has no effect).

Privilege Violation—This status bit indicates that if a privilege vi olatio n occ urs and the BETEN bit is not set, the cycle will not terminate. The BETEN bit must be set for a bus error exception to occur during a privilege violation. This bit is cleared by writing a 1 (writing a 0 has no effect).

signal after 128 clock cycles have

0 = A bus-error-timer time out did not occur. 1 = A bus-error-timer time out has occurred

because an undecoded address space has been accessed or b ecause a write-pr otect or privilege violation has occurred.

0 = A write-protect violation did not occur. 1 = A write-protect violation has occurred.

0 = A privilege violation did not occur. 1 = A privilege violation has occurred.

BETEN

Bit 4

Bit 3

Bus Error Time-Out Enable—This control bit enables the bus error timer.

Supervisor Only—This control bit limits on-chip registers to supervisor accesses only.

0 = Disable the bus error timer. 1 = Enable the bus error timer.

0 = User and supervisor mode. 1 = Supervisor-only mode.

5-2 MC68VZ328 User’s Manual 

Table 5-1. System Control Register Description (Continued)

Name Description Setting

Programming Model

DMAP

Bit 2

Reserved Bit 1

WDTH8

Bit 0

Double Map—This control bit controls the double-mapping fun cti on.

Reserved This bit is reserved and reads 0.

8-Bit Width Select—This control bit allows the D[7:0] pins to be used for Port A input/output.

0 = The on-chip registers are mapped at

0xFFFFF000–0xFFFFFFFF.

1 = The on-chip registers are mapped at

0xFFFFF000–0xFFFFFFFF and 0xXXFFF000–0xXXFFFFF (XX = “don’t care”).

0 = Not an 8-bit system. 1 = 8-bit system.

 System Control 5-3

Programming Model

5.2.2 Peripheral Control Register

This register controls the PWM logical block operation, timer TIN/TOUT signal, and UART UCLK signal. The bit assignments for t he register are shown in the followin g r egister display. The settings for the bits in the register are listed in Table 5-2.

PCR Peripheral Control Register 0x(FF)FFF003

BIT 7 6 5 4 3 2 1 BIT 0

UCLK P[1:0] T[1:0]

TYPE

000 0 0000

RESET

Table 5-2. Peripheral Control Register Description

Name Description Setting

rw rw rw rw rw

0x00

Reserved Bits 7–5

UCLK

Bit 4

P[1:0]

Bits 3–2

T[1:0]

Bits 1–0

Reserved Do not use these bits.

UART Clock Pin Configuration—When UCLK of UART 1 and UART 2 is configured to output signal, this bit selects UART 1’s or UART 2’s UCLK for UCLK pin output. When UCLK of UART 1 and UART 2 is configured as input, this bit is “don’t care,” and UC LK pin is an input si gnal.

PWM Outputs Logic Operation—These bits select the logical combination for final PWM pin output.

TIN/TOUT Signal Configuration—These 2 bits are used to configure the external TIN/TOUT signal when pin PB6/TIN/TOUT is selected as TIN/TOUT function. For detailed information on using this function, see Section 12.1.4, “TOUT/TIN/PB6 Pin,” on page 12-3.

0 = UCLK pin is connected to UART 1. 1 = UCLK pin is connected to UART 2.

00 = 8-bit PWM out only (default). 01 = 16-bit PWM out only. 10 = Logic OR of both PWM outputs. 11 = Logic AND of both PWM outputs.

00 = TIN/TOUT is connected to Timer 1. 01 = TIN/TOUT is connected to Timer 2. 10 = Timer 2 OUT -> Timer 1 IN; TIN -> Timer 2

(DIR6 = 0), or TOUT -> Timer 1 (DIR6 = 1).

11 = Timer 1 OUT -> Timer 2 IN; TIN -> Timer 1

(DIR6 = 0), or TOUT -> Timer 2 (DIR6 = 1).

5-4 MC68VZ328 User’s Manual 

Programming Model

5.2.3 ID Register

This 32-bit read- only register shows the chip identifica ti on. Th e bit assignments for the register are shown in the follow ing register display. The se ttings for the bits in the register are listed in Table 5-3.

IDR ID Register 0x(FF)FFF004

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT 16

CHIPID MASKID

TYPEr r r r r r rrrrrrrrr r

RESET

TYPE r r r r r r rrrrrrrrr r

RESET

0 1 0 1 0 1 100000000 0

0x5600

BIT 1514 13 12 11 10 987654321BIT 0

SWID

0 0 0 0 0 0 000000000 0

0x0000

Table 5-3. ID Register Description

Name Description Setting

CHIPID

Bits 31–24

MASKID

Bits 23–16

SWID

Bits 15–0

Chip ID Field—This field contains the chip identification number for the DragonBall series MPU.

Maskset ID Field—This field contains the maskset number for the silicon. See description

Software ID—This field contains the custom software ID. It is normally “0000.” See description

See description

 System Control 5-5

Programming Model

5.2.4 I/O Drive Control Register

This register controls the driving strength of all I/O signals. By default, all pins are defaulted to 4 mA driving current. After reset, system software should select 2 mA driving for those signals that do not need high-current driving for power saving. The bit assignments for the register are shown in the following display. The settings fo r the bits in th e register are listed in Ta ble 5-4.

IODCR I/O Drive Control Register 0x(FF)FFF008

BIT 1514 13 12 11 10 987654321BIT 0

AB DB CB PM PK PJ PG PF PE PD PC PB PA

TYPE

0 0 0 1 1 1 1111111111

RESET

Table 5-4. I/O Drive Control Register Description

Name Description Setting

rw rw rw rw rw rw rw rw rw rw rw rw rw

0x1FFF

Reserved Bits 15–13

Bit 12

Bit 11

Bit 10

PM–PA

Bits 9–0

Reserved Do not use these bits.

Address Bus Signals I/O D rive Control—It should be noted that A[23:20] are controlled by the PF bit.

Upper Data Bus Signals I/O Drive Control—The lower data bus is controlled by the PA bit.

Control Bus Signals—Only those signals or functions not multiplexed with GPIO are controlled by this bit.

Port M to Port A Group I/O Drive Control—Each bit controls the drive current for the lines in the respective port.

0 = I/O drive current for each pin is 2 mA. 1 = I/O drive current for each pin is 4 mA.

5-6 MC68VZ328 User’s Manual 

Chapter 6

Chip-Select Logic

This chapter describes the chip-select logic’s function and operation and provides programming information for controlling its operation.

6.1 Overview of the CSL

The MC68VZ328 microprocessor contains eight general-purpose, programmable chip-select signals, which are used to select external devices on the address and data bus. The signals are arranged in four groups of two—C

SA0 is a special-purpose chip-select signal, which is the boot device chip-select. After reset, in normal

C mode all the addresses are mapped to CSA0 and the chip-select enable (EN) bit is set in the appropriate chip-select register. From that point forward,

does not decode globally and is only asserted when decoded from the programming information in

CSA0 the chip-select register.

SA[1:0], CSB[1:0], CSC[1:0], an d CSD[1 :0 ].

until such time that the group base address A is programmed

Group C (CSC0 programmed as row address strobe (RAS0 DRAM interface. For details, refer to Section 7.3.2, “DRAM Control Register,” on page 7-14 and Section 6.3.3, “Chip-Select Registers,” in this chapter.

Each memory area can be defined as an inte rnally genera ted cycle- terminati on signal, ca lled DTACK a programmable number of wait states. This feature saves board space that would otherwise be used for cycle-termination logic . Usi ng CDL, t he syst em desi gner can adopt a fle xible memory c onfigur atio n base d on cost and availability. Up to four different classes of devices and memory can be used in a system without the need for e xte rnal decode or wait- st ate ge ner at ion l ogi c. Specifically, 8- o r 16-b it combinations of ROM, SRAM, flash memory and DRAM (EDO RAM, Fast Page Mode, or sync hronous) are s upporte d, as shown in Table 6-1 on page 6-2.

/CSC1) and Group D (CSD0/CSD1) chip-selects are unique in that they can also be

/RAS1) and column address strobe (CAS0/CAS1) for the

, with

 Chip-Select Logic 6-1

Chip-Select Operation

Chip-Select Signal Memory Supported

Table 6-1. Chip-Select and Memory Types

CSA0 CSA1 CSB0 CSB1

CSC0

/RAS0 DRAM, ROM, SRAM, flash memory chip-select

CSC1

/RAS1 DRAM, ROM, SRAM, flash memory chip-select

CSD0

/CAS0 DRAM, ROM, SRAM, flash memory chip-select

CSD1

/CAS1 DRAM, ROM, SRAM, flash memory chip-select

ROM, SRAM, flash memory chip ROM, SRAM, flash memory chip ROM, SRAM, flash memory chip ROM, SRAM, flash memory chip

The basic chip-select model allows the chip-select output signal to assert in response to an address match. The signals are asserted externally shortly after the internal Address Strobe (AS

) signal goes low. The address match is descr ibed in t erms of a gr oup base ad dress reg ister and a c hip-sele ct regis ter. The memor y size of the chip-select can be selected from a set of predefined ranges (32K, 64K, 128K, 256K, 512K, 1 Mbyte, 2 Mbyte, 4 Mbyte, 8 Mbyte, or 16 Mbyte). These memory ranges represent the most popular memory sizes available on the market and apply to the registers CSB, CSC, and CSD. The CSA register primarily supports ROM, which is usually 128K to 16 Mbyte. Using this scheme, it is easy to design software without the necessity of programming a chip-select mask register.

The chip-select ca n be prog rammed t o allow r ead-only or read /write acce sses. Othe r paramet ers tha t can be programmed include the number of wait states (from 0 to 13), data bus size selection, and whether a

TACK signal is automatically generated for the chip-select logic.

6.2 Chip-Select Operation

A chip-select output signal is asserted when an address is matched and after the AS signal goes low. The base address and address mask registers are used in the compare logic to generate an address match. The byte size of t he mat ching blo ck must be a power of two and th e base addr ess must b e an i ntege r multip le of this size. Therefore, an 8K block size must begin on an 8K boundary, and a 64K block size can onl y begi n on a 64K boundary. Each chip-select is programmable, and the registers have read/write capability so that the programmed values can be read back.

NOTE:

The chip-select logic does not allow an address match during interrupt acknowledge (Function Code 7) cycles.

6.2.1 Memory Protection

The chip-select range of the four chip-selects can be programmed as read-only or read/write. Chip-selects that control the crucial system data are usually programmed as supervisor-only and read-only so they can be protected from system misuse (for example, a low battery). However, a certain area of this

6-2 MC68VZ328 User’s Manual 

Chip-Select Operation

chip-select–controlled area can be programmed as read/write, which provides optimal memory use, as shown in Figure 6-1. This area can be defined by programming the UPSIZ bits in th e CSB, CSC, and CSD registers to between 32K and the entire chip-select area.

Unprotected Memory (Read/Write)

Up to 4 Mbyte

Memory

Map

Figure 6-1. Size Selection and Memory Protection for CSB0 and CSB1

RAM

CSB0

CSB1

Up to 16 Mbyte

Protected Memory (Supervisor-Only, Read-Only)

6.2.2 Programmable Data Bus Size

Each chip-select can be conf igu re d to address an 8- or 16-bit space . Both 16- and 8-bit contiguou s add res s memory devices can be mixed o n a 16-b it data bu s syst em. If the CPU pe rforms a 16-bi t dat a transf er in a n 8-bit memory space, then two 8-bit cycles will occur. However, the address and data strobes remain asserted until the end of the second 8-bit cycle. In this case, only the external CPU data bus upper byte (D[15:8]) is used, and the least significant bit of the address (A0) increment s automat ically fro m one to the next. A0 should be ignored in 16-bit data bus cycles even if only the upper or lower byte is being read or written. For an external peripheral that only needs an 8-bit data bus interface and does not require contiguous address locations (unused bytes on empty addresses), use a chip-select configured to a 16-bit data bus width and c onnect to the D[7:0] pi ns. This balances the l oad of t he two data bus halve s i n an 8-bit system. The internal data bus is 16 bits wide. All internal registers can be read or written in a zero wait-state cycle.

Except for CSA0

and EMUCS, all chip-select signals are disabled by default. The data bus width (BSW) field of the chip-select option register enables 16- and 8-bit data bus widths for each of the 16 chip-select ranges. The initia l bus width for th e boot chip -select can be s elected b y placing a logic 0 or 1 on the BUSW pin at reset to sp ecify the width of the data bus. This a llows a boo t EPROM of the data bus wi dth to be used in any given system. All external accesses that do not match one of the chip-select address ranges are assumed to be a 16-bit devi ce. This results in a single access performe d for a 16-bit tr ansfer. If it i s applied to an 8-bit port, the port is accessed every other byte.

The boot chip-select is initia lized fr om reset to ass ert in resp onse to any address exce pt the on-ch ip regist er space (0xFFFFF000 to 0xFFFFFFFF). This ensures that a chip-select to the boot ROM or EPROM will fetch the reset vector and execute the initialization code, which should set up the chip-select ranges.

A logic 0 on the BUSW pin sets the boot device’s data bus to be 8 bits wide, and a logic 1 sets it to be 16 bits wide. At reset, the data bus port size for CSA0

and the data width of the boot ROM device are determined by the state of BUSW. The other chip-selects are initialized to be nonvalid, so they will not assert until they are programmed and the EN bit is set in the chip-select registers.

 Chip-Select Logic 6-3

Programming Model

6.2.3 Overlapping Chip-Select Registers

Do not program group address and chip-select registers to overlap, or the chip-select signals will overlap. Unused chip-selects must be disabled. Map them to an unused space, if possible.

When the CPU tries to write to a read -only l ocati on that ha s alrea dy be en progra mmed, the chip-s el ect and DTACK

signals will not be gene rated internal ly . BERR will be asserted internally if the bus error time-out

function is enabled.

NOTE:

The chip-select logic does not allow an address match during interrupt acknowledge cycles.

6.3 Programming Model

The chip-select module contains registers that are programmed to control external devices, such as memory. Chip-selects d o not operate until the register in a particular group of devices is init i ali ze d a nd the EN bit is set in the corres pon din g chip-select register. The only exception is the CSA0 boot device chip-selec t.

signal, which is the

6.3.1 Chip-Select Group Base Address Registers

The upper 15 bits of each base address register selects the starting address for the chip-select address range. The GBAx field i s compared to the add res s on t he address bus to de te rmi ne if the group is dec oded . The chip-select base address must be set according to the size of the corresponding chip-select signals of the group. For example, if CSA1 register must be s et in a 4 Mbyte space boundary, such as syst em address 0 and so on. It cannot be set at 0

CSGBA Chip-Select Group A Base Address Register 0x(FF)FFF100

BIT

14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0

A28GBA27GBA26GBA25GBA24GBA23GBA22GBA21GBA20GBA19GBA18GBA17GBA16GBA15GBA14

TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RESET

GBAx

Bits 15–1

000000000000000 0

Table 6-2. Chip-Select Group A Base Address Register Description

Name Description Setting

Group A Base Address—These bits select

the high-order bits (28–14) of the starting address for the chip-select range.

and CSA0 are each assigned a 2 Mbyte memory space, the CSGBA

× 0, 0 × 4 Mbyte, 0 × 8Mbyte,

× 1 Mbyte, 0 × 2Mbyte, 0× 3 Mbyte, 0 × 5 Mbyte, and so on.

0x0000

The chip-select base address must be set according to the size of the corresponding chip-select signals of the group.

Reserved Bit 0

6-4 MC68VZ328 User’s Manual 

Reserved This bit is reserved and should be set to 0.

Programming Model

CSGBB Chip-Select Group B Base Address Register 0x(FF)FFF102

BIT

1413121110987654321

B28GBB27GBB26GBB25GBB24GBB23GBB22GBB21GBB20GBB19GBB18GBB17GBB16GBB15GBB14

TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RESET

0000000000000000

0x0000

BIT

Table 6-3. Chip-Select Group B Base Address Register Description

Name Description Setting

GBBx

Bits 15

–1

Reserved

Group B Base Address

the high-order bits (28–14) of the starting address for the chip-select range.

Reserved This bit is reserved and should be set to 0.

—These bits select

The chip-select base address must be set according to the size of the corresponding chip-select signals of the group.

Bit 0

CSGBC Chip-Select Group C Base Address Register 0x(FF)FFF104

BIT

1413121110987654321

TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RESET

0000000000000000

0x0000

BIT

Table 6-4. Chip-Select Group C Base Address Register Description

Name Description Setting

GBCx

Bits 15–1

Reserved

Group C Base Address—These bits select the high-order bits (28–14) of the starting address for the chip-select range.

The chip-select base address must be set according to the size of the corresponding chip-select signals of the group.

Reserved This bit is reserved and should be set to 0.

Bit 0

 Chip-Select Logic 6-5

Programming Model

CSGBD Chip-Select Group D Base Address Register 0x(FF)FFF106

BIT

1413121110987654321

TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RESET

0000000000000000

0x0000

BIT

Table 6-5. Chip-Select Group D Base Address Register Description

Name Description Setting

GBDx

Bits 15

–1

Reserved

Group D Base Address

the high-order bits (28–14) of the starting address for the chip-select range.

Reserved This bit is reserved and should be set to 0.

—These bits select

The chip-select base address must be set according to the size of the corresponding chip-select signals of the group.

Bit 0

6.3.2 Chip-Select Upper Group Base Address Register

The default setti ng for c hip-se lect deco ding li mits ad dre ssing t o A28. When the ful l addr ess deco de enabl e (UGEN) bit is set, it allows full address decoding. Full address decoding is enabled for all four of the chip-select regi ster s by t he UGEN b it i n the chip- sele ct upp er gr oup bas e add ress regis ter (CSUGBA). The bit value of the MSB for each of the four chip-select registers can be written into each of the four MSB fields in this register. The settings for this register are shown in Table 6-6.

CSUGBA Chip-Select Upper Group Base Address Register 0x(FF)FFF108

BIT

1413121110987654321

TYPE rw rw rw rw

RESET

0000000000000000

AGBA[31:29]

BGBA[31:29] CGBA[31:29] DGBA[31:29]

rw rw rw rw rw rw rw rw rw

0x0000

Table 6-6. Chip-Select Upper Group Base Address Register Description

Name Description Setting

UGEN

Bit 15

AGBA[31:29]

Bits 14–12

Full Address Decode Enable—This bit enables full address range decoding for all chip-select registers.

MSB for Chip-Select A—The upper most significant bits for chip-select group A base address. The value will be ignored if UGEN is disabled.

0 = Ignores A31, A30, and A29. 1 = Decoding includes A31, A30, and A29.

Enter value for bits 31–29 of chip-select register A.

BIT

6-6 MC68VZ328 User’s Manual 

Programming Model

Table 6-6. Chip-Select Upper Group Base Address Register Description (Continued)

Name Description Setting

Reserved Bit 11

BGBA[31:29]

Bits 10–8

Reserved Bit 7

CGBA[31:29]

Bits 6–4

Reserved Bit 3

DGBA[31:29]

Bits 2–0

Reserved This bit is reserved and should be set to 0.

MSB for Chip-Select B—The upper most significant bits for chip-select group B base address. The value will be ignored if UGEN is disabled.

Reserved This bit is reserved and should be set to 0.

MSB for Chip-Select C—The upper most significant bits for chip-select group C base address. The value will be ignored if UGEN is disabled.

Reserved This bit is reserved and should be set to 0.

MSB for Chip-Select D—The upper most significant bits for chip-select group D base address. The value will be ignored if UGEN is disabled.

Enter value for bits 31–29 of chip-select register B.

Enter value for bits 31–29 of chip-select register C.

Enter value for bits 31–29 of chip-select register D.

 Chip-Select Logic 6-7

Programming Model

6.3.3 Chip-Select Registers

There are four 16-bit chip-select (CSA, CSB, CSC, and CSD) registers for each corresponding chip-select base address register. Each register controls two chip-select signals and can be configured to select the memory type and size of t he me mory range supported as we ll as to program the required wait states or use the external DTACK page 6-14.

CSA Chip-Select Register A 0x(FF)FFF110

signal. The settings for the register s are descr ibed in Tabl e 6-7 through Table 6-10 on

BIT

TYPE rw

RESET

14 13 12 11 10 9 8 7 654321

FLASH BSW WS3–1 SIZ EN

rw rw rw rw rw rw rw rw w

0 0 0 0 0 0 0 0 1 011000 0

0x00B0

Table 6-7. Chip-Select Register A Description

Name Description Setting

Bit 15

Reserved Bits 14–9

FLASH

Bit 8

Read-Only—This bit sets the chip-select to read-only. Otherw i se , rea d and write access es are allowed. A write to a read-only area will generate a bus error if the BETEN bit of the SCR is set. See Section 5.2.1, “System Control Register,” on page 5-2 for more information.

Reserved These bits are reserved and should be set to 0.

Flash Memory Support—When enabled, this bit provid es support for flash memory by forcing the LWE chip-select.

Note: This bit is used for expanded memory size for CSD when the DRAM bit in the CSD register is enabled.

/UWE signal to go active after

0 = Read/write. 1 = Read-only.

0 = The chip-select and LWE

at the same clock edge.

1 = The chip-select signal goes low 1 clock before

/UWE.

LWE

BIT

/UWE signals go active

BSW

Bit 7

WS3–1

Bits 6–4

Data Bus Width—This bit sets the data bus width for this chip-select area.

Wait State—This field determines the number of wait states add ed before an internal DTACK signal is returned for this chip-select.

Note: When using the external DTACK signal, you must configure the BUSW/DTACK

/PG0 pin.

0 = 8 bit. 1 = 16 bit.

000 = 0 + WS0 wait states. 001 = 2 + WS0 wait states. 010 = 4 + WS0 wait states. 011 = 6 + WS0 wait states. 100 = 8 + WS0 wait states. 101 = 10 + WS0 wait states. 110 = 12 + WS0 wait states. 111 = External DTACK

When using the external DTACK signal, you must select DTACK

WS0 is the DWS0, CWS0, BWS0, or AWS0 bit in the CSCTRL1 register.

function in Port G.

6-8 MC68VZ328 User’s Manual 

Table 6-7. Chip-Select Register A Description (Continued)

Name Description Setting

Programming Model

SIZ

Bits 3–1

Bit 0

Chip-Select Size—This field determines the memory range of the chip-select. For CSAx and CSBx 128K and 16 Mbyte. For CSCx chip-select size is between 32K and 16 Mbyte.

Chip-Select Enable—This write-only bit enables each chip-select.

, the chip-select size is between

and CSDx, the

000 = 128K (32K or 8 Mbyte* for CSCx 001 = 256K (64K or 16Mbyte* for CS Cx 010 = 512K (128K for CSCx 011 = 1 Mbyte (256K for CSCx 100 = 2 Mbyte (512K for CSCx 101 = 4 Mbyte (1 Mbyte for CSCx 110 = 8 Mbyte (2 Mbyte for CSCx 111 = 16 Mbyte (4 Mbyte for CSCx

* Note: Large DRAM size selection requires the DSIZ3 bit in the chi p-select control registe r to be set.

0 = Disabled. 1 = Enabled.

and CSDx).

and CSDx). and CSDx).

and CSDx).

and CSDx). and CSDx).

and CSDx).

 Chip-Select Logic 6-9

Programming Model

CSB Chip-Select Register B 0x(FF)FFF112

BIT

RO SOP ROP UPSIZ

TYPE rw rw rw rw

RESET

14 13 12 11 10 9 8 7 6 5 4 3 2 1

FLASH BSW WS3–1 SIZ EN

rw rw rw rw rw rw rw rw w

0 0 0 0 000 0 0 000000 0

0x0000

Table 6-8. Chip-Select Register B Description

Name Description Setting

Bit 15

SOP

Bit 14

Read-Only—This bit sets the chip-select to read-only. Otherwise, read and write accesses are allowed. A write to a read-only area will generate a bus error if the BETEN bit of the SCR is set. See Section 5.2.1, “System Control Register,” on page 5-2 for more information.

Supervisor-Use-Only Protected Memory Block—This bit sets the protected

memory block to supervisor-only; otherwise, both supervisor and user accesses are allowed. Attempts to access the su pervisor-only area result in a bus error if the BETEN bit of the SCR is set. See Section 5.2.1, “System Control Register,” on page 5-2 for more information.

0 = Read/write. 1 = Read-only.

0 = Supervisor/user. 1 = Supervisor-only.

BIT

ROP

Bit 13

UPSIZ

Bits 12–11

Reserved Bits 10–9

FLASH

Bit 8

BSW

Bit 7

Read-Only for Protected Memory Block—This bit sets the protected mem-

0 = Read/write.

1 = Read-only. ory block to read-only. Otherwise, read and write accesses are allowed. If you write to a read-only area, you will get a bus error.

Unprotected Memory Block Size—This field determines the unprotected memory range of the chip-select.

00 = 32K.

01 = 64K.

10 = 128K.

11 = 256K. Reserved These bits are reserved and should be set to 0.

Flash Memory Support—W hen e nab led , this bit provides support for flash memory by forcing the LWE

/UWE signal to go

active after chip-select.

0 = The chip-select and LWE/UWE signals go active at

the same clock edge.

1 = The chip-select signal goes low 1 clock before

/UWE.

LWE

Note: This bit is used for expanded memory size for CSD when the DRAM bit in the CSD register is enabled.

Data Bus Width—This bit sets the data bus width for this chip-select area.

0 = 8 bit.

1 = 16 bit.

6-10 MC68VZ328 User’s Manual 

Table 6-8. Chip-Select Register B Description (Continued)

Name Description Setting

Programming Model

WS3–1

Bits 6–4

SIZ

Bits 3–1

Bit 0

Wait State—This field determines the number of wait states added before an internal DTACK signal is returned for this chip-select.

Note: When using the external DTACK signal, you must configure the BUSW/DTACK

Chip-Select Size—This field determines the memory range of the chip-select. For CSAx

and CSBx, the chip-select size is between 128K and 16Mbyte. For CSCx and CSDx 32K and 16 Mbyte.

Chip-Select Enable—This write-only bit enables each chip-select.

/PG0 pin.

, the chip-select size is between

When using the external DTACK select DTACK

WS0 is the DWS0, CWS0, BWS0, or AWS0 bit in the CSCTRL1 register.

000 = 128K (32K or 8 Mbyte* for CSCx 001 = 256K (64K or 16Mbyte* for CSCx 010 = 512K (128K for CSCx 011 = 1 Mbyte (256K for CSCx 100 = 2 Mbyte (512K for CSCx 101 = 4 Mbyte (1 Mbyte for CSCx 110 = 8 Mbyte (2 Mbyte for CSCx 111 = 16 Mbyte (4 Mbyte for CSCx

* Note: Large DRAM size selection requires the DSIZ3 bit in the chip-select control register to be set.

0 = Disabled . 1 = Enabled.

function in Port G.

signal, you must

and CSDx).

and CSDx). and CSDx).

and CSDx).

 Chip-Select Logic 6-11

Programming Model

CSC Chip-Select Register C 0x(FF)FFF114

BIT

RO SOP ROP UPSIZ

TYPE rw rw rw rw

RESET

14 13 12 11 10 9 8 7 6 5 4 3 2 1

FLASH BSW WS3–1 SIZ EN

rw rw rw rw rw rw rw rw w

0 0 0 0 0 00 0 0 00000 0 0

0x0000

Table 6-9. Chip-Select Register C Description

Name Description Setting

Bit 15

Read-Only—This bit sets the chip-select to read-only. Otherwise, read and write

0 = Read/write.

1 = Read-only. accesses are allowed. A write to a read-only area will generate a bus error if the BETEN bit of the SCR is set. See Section 5.2.1, “System Control Register,” on page 5-2 for more information.

SOP

Bit 14

Supervisor-Use-Only Protected Memory Block—This bit sets the protected

0 = Supervisor/user.

1 = Supervisor-only. memory block to supervisor-only; otherwise, both supervisor and user accesses are allowed. Attempts to access the su pervisor-only area result in a bus error if the BETEN bit of the SCR is set. See Section 5.2.1, “System Control Register,” on page 5-2 for more information.

BIT

ROP

Bit 13

UPSIZ

Bits 12–11

Reserved Bits 10–9

FLASH

Bit 8

BSW

Bit 7

Read-Only for Protected Memory Block—This bit sets the protected mem-

0 = Read/write.

1 = Read-only. ory block to read-only. Otherwise, read and write accesses are allowed. If you write to a read-only area, you will get a bus error.

Unprotected Memory Block Size—This field determines the unprotected memory range of the chip-select.

00 = 32K.

01 = 64K.

10 = 128K.

11 = 256K. Reserved These bits are reserved and should be set to 0.

Flash Memory Support—W hen e nab led , this bit provides support for flash memory by forcing the LWE

/UWE signal to go

active after chip-select.

0 = The chip-select and LWE/UWE signals go active at

the same clock edge.

1 = The chip-select signal goes low 1 clock before

/UWE.

LWE

Note: This bit is used for expanded memory size for CSD when the DRAM bit in the CSD register is enabled.

Data Bus Width—This bit sets the data bus width for this chip-select area.

0 = 8 bit.

1 = 16 bit.

6-12 MC68VZ328 User’s Manual 

Motorola MC68VZ328 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

 Table of Contents iii

List of Figures

List of Tables

List of Examples

About This Book

1.1 Features of the MC68VZ328

1.2 CPU

1.2.1 CPU Programming Model

1.2.2 Data and Address Mode Types

1.2.3 FLX68000 Instruction Set

1.3 Modules of the MC68VZ328

1.3.1 Memory Controller

1.3.2 Clock Generation Module and Power Control Module

1.3.3 System Control

1.3.4 Chip-Select Logic

1.3.5 DRAM Controller

1.3.6 LCD Controller

1.3.7 Interrupt Controller

1.3.8 General-Purpose I/O (GPIO) Lines

1.3.9 Real-Time Clock

1.3.10 General-Purpose Timer

1.3.11 Serial Peripheral Interfaces (SPI)

1.3.13 Pulse-Width Modulators (PWM)

1.3.14 In-Circuit Emulation Module

1.3.15 Bootstrap Mode

2.1 Signals Grouped by Function

2.2 Power and Ground Signals

2.3 Clock and System Control Signals

2.4 Address Bus Signals

2.5 Data Bus Signals

2.6 Bus Control Signals

2.7 Interrupt Controller Signals

2.8 LCD Controller Signals

2.9 UART 1 and UART 2 Controller Signals

2.10 Timer Signals

2.11 Pulse-Width Modulator Signals

2.12 Serial Peripheral Interface 1 Signals

2.13 Serial Peripheral Interface 2 Signals

2.14 Chip-Select and EDO RAM Interface Signals

2.15 SDRAM Interface Signals

2.16 In-Circuit Emulation (ICE) Signals

3.1 Programmer’s Memory Map

4.1 Introduction to the Clock Generation Module

4.2 CGM Operational Overview

4.3 Detailed CGM Clock Descriptions

4.3.1 CLK32 Clock Signal

4.3.2 PLLCLK Clock Signal

4.3.2.1 PLLCLK Initial Power-up Sequence

4.3.2.2 PLL Frequency Selection

4.3.2.3 PLLCLK Frequency Selection Programming Example

4.3.2.4 Programming Considerations When Changing Frequencies

4.4 CGM Programming Model

4.4.1 PLL Control Register

4.4.2 PLL Frequency Select Register

4.5 Introduction to the Power Control Module

4.5.1 Operating the PCM

4.5.1.1 Normal Mode

4.5.1.2 Burst Mode

4.5.1.3 Doze Mode

4.5.1.4 Sleep Mode

4.5.2 CGM Operation During Sleep Mode

4.5.3 Burst Mode Operation

4.5.4 Power Control Register

5.1 System Control Operation

5.1.1 Bus Monitors and Watchdog Timers

5.2 Programming Model

5.2.1 System Control Register

5.2.2 Peripheral Control Register

5.2.3 ID Register

5.2.4 I/O Drive Control Register

6.1 Overview of the CSL

6.2 Chip-Select Operation

6.2.1 Memory Protection

6.2.2 Programmable Data Bus Size

6.2.3 Overlapping Chip-Select Registers

6.3 Programming Model