Motorola MC68HC908GP32 Technical Data Manual

MOTOROLA.COM/SEMICONDUCTORS

M68HC08

Microcontrollers

MC68HC908GP32/H
Rev. 6, 8/2002

MC68HC908GP32
MC68HC08GP32

Te c h n i c a l D a t a

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA 1

MC68HC908GP32
MC68HC08GP32

Technical Data

Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and the Stylized M logo are registered trademarks of Motorola, Inc.
digital dna is a trademark of Motorola, Inc. © Motorola, Inc., 2002

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Revision History

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

2 MOTOROLA

To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:

http://motorola.com/semiconductors

The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.

Revision History

Date

Revision

Level

Description

Page

Number(s)

August, 2002 6

Section 22. Timer Interface Module (TIM) — Timer

discrepancies corrected throughout this section.

341

Section 24. Mechanical Specifications — Replaced incorrect

44-pin QFP drawing, case 824E to case 824A.

393

July, 2001 5

In Table 15-1, second cell in "Comment" column, corrected PTC
to PTC1.

199

In Figure 21-2, Timebase control register, bit 0 is a reserved bit. 337

Updated crystal oscillator component values in 23.17.1 CGM

Component Specifications.

387

Added appendix A: MC68HC08GP32 — ROM part. 397

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA List of Sections 3

Technical Data – MC68HC908GP32•MC68HC08GP32

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . .31

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .43

Section 3. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .57

Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 69

Section 5. Analog-to-Digital Converter (ADC) . . . . . . . . 87

Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . .97

Section 7. Clock Generator Module (CGMC) . . . . . . . . 105

Section 8. Configuration Register (CONFIG) . . . . . . . .137

Section 9. Computer Operating Properly (COP) . . . . .141

Section 10. Central Processor Unit (CPU) . . . . . . . . . . 147

Section 11. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . 165

Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . 175

Section 13. Keyboard Interrupt Module (KBI). . . . . . . . 181

Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 189

Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 195

Section 16. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 211

Section 17. Random-Access Memory (RAM) . . . . . . . . 235

Section 18. Serial Communications Interface

Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . 237

Section 19. System Integration Module (SIM) . . . . . . .277

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List of Sections

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

4 List of Sections MOTOROLA

Section 20. Serial Peripheral Interface Module (SPI) . . 303

Section 21. Timebase Module (TBM). . . . . . . . . . . . . . .335

Section 22. Timer Interface Module (TIM) . . . . . . . . . . . 341

Section 23. Electrical Specifications. . . . . . . . . . . . . . .365

Section 24. Mechanical Specifications . . . . . . . . . . . . . 391

Section 25. Ordering Information . . . . . . . . . . . . . . . . . 395

Appendix A. MC68HC08GP32 . . . . . . . . . . . . . . . . . . . . 397

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Table of Contents 5

Technical Data – MC68HC908GP32•MC68HC08GP32

Table of Contents

Section 1. General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3.1 Standard Features of the MC68HC908GP32. . . . . . . . . . . .32

1.3.2 Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

1.6.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . .39

1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40

1.6.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . .40

1.6.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

1.6.5 CGM Power Supply Pins (V

DDA

and V

SSA

) . . . . . . . . . . . . .41

1.6.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .41

1.6.7 ADC Power Supply/Reference Pins
(V

DDAD/VREFH

and V

SSAD/VREFL

) . . . . . . . . . . . . . . . . . .41

1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7

–PTA0/KBD0) .41

1.6.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .41

1.6.10 Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . .42

1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . .42

1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

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Table of Contents

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

6 Table of Contents MOTOROLA

Section 2. Memory Map

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .43

2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Section 3. Low-Power Modes

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59

3.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60

3.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7 Computer Operating Properly Module (COP). . . . . . . . . . . . . .61

3.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.8 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62

3.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62

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Table of Contents

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Table of Contents 7

3.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63

3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .63

3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .64

3.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . .64

3.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Section 4. Resets and Interrupts

4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.3.3 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4.3.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4.3.3.2 COP Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.3 Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.3.4 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .74

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Table of Contents

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

8 Table of Contents MOTOROLA

4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

4.4.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

4.4.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.4.2.1 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.3 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.4 CGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.5 TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.6 TIM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.4.2.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.4.2.8 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

4.4.2.9 KBD0–KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.2.10 ADC (Analog-to-Digital Converter). . . . . . . . . . . . . . . . . .83

4.4.2.11 TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.3 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.4.3.1 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .85

4.4.3.2 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .85

4.4.3.3 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .86

Section 5. Analog-to-Digital Converter (ADC)

5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

5.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

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Table of Contents

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Table of Contents 9

5.7.1 ADC Analog Power Pin (V

DDAD

)/

ADC Voltage Reference High Pin (V

REFH

) . . . . . . . . . . .92

5.7.2 ADC Analog Ground Pin (V

SSAD

)/

ADC Voltage Reference Low Pin (V

REFL

) . . . . . . . . . . . .92

5.7.3 ADC Voltage In (V

ADIN

) . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

5.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . .93

5.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

5.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Section 6. Break Module (BRK)

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

6.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .100

6.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

6.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .100

6.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

6.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

6.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .101

6.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .102

6.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6.6.4 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . .104

Section 7. Clock Generator Module (CGMC)

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

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7.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .109

7.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . .109

7.4.3 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

7.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . .111

7.4.5 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . .111

7.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

7.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . .117

7.4.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .117

7.4.9 CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . 118

7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .119

7.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .119

7.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .120

7.5.4 PLL Analog Power Pin (V

DDA

) . . . . . . . . . . . . . . . . . . . . . .120

7.5.5 PLL Analog Ground Pin (V

SSA

) . . . . . . . . . . . . . . . . . . . . .120

7.5.6 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .120

7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB) . . . . . .120

7.5.8 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .121

7.5.9 CGMC Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .121

7.5.10 CGMC CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . .121

7.6 CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

7.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

7.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . .125

7.6.3 PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . .127

7.6.4 PLL Multiplier Select Register Low. . . . . . . . . . . . . . . . . . .128

7.6.5 PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . .129

7.6.6 PLL Reference Divider Select Register . . . . . . . . . . . . . . .130

7.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

7.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

7.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

7.8.3 CGMC During Break Interrupts . . . . . . . . . . . . . . . . . . . . .132

7.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .133

7.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .133

7.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .134

7.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

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Section 8. Configuration Register (CONFIG)

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Section 9. Computer Operating Properly (COP)

9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

9.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

9.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

9.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .144

9.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .146

Section 10. Central Processor Unit (CPU)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

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10.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

10.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

10.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .155

10.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

Section 11. FLASH Memory

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .167

11.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .168

11.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .169

11.8 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . .172

11.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

11.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

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Section 12. External Interrupt (IRQ)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

12.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

12.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .179

12.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .179

Section 13. Keyboard Interrupt Module (KBI)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .186

13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

13.8.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .187

13.8.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . .188

Section 14. Low-Voltage Inhibit (LVI)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

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14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

14.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .192

14.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .192

14.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

Section 15. Monitor ROM (MON)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

15.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .198

15.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4.3 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15.4.4 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

15.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Section 16. Input/Output (I/O) Ports

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

16.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

16.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .216

16.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . .218

16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

16.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

16.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .220

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16.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

16.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

16.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .223

16.5.3 Port C Input Pullup Enable Register. . . . . . . . . . . . . . . . . .225

16.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

16.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

16.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . .228

16.6.3 Port D Input Pullup Enable Register. . . . . . . . . . . . . . . . . .230

16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

16.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

16.7.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . .232

Section 17. Random-Access Memory (RAM)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

Section 18. Serial Communications

Interface Module (SCI)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

18.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

18.5.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .245

18.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

18.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

18.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .247

18.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .247

18.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

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18.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

18.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .248

18.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

18.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

18.5.3.5 Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .252

18.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

18.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

18.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

18.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .258

18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

18.8.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .258

18.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .258

18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

18.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .259

18.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .262

18.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .265

18.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

18.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

18.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

18.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .274

Section 19. System Integration Module (SIM)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278

19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .281

19.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

19.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . .281

19.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .282

19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .282

19.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

19.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .284

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19.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

19.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .286

19.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .286

19.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .286

19.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .287

19.4.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . .287

19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

19.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .287

19.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .288

19.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .288

19.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

19.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

19.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .291

19.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

19.6.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . .292

19.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

19.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

19.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .295

19.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

19.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .298

19.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . 300

19.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .301

Section 20. Serial Peripheral Interface Module (SPI)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

20.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

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20.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308

20.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

20.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .309

20.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .310

20.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .312

20.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .313

20.7 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .315

20.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

20.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

20.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .324

20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

20.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .325

20.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .325

20.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

20.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

20.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .327

20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

20.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

20.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .330

20.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

Section 21. Timebase Module (TBM)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

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21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

21.5 Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . .337

21.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338

21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

21.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

21.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

Section 22. Timer Interface Module (TIM)

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

22.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

22.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .348

22.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .349

22.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .349

22.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .350

22.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .351

22.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

22.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

22.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

22.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .354

22.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

22.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 356

22.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

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22.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .359

22.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .360

22.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .363

Section 23. Electrical Specifications

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .366

23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .367

23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .368

23.7 3.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .370

23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372

23.9 3.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

23.10 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .374

23.11 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . .377

23.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

23.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

23.14 5.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

23.15 3.0-V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .384

23.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .387

23.17 Clock Generation Module Characteristics . . . . . . . . . . . . . . .387

23.17.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . .387

23.17.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . .388

23.18 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

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MOTOROLA Table of Contents 21

Section 24. Mechanical Specifications

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391

24.3 40-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .392

24.4 42-Pin Shrink Dual in-Line Package (SDIP) . . . . . . . . . . . . . .392

24.5 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .393

Section 25. Ordering Information

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

Appendix A. MC68HC08GP32

A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

A.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400

A.5 Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401

A.6 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

A.7 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402

A.8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

A.8.1 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .403

A.8.2 5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . .403

A.8.3 3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . .404

A.8.4 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .405

A.9 ROM MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . .406

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA List of Figures 23

Technical Data – MC68HC908GP32•MC68HC08GP32

List of Figures

Figure Title Page

1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

1-2 40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .37

1-3 42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .38

1-4 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .39

1-5 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .47

4-1 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4-2 Power-On Reset Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4-3 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .74

4-4 Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4-5 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .77

4-6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4-7 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .85

4-8 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .85

4-9 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .86

5-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

5-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . . .93

5-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

5-4 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . .95

6-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .99

6-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

6-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .101

6-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .102

6-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . 102

6-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .103

6-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .104

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List of Figures

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

24 List of Figures MOTOROLA

Figure Title Page

7-1 CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

7-2 CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . .119

7-3 CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 122

7-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .123

7-5 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .126

7-6 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .127

7-7 PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . .128

7-8 PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . .129

7-9 PLL Reference Divider Select Register (PMDS) . . . . . . . . . .130

7-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

8-1 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .138

8-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .138

9-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

9-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .145

10-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . 152

11-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . .166

11-2 FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . .171

11-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . .172

11-4 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . .172

12-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .177

12-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .177

12-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .180

13-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .183

13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

13-3 Keyboard Status and Control Register (INTKBSCR) . . . . . . . 187

13-4 Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . .188

14-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .191

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List of Figures

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA List of Figures 25

Figure Title Page

14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .191

14-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . . 193

15-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

15-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .201

15-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-4 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15-6 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15-7 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .208

15-8 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .209

16-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .212

16-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .215

16-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .216

16-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

16-5 Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . .218

16-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .219

16-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .220

16-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

16-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .222

16-10 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .223

16-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

16-12 Port C Input Pullup Enable Register (PTCPUE). . . . . . . . . . .225

16-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .226

16-14 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .228

16-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-16 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . . . .230

16-17 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .231

16-18 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .232

16-19 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

18-1 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .241

18-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .242

18-3 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

18-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .249

18-6 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

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List of Figures

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

26 List of Figures MOTOROLA

Figure Title Page

18-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

18-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

18-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .260

18-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .263

18-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .265

18-12 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .268

18-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

18-14 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .272

18-15 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .273

18-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .274

19-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

19-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .280

19-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

19-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

19-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

19-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

19-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .291

19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .293

19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .293

19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .294

19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

19-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .296

19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .296

19-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .298

19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .298

19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .300

19-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .301

20-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .306

20-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .307

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Figure Title Page

20-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .311

20-5 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

20-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .312

20-7 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . .314

20-8 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . .315

20-9 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .317

20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .318

20-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .321

20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .328

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I

20-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .330

20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .333

List of Figures

cale Semiconductor,

Frees

21-1 Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

21-2 Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . .337

22-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344

22-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .345

22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .350

22-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .356

22-5 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . .358

22-6 TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . .358

22-7 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .359

22-8 TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . .359

22-9 TIM Channel 0 Status and Control Register (TSC0) . . . . . . .360

22-10 TIM Channel 1 Status and Control Register (TSC1) . . . . . . .360

22-11 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

22-12 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . .364

22-13 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . .364

22-14 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . .364

22-15 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . .364

23-1 Typical High-Side Driver Characteristics –

23-2 Typical High-Side Driver Characteristics –

23-3 Typical High-Side Driver Characteristics –

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA List of Figures 27

For More Information On This Product,

Port PTA7–PTA0 (V

Port PTA7–PTA0 (V

Port PTC4–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . .375

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= 4.5 Vdc). . . . . . . . . . . . . . . . . . .374

DD

= 2.7 Vdc). . . . . . . . . . . . . . . . . . .374

DD

List of Figures

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

28 List of Figures MOTOROLA

Figure Title Page

23-4 Typical High-Side Driver Characteristics –

Port PTC4–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . .375

23-5 Typical High-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . .376

23-6 Typical High-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . .376

23-7 Typical Low-Side Driver Characteristics –

Port PTA7–PTA0 (VDD = 5.5 Vdc). . . . . . . . . . . . . . . . . . .377

23-8 Typical Low-Side Driver Characteristics –

Port PTA7–PTA0 (VDD = 2.7 Vdc). . . . . . . . . . . . . . . . . . .377

23-9 Typical Low-Side Driver Characteristics –

Port PTC4–PTC0 (VDD = 4.5 Vdc) . . . . . . . . . . . . . . . . . .378

23-10 Typical Low-Side Driver Characteristics –

Port PTC4–PTC0 (VDD = 2.7 Vdc) . . . . . . . . . . . . . . . . . .378

23-11 Typical Low-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) . . . . . . . .379

23-12 Typical Low-Side Driver Characteristics –

Ports PTB7–PTB0, PTC6–PTC5,

PTD7–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . .379

23-13 Typical Operating IDD,

with All Modules Turned On (–40 °C to 85 °C) . . . . . . . . .380

23-14 Typical Wait Mode IDD,

with all Modules Disabled (–40 °C to 85 °C) . . . . . . . . . . .380

23-15 Typical Stop Mode IDD,

with all Modules Disabled (–40 °C to 85 °C) . . . . . . . . . . .381

23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

23-17 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386

A-1 MC68HC08GP32 Block Diagram . . . . . . . . . . . . . . . . . . . . . .399

A-2 MC68HC08GP32 Memory Map . . . . . . . . . . . . . . . . . . . . . . .400

A-3 Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . .402

A-4 Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . .402

A-5 Typical Operating I

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404

A-6 Typical Wait Mode IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

A-7 Typical Stop Mode I

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA List of Tables 29

Technical Data – MC68HC908GP32

List of Tables

Table Title Page

2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4-1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4-2 Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

5-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7-1 Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

7-3 VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .125

7-2 PRE1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . .125

10-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

10-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

14-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

15-1 Monitor Mode Signal Requirements and Options. . . . . . . . . .199

15-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .203

15-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .205

15-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 205

15-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .206

15-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .206

15-8 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .207

15-9 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .207

16-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .214

16-2 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

16-3 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

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List of Tables

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

30 List of Tables MOTOROLA

Table Title Page

16-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

16-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-6 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

18-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

18-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

18-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

18-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

18-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .262

18-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .274

18-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

18-8 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .276

19-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .279

19-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

19-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

19-4 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

20-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

20-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

20-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

20-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .333

21-1 Timebase Rate Selection for OSC1 = 32.768-kHz. . . . . . . . .337

22-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

22-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

22-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .362

25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

A-1 Summary of MC68HC08GP32 and MC68HC908GP32

differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

A-2 ROM MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . .406

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 31

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 1. General Description

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

1.3.1 Standard Features of the MC68HC908GP32. . . . . . . . . . . .32

1.3.2 Features of the CPU08. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

1.6.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . .39

1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .40

1.6.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . .40

1.6.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . .40

1.6.5 CGM Power Supply Pins (V

DDA

and V

SSA

) . . . . . . . . . . . . .41

1.6.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .41

1.6.7 ADC Power Supply/Reference Pins

(V

DDAD/VREFH

and V

SSAD/VREFL

) . . . . . . . . . . . . . . . . . .41

1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7

–PTA0/KBD0) .41

1.6.9 Port B I/O Pins (PTB7/AD7–PTB0/AD0) . . . . . . . . . . . . . . .41

1.6.10 Port C I/O Pins (PTC6–PTC0) . . . . . . . . . . . . . . . . . . . . . . .42

1.6.11 Port D I/O Pins (PTD7/T2CH1–PTD0/SS) . . . . . . . . . . . . . .42

1.6.12 Port E I/O Pins (PTE1/RxD–PTE0/TxD). . . . . . . . . . . . . . . .42

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General Description

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

32 General Description MOTOROLA

1.2 Introduction

The MC68HC908GP32 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.

1.3 Features

For convenience, features have been organized to reflect:

• Standard features of the MC68HC908GP32

• Features of the CPU08

1.3.1 Standard Features of the MC68HC908GP32

• High-performance M68HC08 architecture optimized for
C-compilers

• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families

• 8-MHz internal bus frequency

• FLASH program memory security

1

• On-chip programming firmware for use with host personal
computer which does not require high voltage for entry

• In-system programming

• System protection features:

– Optional computer operating properly (COP) reset

– Low-voltage detection with optional reset and selectable trip

points for 3.0-V and 5.0-V operation

– Illegal opcode detection with reset

– Illegal address detection with reset

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.

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General Description

Features

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 33

• Low-power design; fully static with stop and wait modes

• Standard low-power modes of operation:

– Wait mode

– Stop mode

• Master reset pin and power-on reset (POR)

• 32 Kbytes of on-chip FLASH memory with in-circuit programming
capabilities of FLASH program memory

• 512 bytes of on-chip random-access memory (RAM)

• Serial peripheral interface module (SPI)

• Serial communications interface module (SCI)

• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2)
with selectable input capture, output compare, and PWM
capability on each channel

• 8-channel, 8-bit successive approximation analog-to-digital
converter (ADC)

• BREAK module (BRK) to allow single breakpoint setting during
in-circuit debugging

• Internal pullups on IRQ and RST to reduce customer system cost

• Clock generator module with on-chip 32-kHz crystal compatible
PLL (phase-lock loop)

• Up to 33 general-purpose input/output (I/O) pins, including:

– 26 shared-function I/O pins

– Five or seven dedicated I/O pins, depending on package

choice

• Selectable pullups on inputs only on ports A, C, and D. Selection
is on an individual port bit basis. During output mode, pullups are
disengaged.

• High current 10-mA sink/10-mA source capability on all port pins

• Higher current 15-mA sink/source capability on PTC0–PTC4

• Timebase module with clock prescaler circuitry for eight user
selectable periodic real-time interrupts with optional active clock
source during stop mode for periodic wakeup from stop using an
external 32-kHz crystal

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General Description

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

34 General Description MOTOROLA

• Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG
register to allow user selection of having the oscillator enabled or
disabled during stop mode

• 8-bit keyboard wakeup port

• 5-mA maximum current injection on all port pins to maintain input
protection

• 40-pin plastic dual-in-line package (PDIP), 42-pin shrink dual-in­line package (SDIP), or 44-pin quad flat pack (QFP)

• Specific features of the MC68HC908GP32 in 40-pin PDIP are:

– Port C is only 5 bits: PTC0–PTC4

– Port D is only 6 bits: PTD0–PTD5; single 2-channel TIM

module

• Specific features of the MC68HC908GP32 in 42-pin SDIP are:

– Port C is only 5 bits: PTC0–PTC4

– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules

• Specific features of the MC68HC908GP32 in 44-pin QFP are:

– Port C is 7 bits: PTC0–PTC6

– Port D is 8 bits: PTD0–PTD7; dual 2-channel TIM modules

1.3.2 Features of the CPU08

Features of the CPU08 include:

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (eight more than the HC05)

• 16-bit index register and stack pointer

• Memory-to-memory data transfers

•Fast 8 × 8 multiply instruction

• Fast 16/8 divide instruction

• Binary-coded decimal (BCD) instructions

• Optimization for controller applications

• Efficient C language support

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General Description

MCU Block Diagram

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 35

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908GP32. Text in

parentheses within a module block indicates the module name. Text in
parentheses next to a signal indicates the module which uses the signal.

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General Description

PTB7/AD7

PTA7/KBD7–PTA0/KBD0 †

PORTA

DDRA

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I

PTB6/AD6

PTB5/AD5

PTB4/AD4

PTB3/AD3

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PTB2/AD2

PTB1/AD1

PTB0/AD0

PTC6 †

PORTB

DDRB

†

PTE1/RxD

PTD7/T2CH1 †

PTD6/T2CH0 †

PTD5/T1CH1 †

PTD4/T1CH0 †

PTD3/SPSCK †

PTD2/MOSI †

PTD1/MISO †

PTC5 †

PTC4 † ‡

PTC3 † ‡

PTC2 † ‡

PTC1 † ‡

PTC0 † ‡

PORTC

DDRC

DDRD

PTD0/SS

PORTD

PTE0/TxD

DDRE

MODULE

SECURITY

PORTE

MODULE

MONITOR MODE ENTRY

cale Semiconductor,

Frees

INTERNAL BUS

MODULE

PROGRAMMABLE TIMEBASE

ARITHMETIC/LOGIC

M68HC08 CPU

CPU

MODULE

DUAL VOLTAGE

SINGLE BREAKPOINT BREAK

UNIT (ALU)

REGISTERS

CONTROL AND STATUS REGISTERS — 64 BYTES

8-BIT KEYBOARD

INTERRUPT MODULE

LOW-VOLTAGE INHIBIT MODULE

USER RAM — 512 BYTES

USER FLASH — 32,256 BYTES

MODULE 1

2-CHANNEL TIMER INTERFACE

MONITOR ROM — 307 BYTES

MODULE 2

PROPERLY MODULE

INTERFACE MODULE

COMPUTER OPERATING

PHASE-LOCKED LOOP

CGMXFC

OSC1

SERIAL COMMUNICATIONS

32-kHz OSCILLATOR

OSC2

2-CHANNEL TIMER INTERFACE

CLOCK GENERATOR MODULE

USER FLASH VECTOR SPACE — 36 BY TES

SERIAL PERIPHERAL

MODULE

24 INTR SYSTEM INTEGRATION

* RST

MONITOR MODULE

INTERFACE MODULE

MODULE

SINGLE EXTERNAL IRQ

* IRQ

MODULE

DATA BUS SWITCH

CONVERTER MODULE

8-BIT ANALOG-TO-DIGITAL

REFL

REFH

/V

/V

SSAD

DDAD

V

V

POWER-ON RESET

MODULE

MEMORY MAP

MODULE

MODULE

CONFIGURATION REGISTER 1

POWER

SS

DD

DDA

V

V

V

V

SSA

MODULE

CONFIGURATION REGISTER 2

Figure 1-1. MCU Block Diagram

Technical Data MC68HC908GP32•MC68HC08GP32

36 General Description MOTOROLA

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† Ports are software configurable with pullup device if input port.

‡ Higher current drive port pins

* Pin contains integrated pullup device

—

Rev. 6

General Description

Pin Assignments

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 37

1.5 Pin Assignments

Figure 1-2. 40-Pin PDIP Pin Assignments

PTB1/AD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PTB0/AD0

PTD5/T1CH1

PTD4/T1CH0

V

DD

V

SS

PTD3/SPSCK

PTD2/MOSI

RST

IRQ

PTD0/SS

PTD1/MISO

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

PTA5/KBD5

PTA6/KBD6

PTA7/KBD7

PTB6/AD6

PTB7/AD7

PTB3/AD3

PTB4/AD4

PTB5/AD5

V

SSA

(PLL)

V

DDA

(PLL)

V

DDAD/VREFH

(ADC)

V

SSAD/VREFL

(ADC)

CGMXFC (PLL)

OSC2

OSC1

PTC0

PTC1

PTC2

PTC3

PTC4

PTE0/TxD

PTE1/RxD

PTB2/AD2

Pins not available on 40-pin package Internal connection

PTC5 Connected to ground

PTC6 Connected to ground

PTD6/T2CH0 Unconnected

PTD7/T2CH1 Unconnected

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General Description

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

38 General Description MOTOROLA

Figure 1-3. 42-Pin SDIP Pin Assignments

21 22

PTD5/T1CH1

PTD4/T1CH0

PTB1/AD1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

PTB0/AD0

PTD7/T2CH1

V

SS

PTD3/SPSCK

PTD2/MOSI

RST

IRQ

PTD0/SS

PTD1/MISO

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

PTA3/KBD3

PTA4/KBD4

PTA5/KBD5

PTA6/KBD6

PTA7/KBD7

PTB6/AD6

PTB7/AD7

PTB3/AD3

PTB4/AD4

PTB5/AD5

V

SSA

(PLL)

V

DDA

(PLL)

V

DDAD/VREFH

(ADC)

V

SSAD/VREFL

(ADC)

CGMXFC (PLL)

OSC2

OSC1

PTC0

PTC1

PTC2

PTC3

PTC4

PTE0/TxD

PTE1/RxD

PTB2/AD2

20 23

PTD6/T2CH0

V

DD

Pins not available on 42-pin package Internal connection

PTC5 Connected to ground

PTC6 Connected to ground

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General Description

Pin Functions

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 39

Figure 1-4. 44-Pin QFP Pin Assignments

1.6 Pin Functions

Descriptions of the pin functions are provided here.

1.6.1 Power Supply Pins (V

DD

and VSS)

V

DD

and VSS are the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the C1 bypass capacitor as close to the MCU as possible.

44

34

43

42

41

40

39

38

37

36

35

1

2

3

4

5

6

7

8

9

10

11

13

14

15

16

17

18

19

20

21

22

33

32

31

30

29

28

27

26

25

24

12

23

RST

PTE0/TxD

PTE1/RxD

IRQ

PTC0

PTC1

PTC2

PTC3

PTC4

PTC5

PTC6

PTD5/T1CH1

PTD4/T1CH0

V

DD

V

SS

PTD3/SPSCK

PTD2/MOSI

PTD1/MISO

PTD0/SS

PTD6/T2CH0

PTD7/T2CH1

PTB0/AD0

PTB6/AD6

PTB7/AD7

V

DDAD/VREFH

V

SSAD/VREFL

PTA0/KBD0

PTB2/AD2

PTB3/AD3

PTB1/AD1

PTB4/AD4

PTB5/AD5

PTA4/KBD4

PTA5/KBD5

V

DDA

OSC1

OSC2

CGMXFC

V

SSA

PTA1/KBD1

PTA6/KBD6

PTA7/KBD7

PTA3/KBD3

PTA2/KBD2

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General Description

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

40 General Description MOTOROLA

Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.

Figure 1-5. Power Supply Bypassing

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 7. Clock Generator Module (CGMC).

1.6.3 External Reset Pin (RST)

A logic 0 on the RST

pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor. See Section 19. System Integration Module (SIM).

1.6.4 External Interrupt Pin (IRQ

)

IRQ is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor. See Section 12. External Interrupt (IRQ).

MCU

V

DD

C2

C1

0.1

µF

V

SS

V

DD

+

NOTE: Component values shown

represent typical applications.

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General Description

Pin Functions

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA General Description 41

1.6.5 CGM Power Supply Pins (V

DDA

and V

SSA

)

V

DDA

and V

SSA

are the power supply pins for the analog portion of the

clock generator module (CGM). Connect the V

DDA

pin to the same

voltage potential as VDD, and the V

SSA

pin to the same voltage potential

as VSS. Decoupling of these pins should be as per the digital supply. See

Section 7. Clock Generator Module (CGMC).

1.6.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Section 7. Clock Generator Module (CGMC).

1.6.7 ADC Power Supply/Reference Pins (V

DDAD/VREFH

and V

SSAD/VREFL

)

V

DDAD

and V

SSAD

are the power supply pins for the analog-to-digital

converter (ADC). Connect the V

DDAD

pin to the same voltage potential

as VDD, and the V

SSAD

pin to the same voltage potential as VSS.

Decoupling of these pins should be as per the digital supply. See

Section 5. Analog-to-Digital Converter (ADC).

V

REFH

is the high reference supply for the ADC, and is internally

connected to V

DDAD

.

V

REFL

is the low reference supply for the ADC, and is internally

connected to V

SSAD

.

1.6.8 Port A Input/Output (I/O) Pins (PTA7/KBD7—PTA0/KBD0)

PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all
of the port A pins can be programmed to serve as keyboard interrupt
pins. See Section 16. Input/Output (I/O) Ports and Section 13.

Keyboard Interrupt Module (KBI).

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

1.6.9 Port B I/O Pins (PTB7/AD7—PTB0/AD0)

PTB7–PTB0 are general-purpose, bidirectional I/O port pins that can
also be used for analog-to-digital converter (ADC) inputs. See Section

16. Input/Output (I/O) Ports and Section 5. Analog-to-Digital
Converter (ADC).

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General Description

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

42 General Description MOTOROLA

1.6.10 Port C I/O Pins (PTC6—PTC0)

PTC6–PTC0 are general-purpose, bidirectional I/O port pins. See

Section 16. Input/Output (I/O) Ports. PTC5 and PTC6 are only

available on 44-pin QFP package.

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

1.6.11 Port D I/O Pins (PTD7/T2CH1—PTD0/SS)

PTD7–PTD0 are special-function, bidirectional I/O port pins.
PTD0–PTD3 can be programmed to be serial peripheral interface (SPI)
pins, while PTD4–PTD7 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See Section 22. Timer

Interface Module (TIM), Section 20. Serial Peripheral Interface
Module (SPI), and Section 16. Input/Output (I/O) Ports. PTD6 and

PTD7 are only available on 42-SDIP and 44-pin QFP packages.

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

1.6.12 Port E I/O Pins (PTE1/RxD—PTE0/TxD)

PTE0–PTE1 are general-purpose, bidirectional I/O port pins. These pins
can also be programmed to be serial communications interface (SCI)
pins. See Section 18. Serial Communications Interface Module (SCI)
and Section 16. Input/Output (I/O) Ports.

NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic

level (either V

DD

or VSS). Although the I/O ports of the
MC68HC908GP32 do not require termination, termination is
recommended to reduce the possibility of static damage.

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 43

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 2. Memory Map

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .43

2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.2 Introduction

The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:

• 32,256 bytes of user FLASH memory

• 512 bytes of random-access memory (RAM)

• 36 bytes of user-defined vectors

• 307 bytes of monitor ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address
reset. In the memory map (Figure 2-1) and in register figures in this
document, unimplemented locations are shaded.

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Memory Map

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

44 Memory Map MOTOROLA

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area
of $0000–$003F. Additional I/O registers have these addresses:

• $FE00; SIM break status register, SBSR

• $FE01; SIM reset status register, SRSR

• $FE02; reserved, SUBAR

• $FE03; SIM break flag control register, SBFCR

• $FE04; interrupt status register 1, INT1

• $FE05; interrupt status register 2, INT2

• $FE06; interrupt status register 3, INT3

•$FE07; reserved

• $FE08; FLASH control register, FLCR

• $FE09; break address register high, BRKH

• $FE0A; break address register low, BRKL

• $FE0B; break status and control register, BRKSCR

• $FE0C; LVI status register, LVISR

• $FF7E; FLASH block protect register, FLBPR

• $FFFF; COP control register, COPCTL

Data registers are shown in Figure 2-2. Table 2-1 is a list of vector
locations.

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Memory Map

Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 45

$0000

I/O Registers

64 Bytes

↓

$003F

$0040

RAM

512 Bytes

↓

$023F

$0240

Unimplemented

32,192 Bytes

↓

$7FFF

$8000

FLASH Memory

32,256 Bytes

↓

$FDFF

$FE00 SIM Break Status Register (SBSR)

$FE01 SIM Reset Status Register (SRSR)

$FE02 Reserved (SUBAR)

$FE03 SIM Break Flag Control Register (SBFCR)

$FE04 Interrupt Status Register 1 (INT1)

$FE05 Interrupt Status Register 2 (INT2)

$FE06 Interrupt Status Register 3 (INT3)

$FE07 Reserved

$FE08 FLASH Control Register (FLCR)

$FE09 Break Address Register High (BRKH)

$FE0A Break Address Register Low (BRKL)

$FE0B Break Status and Control Register (BRKSCR)

$FE0C LVI Status Register (LVISR)

$FE0D

Unimplemented

3 Bytes

↓

$FE0F

Figure 2-1. Memory Map

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Memory Map

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

46 Memory Map MOTOROLA

$FE10

Unimplemented

16 Bytes

Reserved for Compatibility with Monitor Code

for A-Family Parts

↓

$FE1F

$FE20

Monitor ROM

307 Bytes

↓

$FF52

$FF53

Unimplemented

43 Bytes

↓

$FF7D

$FF7E FLASH Block Protect Register (FLBPR)

$FF7F

Unimplemented

93 Bytes

↓

$FFDB

Note: $FFF6–$FFFD

reserved for

8 security bytes

$FFDC

FLASH Vectors

36 Bytes

↓

$FFFF

Figure 2-1. Memory Map (Continued)

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Memory Map

Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 47

Addr.Register Name Bit 7654321Bit 0

$0000

Port A Data Register

(PTA)

Read:

PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

Write:

Reset: Unaffected by reset

$0001

Port B Data Register

(PTB)

Read:

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

Write:

Reset: Unaffected by reset

$0002

Port C Data Register

(PTC)

Read: 0

PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

Write:

Reset: Unaffected by reset

$0003

Port D Data Register

(PTD)

Read:

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

Write:

Reset: Unaffected by reset

$0004

Data Direction Register A

(DDRA)

Read:

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

Write:

Reset:00000000

$0005

Data Direction Register B

(DDRB)

Read:

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

Write:

Reset:00000000

$0006

Data Direction Register C

(DDRC)

Read: 0

DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

Write:

Reset:00000000

$0007

Data Direction Register D

(DDRD)

Read:

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

Write:

Reset:00000000

$0008

Port E Data Register

(PTE)

Read: 000000

PTE1 PTE0

Write:

Reset: Unaffected by reset

$0009 Unimplemented

Read:

Write:

Reset:00000000

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

48 Memory Map MOTOROLA

$000A Unimplemented

Read:

Write:

Reset:00000000

$000B Unimplemented

Read:

Write:

Reset:00000000

$000C

Data Direction Register E

(DDRE)

Read: 000000

DDRE1 DDRE0

Write:

Reset:00000000

$000D

Port A Input Pullup Enable

Register

(PTAPUE)

Read:

PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:00000000

$000E

Port C Input Pullup Enable

Register

(PTCPUE)

Read: 0

PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0

Write:

Reset:00000000

$000F

Port D Input Pullup Enable

Register

(PTDPUE)

Read:

PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Write:

Reset:00000000

$0010

SPI Control Register

(SPCR)

Read:

SPRIE

DMAS

SPMSTR CPOL CPHA SPWOM SPE SPTIE

Write:

Reset:00101000

$0011

SPI Status and Control

Register

(SPSCR)

Read: SPRF

ERRIE

OVRF MODF SPTE

MODFEN SPR1 SPR0

Write:

Reset:00001000

$0012

SPI Data Register

(SPDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

$0013

SCI Control Register 1

(SCC1)

Read:

LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

Write:

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 49

$0014

SCI Control Register 2

(SCC2)

Read:

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

Write:

Reset:00000000

$0015

SCI Control Register 3

(SCC3)

Read: R8

T8 DMARE DMATE ORIE NEIE FEIE PEIE

Write:

Reset:UU000000

$0016

SCI Status Register 1

(SCS1)

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

$0017

SCI Status Register 2

(SCS2)

Read:

BKF RPF

Write:

Reset:00000000

$0018

SCI Data Register

(SCDR)

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

$0019

SCI Baud Rate Register

(SCBR)

Read:

SCP1 SCP0 R SCR2 SCR1 SCR0

Write:

Reset:00000000

$001A

Keyboard Status

and Control Register

(INTKBSCR)

Read: 0000KEYF0

IMASKK MODEK

Write:

ACKK

Reset:00000000

$001B

Keyboard Interrupt Enable

Register

(INTKBIER)

Read:

KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

Write:

Reset:00000000

$001C

Time Base Module Control

Register

(TBCR)

Read: TBIF

TBR2 TBR1 TBR0

0

TBIE TBON R

Write:

TACK

Reset:00000000

$001D

IRQ Status and Control

Register

(INTSCR)

Read: 0000IRQF0

IMASK MODE

Write:

ACK

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

50 Memory Map MOTOROLA

$001E

Configuration Register 2

(CONFIG2)†

Read: 000000

OSC-

STOPENB

SCIBD-

SRC

Write:

Reset:00000000

$001F

Configuration Register 1

(CONFIG1)

†

Read:

COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3

†

SSREC STOP COPD

Write:

Reset:00000000

$0020

Timer 1 Status and Control

Register

(T1SC)

Read: TOF

TOIE TSTOP

00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$0021

Timer 1 Counter

Register High

(T1CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$0022

Timer 1 Counter

Register Low

(T1CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$0023

Timer 1 Counter Modulo

Register High

(T1MODH)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$0024

Timer 1 Counter Modulo

Register Low

(T1MODL)

Read:

Bit 7654321Bit 0

Write:

Reset:11111111

$0025

Timer 1 Channel 0 Status

and Control Register

(T1SC0)

Read: CH0F

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0026

Timer 1 Channel 0

Register High

(T1CH0H)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$0027

Timer 1 Channel 0

Register Low

(T1CH0L)

Read:

Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 51

$0028

Timer 1 Channel 1 Status

and Control Register

(T1SC1)

Read: CH1F

CH1IE

0

MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset:00000000

$0029

Timer 1 Channel 1

Register High

(T1CH1H)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$002A

Timer 1 Channel 1

Register Low

(T1CH1L)

Read:

Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$002B

Timer 2 Status and Control

Register

(T2SC)

Read: TOF

TOIE TSTOP

00

PS2 PS1 PS0

Write: 0 TRST

Reset:00100000

$002C

Timer 2 Counter

Register High

(T2CNTH)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$002D

Timer 2 Counter

Register Low

(T2CNTL)

Read: Bit 7 654321Bit 0

Write:

Reset:00000000

$002E

Timer 2 Counter Modulo

Register High

(T2MODH)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:11111111

$002F

Timer 2 Counter Modulo

Register Low

(T2MODL)

Read:

Bit 7654321Bit 0

Write:

Reset:11111111

$0030

Timer 2 Channel 0 Status

and Control Register

(T2SC0)

Read: CH0F

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset:00000000

$0031

Timer 2 Channel 0

Register High

(T2CH0H)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

52 Memory Map MOTOROLA

$0032

Timer 2 Channel 0

Register Low

(T2CH0L)

Read:

Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$0033

Timer 2 Channel 1 Status

and Control Register

(T2SC1)

Read: CH1F

CH1IE

0

MS1A ELS1B ELS1A TOV1 CH1MAX

Write: 0

Reset:00000000

$0034

Timer 2 Channel 1

Register High

(T2CH1H)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

$0035

Timer 2 Channel 1

Register Low

(T2CH1L)

Read:

Bit 7654321Bit 0

Write:

Reset: Indeterminate after reset

$0036

PLL Control Register

(PCTL)

Read:

PLLIE

PLLF

PLLON BCS PRE1 PRE0 VPR1 VPR0

Write:

Reset:00100000

$0037

PLL Bandwidth Control

Register

(PBWC)

Read:

AUTO

LOCK

ACQ

0000

R

Write:

Reset:00000000

$0038

PLL Multiplier Select High

Register

(PMSH)

Read: 0000

MUL11 MUL10 MUL9 MUL8

Write:

Reset:00000000

$0039

PLL Multiplier Select Low

Register

(PMSL)

Read:

MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0

Write:

Reset:01000000

$003A

PLL VCO Range Select

Register

(PMRS)

Read:

VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0

Write:

Reset:01000000

$003B

PLL Reference Divider

Select Register

(PMDS)

Read: 0000

RDS3 RDS2 RDS1 RDS0

Write:

Reset:00000001

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)

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Memory Map

Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 53

$003C

Analog-to-Digital Status

and Control Register

(ADSCR)

Read:

COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

Write:

Reset:00011111

$003D

Analog-to-Digital Data

Register

(ADR)

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:

Reset:00000000

$003E

Analog-to-Digital Clock

Register

(ADCLK)

Read:

ADIV2 ADIV1 ADIV0 ADICLK

0000

Write:

Reset:00000000

$003F Unimplemented

Read:

Write:

Reset:

$FE00

SIM Break Status Register

(SBSR)

Read:

RRRRRR

SBSW

R

Write: Note

Reset: 0

Note: Writing a logic 0 clears SBSW.

$FE01

SIM Reset Status Register

(SRSR)

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

$FE02

SIM Upper Byte Address

Register

(SUBAR)

Read:

RRRRRRRR

Write:

Reset:

$FE03

SIM Break Flag Control

Register

(SBFCR)

Read:

BCFERRRRRRR

Write:

Reset: 0

$FE04

Interrupt Status Register 1

(INT1)

Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0

Write:RRRRRRRR

Reset:00000000

$FE05

Interrupt Status Register 2

(INT2)

Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7

Write:RRRRRRRR

Reset:00000000

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

54 Memory Map MOTOROLA

$FE06

Interrupt Status Register 3

(INT3)

Read: 000000IF16IF15

Write:RRRRRRRR

Reset:00000000

$FE07 Reserved

Read:

RRRRRRRR

Write:

Reset:00000000

$FE08

FLASH Control Register

(FLCR)

Read: 0000

HVEN MASS ERASE PGM

Write:

Reset:00000000

$FE09

Break Address

Register High

(BRKH)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:00000000

$FE0A

Break Address

Register Low

(BRKL)

Read:

Bit 7654321Bit 0

Write:

Reset:00000000

$FE0B

Break Status and Control

Register

(BRKSCR)

Read:

BRKE BRKA

000000

Write:

Reset:00000000

$FE0C

LVI Status Register

(LVISR)

Read: LVIOUT 0000000

Write:

Reset:00000000

$FF7E

FLASH Block Protect

Register

(FLBPR)

†

Read:

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:

Reset:UUUUUUUU

$FFFF

COP Control Register

(COPCTL)

Read: Low byte of reset vector

Write: Writing clears COP counter (any value)

Reset: Unaffected by reset

† Non-volatile FLASH register

Addr.Register Name Bit 7654321Bit 0

= Unimplemented R = Reserved U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)

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Input/Output (I/O) Section

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Memory Map 55

.

Table 2-1. Vector Addresses

Vector Priority Vector Address Vector

Lowest

IF16

$FFDC Timebase Vector (High)

$FFDD Timebase Vector (Low)

IF15

$FFDE ADC Conversion Complete Vector (High)

$FFDF ADC Conversion Complete Vector (Low)

IF14

$FFE0 Keyboard Vector (High)

$FFE1 Keyboard Vector (Low)

IF13

$FFE2 SCI Transmit Vector (High)

$FFE3 SCI Transmit Vector (Low)

IF12

$FFE4 SCI Receive Vector (High)

$FFE5 SCI Receive Vector (Low)

IF11

$FFE6 SCI Error Vector (High)

$FFE7 SCI Error Vector (Low)

IF10

$FFE8 SPI Transmit Vector (High)

$FFE9 SPI Transmit Vector (Low)

IF9

$FFEA SPI Receive Vector (High)

$FFEB SPI Receive Vector (Low)

IF8

$FFEC TIM2 Overflow Vector (High)

$FFED TIM2 Overflow Vector (Low)

IF7

$FFEE TIM2 Channel 1 Vector (High)

$FFEF TIM2 Channel 1 Vector (Low)

IF6

$FFF0 TIM2 Channel 0 Vector (High)

$FFF1 TIM2 Channel 0 Vector (Low)

IF5

$FFF2 TIM1 Overflow Vector (High)

$FFF3 TIM1 Overflow Vector (Low)

IF4

$FFF4 TIM1 Channel 1 Vector (High)

$FFF5 TIM1 Channel 1 Vector (Low)

IF3

$FFF6 TIM1 Channel 0 Vector (High)

$FFF7 TIM1 Channel 0 Vector (Low)

IF2

$FFF8 PLL Vector (High)

$FFF9 PLL Vector (Low)

IF1

$FFFA IRQ

Vector (High)

$FFFB IRQ Vector (Low)

—

$FFFC SWI Vector (High)

$FFFD SWI Vector (Low)

—

$FFFE Reset Vector (High)

Highest $FFFF Reset Vector (Low)

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56 Memory Map MOTOROLA

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 57

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 3. Low-Power Modes

3.1 Contents

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . .59

3.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3.4.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . . .60

3.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

3.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7 Computer Operating Properly Module (COP). . . . . . . . . . . . . .61

3.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

3.8 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . .62

3.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . .62

3.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

3.10 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . .63

3.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

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3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11 Serial Communications Interface Module (SCI) . . . . . . . . . . . .63

3.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . .64

3.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . .64

3.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

3.14 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.15 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

3.16 Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.2 Introduction

The MCU may enter two low-power modes: wait mode and stop mode.
They are common to all HC08 MCUs and are entered through instruction
execution. This section describes how each module acts in the low­power modes.

3.2.1 Wait Mode

The WAIT instruction puts the MCU in a low-power standby mode in
which the CPU clock is disabled but the bus clock continues to run.
Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See

Section 8. Configuration Register (CONFIG).)

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Low-Power Modes

Analog-to-Digital Converter (ADC)

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 59

3.2.2 Stop Mode

Stop mode is entered when a STOP instruction is executed. The CPU
clock is disabled and the bus clock is disabled if the OSCSTOPENB bit
in the CONFIG register is at a logic 0. (See Section 8. Configuration

Register (CONFIG).)

3.3 Analog-to-Digital Converter (ADC)

3.3.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.

3.3.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.

3.4 Break Module (BRK)

3.4.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if the
SBSW bit in the break status register is set.

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60 Low-Power Modes MOTOROLA

3.4.2 Stop Mode

The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the SBSW bit in the break status register. The
STOP instruction does not affect break module register states.

3.5 Central Processor Unit (CPU)

3.5.1 Wait Mode

The WAIT instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

3.5.2 Stop Mode

The STOP instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.

3.6 Clock Generator Module (CGM)

3.6.1 Wait Mode

The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive

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Low-Power Modes

Computer Operating Properly Module (COP)

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 61

applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.

3.6.2 Stop Mode

If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.

If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.

3.7 Computer Operating Properly Module (COP)

3.7.1 Wait Mode

The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.

3.7.2 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

62 Low-Power Modes MOTOROLA

The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.

3.8 External Interrupt Module (IRQ)

3.8.1 Wait Mode

The IRQ module remains active in wait mode. Clearing the IMASK bit in
the IRQ status and control register enables IRQ CPU interrupt requests
to bring the MCU out of wait mode.

3.8.2 Stop Mode

The IRQ module remains active in stop mode. Clearing the IMASK bit in
the IRQ status and control register enables IRQ CPU interrupt requests
to bring the MCU out of stop mode.

3.9 Keyboard Interrupt Module (KBI)

3.9.1 Wait Mode

The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.

3.9.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.

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Low-Power Modes

Low-Voltage Inhibit Module (LVI)

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 63

3.10 Low-Voltage Inhibit Module (LVI)

3.10.1 Wait Mode

If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.

3.10.2 Stop Mode

If enabled, the LVI module remains active in stop mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of stop mode.

3.11 Serial Communications Interface Module (SCI)

3.11.1 Wait Mode

The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.

If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.

3.11.2 Stop Mode

The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.

Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.

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Low-Power Modes

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64 Low-Power Modes MOTOROLA

3.12 Serial Peripheral Interface Module (SPI)

3.12.1 Wait Mode

The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.

3.12.2 Stop Mode

The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.

3.13 Timer Interface Module (TIM1 and TIM2)

3.13.1 Wait Mode

The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.

3.13.2 Stop Mode

The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.

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Low-Power Modes

Timebase Module (TBM)

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 65

3.14 Timebase Module (TBM)

3.14.1 Wait Mode

The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.

If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.

3.14.2 Stop Mode

The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.

If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during stop mode. In stop mode, the
timebase register is not accessible by the CPU.

If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.

3.15 Exiting Wait Mode

These events restart the CPU clock and load the program counter with
the reset vector or with an interrupt vector:

• External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.

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66 Low-Power Modes MOTOROLA

• External interrupt — A high-to-low transition on an external
interrupt pin (IRQ pin) loads the program counter with the contents
of locations: $FFFA and $FFFB; IRQ pin.

• Break interrupt — A break interrupt loads the program counter
with the contents of $FFFC and $FFFD.

• Computer operating properly module (COP) reset — A timeout of
the COP counter resets the MCU and loads the program counter
with the contents of $FFFE and $FFFF.

• Low-voltage inhibit module (LVI) reset — A power supply voltage
below the V

tripf

voltage resets the MCU and loads the program

counter with the contents of locations $FFFE and $FFFF.

• Clock generator module (CGM) interrupt — A CPU interrupt
request from the phase-locked loop (PLL) loads the program
counter with the contents of $FFF8 and $FFF9.

• Keyboard module (KBI) interrupt — A CPU interrupt request from
the KBI module loads the program counter with the contents of
$FFE0 and $FFE1.

• Timer 1 interface module (TIM1) interrupt — A CPU interrupt
request from the TIM1 loads the program counter with the
contents of:

– $FFF2 and $FFF3; TIM1 overflow

– $FFF4 and $FFF5; TIM1 channel 1

– $FFF6 and $FFF7; TIM1 channel 0

• Timer 2 interface module (TIM2) interrupt — A CPU interrupt
request from the TIM2 loads the program counter with the
contents of:

– $FFEC and $FFED; TIM2 overflow

– $FFEE and $FFEF; TIM2 channel 1

– $FFF0 and $FFF1; TIM2 channel 0

• Serial peripheral interface module (SPI) interrupt — A CPU
interrupt request from the SPI loads the program counter with the
contents of:

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Exiting Stop Mode

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Low-Power Modes 67

– $FFE8 and $FFE9; SPI transmitter

– $FFEA and $FFEB; SPI receiver

• Serial communications interface module (SCI) interrupt — A CPU
interrupt request from the SCI loads the program counter with the
contents of:

– $FFE2 and $FFE3; SCI transmitter

– $FFE4 and $FFE5; SCI receiver

– $FFE6 and $FFE7; SCI receiver error

• Analog-to-digital converter module (ADC) interrupt — A CPU
interrupt request from the ADC loads the program counter with the
contents of: $FFDE and $FFDF; ADC conversion complete.

• Timebase module (TBM) interrupt — A CPU interrupt request from
the TBM loads the program counter with the contents of: $FFDC
and $FFDD; TBM interrupt.

3.16 Exiting Stop Mode

These events restart the system clocks and load the program counter
with the reset vector or with an interrupt vector:

• External reset — A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.

• External interrupt — A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:

– $FFFA and $FFFB; IRQ pin

– $FFE0 and $FFE1; keyboard interrupt pins

• Low-voltage inhibit (LVI) reset — A power supply voltage below
the LVI

tripf

voltage resets the MCU and loads the program counter

with the contents of locations $FFFE and $FFFF.

• Break interrupt — A break interrupt loads the program counter
with the contents of locations $FFFC and $FFFD.

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68 Low-Power Modes MOTOROLA

• Timebase module (TBM) interrupt — A TBM interrupt loads the
program counter with the contents of locations $FFDC and $FFDD
when the timebase counter has rolled over. This allows the TBM
to generate a periodic wakeup from stop mode.

Upon exit from stop mode, the system clocks begin running after an
oscillator stabilization delay. A 12-bit stop recovery counter inhibits the
system clocks for 4096 CGMXCLK cycles after the reset or external
interrupt.

The short stop recovery bit, SSREC, in the configuration register
controls the oscillator stabilization delay during stop recovery. Setting
SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32
CGMXCLK cycles.

NOTE: Use the full stop recovery time (SSREC = 0) in applications that use an

external crystal.

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 69

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 4. Resets and Interrupts

4.1 Contents

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.3.3 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4.3.3.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4.3.3.2 COP Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.3 Low-Voltage Inhibit Reset . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.3.4 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .74

4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

4.4.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

4.4.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.4.2.1 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.3 IRQ

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.4 CGM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.5 TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.4.2.6 TIM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.4.2.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.4.2.8 SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

4.4.2.9 KBD0–KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.2.10 ADC (Analog-to-Digital Converter). . . . . . . . . . . . . . . . . .83

4.4.2.11 TBM (Timebase Module) . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.3 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.4.3.1 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .85

4.4.3.2 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .85

4.4.3.3 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .86

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Resets and Interrupts

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

70 Resets and Interrupts MOTOROLA

4.2 Introduction

Resets and interrupts are responses to exceptional events during
program execution. A reset re-initializes the MCU to its startup condition.
An interrupt vectors the program counter to a service routine.

4.3 Resets

A reset immediately returns the MCU to a known startup condition and
begins program execution from a user-defined memory location.

4.3.1 Effects

A reset:

• Immediately stops the operation of the instruction being executed

• Initializes certain control and status bits

• Loads the program counter with a user-defined reset vector
address from locations $FFFE and $FFFF

• Selects CGMXCLK divided by four as the bus clock

4.3.2 External Reset

A logic 0 applied to the RST

pin for a time, t

IRL

, generates an external

reset. An external reset sets the PIN bit in the SIM reset status register.

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Resets and Interrupts

Resets

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 71

4.3.3 Internal Reset

Sources:

• Power-on reset (POR)

• Computer operating properly (COP)

• Low-power reset circuits

• Illegal opcode

• Illegal address

All internal reset sources pull the RST pin low for 32 CGMXCLK cycles
to allow resetting of external devices. The MCU is held in reset for an
additional 32 CGMXCLK cycles after releasing the RST pin.

Figure 4-1. Internal Reset Timing

RST PIN

PULLED LOW BY MCU

INTERNAL

32 CYCLES 32 CYCLES

CGMXCLK

RESET

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Resets and Interrupts

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72 Resets and Interrupts MOTOROLA

4.3.3.1 Power-On Reset

A power-on reset (POR) is an internal reset caused by a positive
transition on the VDD pin. VDD at the POR must go completely to 0 V to
reset the MCU. This distinguishes between a reset and a POR. The POR
is not a brown-out detector, low-voltage detector, or glitch detector.

A power-on reset:

• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles

• Drives the RST pin low during the oscillator stabilization delay

• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay

• Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay

• Sets the POR and LP bits in the SIM reset status register and
clears all other bits in the register

Figure 4-2. Power-On Reset Recovery

PORRST

(1)

OSC1

CGMXCLK

CGMOUT

RST

PIN

INTERNAL

4096

CYCLES32CYCLES32CYCLES

1. PORRST is an internally generated power-on reset pulse.

RESET

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Resets and Interrupts

Resets

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 73

4.3.3.2 COP Reset

A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.

To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.

4.3.3.3 Low-Voltage Inhibit Reset

A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI

tripf

voltage.

An LVI reset:

• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI

tripr

voltage

• Drives the RST pin low for as long as VDD is below the LVI

tripr

voltage and during the oscillator stabilization delay

• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay

• Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay

• Sets the LVI bit in the SIM reset status register

4.3.3.4 Illegal Opcode Reset

An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.

If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

74 Resets and Interrupts MOTOROLA

4.3.3.5 Illegal Address Reset

An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.

A data fetch from an unmapped address does not generate a reset.

4.3.4 SIM Reset Status Register

This read-only register contains flags to show reset sources. All flag bits
are automatically cleared following a read of the register. Reset service
can read the SIM reset status register to clear the register after power­on reset and to determine the source of any subsequent reset.

The register is initialized on power-up as shown with the POR bit set and
all other bits cleared. During a POR or any other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a VIH at that time, then the
PIN bit in the SRSR may be set in addition to whatever other bits are set.

NOTE: Only a read of the SIM reset status register clears all reset flags. After

multiple resets from different sources without reading the register,
multiple flags remain set.

POR — Power-On Reset Flag

1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset

Address: $FE01

Bit 7654321Bit 0

Read: POR PIN COP ILOP ILAD MODRST LVI 0

Write:

POR:10000000

= Unimplemented

Figure 4-3. SIM Reset Status Register (SRSR)

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 75

PIN — External Reset Flag

1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit

1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations

$FFFE and $FFFF are $FF after POR while IRQ = V

DD

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR

4.4 Interrupts

An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.

4.4.1 Effects

An interrupt:

• Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.

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76 Resets and Interrupts MOTOROLA

• Sets the interrupt mask (I bit) to prevent additional interrupts.
Once an interrupt is latched, no other interrupt can take
precedence, regardless of its priority.

• Loads the program counter with a user-defined vector address

Figure 4-4. Interrupt Stacking Order

After every instruction, the CPU checks all pending interrupts if the I bit
is not set. If more than one interrupt is pending when an instruction is
done, the highest priority interrupt is serviced first. In the example shown
in Figure 4-5, if an interrupt is pending upon exit from the interrupt
service routine, the pending interrupt is serviced before the LDA
instruction is executed.

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER (LOW BYTE)*

PROGRAM COUNTER (HIGH BYTE)

PROGRAM COUNTER (LOW BYTE)

•

•

•

•

•

•

1

2

3

4

5

5

4

3

2

1

STACKING

ORDER

*High byte of index register is not stacked.

$00FF DEFAULT ADDRESS ON RESET

UNSTACKING

ORDER

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 77

Figure 4-5. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.

NOTE: To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the
H register and then restore it prior to exiting the routine.

CLI

LDA

INT1

PULH
RTI

INT2

BACKGROUND

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH
RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

ROUTINE

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Resets and Interrupts

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

78 Resets and Interrupts MOTOROLA

Figure 4-6. Interrupt Processing

NO

NO

NO

YES

NO

NO

YES

NO

YES

YES

FROM RESET

BREAK

I BIT SET?

IRQ

INTERRUPT

CGM

INTERRUPT

FETCH NEXT

INSTRUCTION

UNSTACK CPU REGISTERS

STACK CPU REGISTERS

SET I BIT

LOAD PC WITH INTERRUPT VECTOR

EXECUTE INSTRUCTION

YES

YES

I BIT SET?

INTERRUPT

YES

OTHER

INTERRUPTS

NO

SWI

INSTRUCTION

RTI

INSTRUCTION

?

?

?

?

?

?

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 79

4.4.2 Sources

The sources in Table 4-1 can generate CPU interrupt requests.

Table 4-1. Interrupt Sources

Source

Flag

Mask

(1)

1. The I bit in the condition code register is a global mask for all interrupt sources except the
SWI instruction.

INT Register

Flag

Priority

(2)

2. 0 = highest priority

Vector

Address

Reset None None None 0

$FFFE

–$FFFF

SWI instruction None None None 0

$FFFC–$FFFD

IRQ

pin IRQF IMASK IF1 1

$FFFA

–$FFFB

CGM (PLL) PLLF PLLIE IF2 2 $FFF8–$FFF9

TIM1 channel 0 CH0F CH0IE IF3 3 $FFF6–$FFF7

TIM1 channel 1 CH1F CH1IE IF4 4 $FFF4–$FFF5

TIM1 overflow TOF TOIE IF5 5 $FFF2–$FFF3

TIM2 channel 0 CH0F CH0IE IF6 6 $FFF0–$FFF1

TIM2 channel 1 CH1F CH1IE IF7 7 $FFEE–$FFEF

TIM2 overflow TOF TOIE IF8 8 $FFEC–$FFED

SPI receiver full SPRF SPRIE

IF9 9 $FFEA–$FFEBSPI overflow OVRF ERRIE

SPI mode fault MODF ERRIE

SPI transmitter empty SPTE SPTIE IF10 10 $FFE8–$FFE9

SCI receiver overrun OR ORIE

IF11 11 $FFE6–$FFE7

SCI noise fag NF NEIE

SCI framing error FE FEIE

SCI parity error PE PEIE

SCI receiver full SCRF SCRIE

IF12 12 $FFE4–$FFE5

SCI input idle IDLE ILIE

SCI transmitter empty SCTE SCTIE

IF13 13 $FFE2–$FFE3

SCI transmission complete TC TCIE

Keyboard pin KEYF IMASKK IF14 14 $FFE0–$FFE1

ADC conversion complete COCO AIEN IF15 15 $FFDE–$FFDF

Timebase TBIF TBIE IF16 16 $FFDC–$FFDD

Note:

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Resets and Interrupts

4.4.2.1 SWI Instruction

NOTE: A software interrupt pushes PC onto the stack. An SWI does not push

4.4.2.2 Break Interrupt

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4.4.2.3 IRQ Pin

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The software interrupt instruction (SWI) causes a non-maskable
interrupt.

PC – 1, as a hardware interrupt does.

The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.

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4.4.2.4 CGM

4.4.2.5 TIM1

A logic 0 on the IRQ pin latches an external interrupt request.

The CGM can generate a CPU interrupt request every time the phase­locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.

TIM1 CPU interrupt sources:

• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter reaches the modulo value programmed in the TIM1
counter modulo registers. The TIM1 overflow interrupt enable bit,
TOIE, enables TIM1 overflow CPU interrupt requests. TOF and
TOIE are in the TIM1 status and control register.

• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an

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input capture or output compare occurs on channel x.
The channel x interrupt enable bit, CHxIE, enables channel x
TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1
channel x status and control register.

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TIM2 CPU interrupt sources:

• TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2

• TIM2 channel flags (CH1F–CH0F) — The CHxF bit is set when an

Resets and Interrupts

Interrupts

counter reaches the modulo value programmed in the TIM2
counter modulo registers. The TIM2 overflow interrupt enable bit,
TOIE, enables TIM2 overflow CPU interrupt requests. TOF and
TOIE are in the TIM2 status and control register.

input capture or output compare occurs on channel x.
The channel x interrupt enable bit, CHxIE, enables channel x
TIM2 CPU interrupt requests. CHxF and CHxIE are in the TIM2
channel x status and control register.

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4.4.2.7 SPI

SPI CPU interrupt sources:

• SPI receiver full bit (SPRF) — The SPRF bit is set every time a
byte transfers from the shift register to the receive data register.
The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register
and SPRIE is in the SPI control register.

• SPI transmitter empty (SPTE) — The SPTE bit is set every time a
byte transfers from the transmit data register to the shift register.
The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register
and SPTIE is in the SPI control register.

• Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the

pin goes high during a transmission with the mode fault enable

SS
bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS
pin goes low at any time with the MODFEN bit set. The error
interrupt enable bit, ERRIE, enables MODF CPU interrupt
requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 81

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Resets and Interrupts

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

82 Resets and Interrupts MOTOROLA

• Overflow bit (OVRF) — The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.

4.4.2.8 SCI

SCI CPU interrupt sources:

• SCI transmitter empty bit (SCTE) — SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.

• Transmission complete bit (TC) — TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.

• SCI receiver full bit (SCRF) — SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.

• Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.

• Receiver overrun bit (OR) — OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 83

• Noise flag (NF) — NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.

• Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.

• Parity error bit (PE) — PE is set when the SCI detects a parity error
in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.

4.4.2.9 KBD0—KBD7 Pins

A logic 0 on a keyboard interrupt pin latches an external interrupt
request.

4.4.2.10 ADC (Analog-to-Digital Converter)

When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. The COCO bit is not used as
a conversion complete flag when interrupts are enabled.

4.4.2.11 TBM (Timebase Module)

The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2–TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

84 Resets and Interrupts MOTOROLA

4.4.3 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt
sources. Table 4-2 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.

Table 4-2. Interrupt Source Flags

Interrupt Source

Interrupt Status

Register Flag

Reset —

SWI instruction —

IRQ

pin IF1

CGM (PLL) IF2

TIM1 channel 0 IF3

TIM1 channel 1 IF4

TIM1 overflow IF5

TIM2 channel 0 IF6

TIM2 channel 1 IF7

TIM2 overflow IF8

SPI receive IF9

SPI transmit IF10

SCI error IF11

SCI receive IF12

SCI transmit IF13

Keyboard IF14

ADC conversion complete IF15

Timebase IF16

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Resets and Interrupts 85

4.4.3.1 Interrupt Status Register 1

IF6–IF1 — Interrupt Flags 6–1

These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.

1 = Interrupt request present
0 = No interrupt request present

Bit 1 and Bit 0 — Always read 0

4.4.3.2 Interrupt Status Register 2

IF14–IF7 — Interrupt Flags 14–7

These flags indicate the presence of interrupt requests from the
sources shown in Table 4-2.

1 = Interrupt request present
0 = No interrupt request present

Address: $FE04

Bit 7654321Bit 0

Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-7. Interrupt Status Register 1 (INT1)

Address: $FE05

Bit 7654321Bit 0

Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-8. Interrupt Status Register 2 (INT2)

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Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

86 Resets and Interrupts MOTOROLA

4.4.3.3 Interrupt Status Register 3

IF16–IF15 — Interrupt Flags 16–15

This flag indicates the presence of an interrupt request from the
source shown in Table 4-2.

1 = Interrupt request present
0 = No interrupt request present

Bits 7–2 — Always read 0

Address: $FE06

Bit 7654321Bit 0

Read: 000000IF16IF15

Write:RRRRRRRR

Reset:00000000

R = Reserved

Figure 4-9. Interrupt Status Register 3 (INT3)

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 87

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 5. Analog-to-Digital Converter (ADC)

5.1 Contents

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

5.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

5.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.4 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

5.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.7.1 ADC Analog Power Pin (V

DDAD

)/

ADC Voltage Reference High Pin (V

REFH

) . . . . . . . . . . .92

5.7.2 ADC Analog Ground Pin (V

SSAD

)/

ADC Voltage Reference Low Pin (V

REFL

) . . . . . . . . . . . .92

5.7.3 ADC Voltage In (V

ADIN

) . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

5.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . . .93

5.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

5.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

88 Analog-to-Digital Converter (ADC) MOTOROLA

5.2 Introduction

This section describes the 8-bit analog-to-digital converter (ADC).

5.3 Features

Features of the ADC module include:

• Eight channels with multiplexed input

• Linear successive approximation with monotonicity

• 8-bit resolution

• Single or continuous conversion

• Conversion complete flag or conversion complete interrupt

• Selectable ADC clock

5.4 Functional Description

The ADC provides eight pins for sampling external sources at pins
PTB7/AD7–PTB0/AD0. An analog multiplexer allows the single ADC
converter to select one of eight ADC channels as ADC voltage in
(V

ADIN

). V

ADIN

is converted by the successive approximation register­based analog-to-digital converter. When the conversion is completed,
ADC places the result in the ADC data register and sets a flag or
generates an interrupt. (See Figure 5-1.)

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Analog-to-Digital Converter (ADC)

Functional Description

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 89

Figure 5-1. ADC Block Diagram

5.4.1 ADC Port I/O Pins

PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that
share with the ADC channels. The channel select bits define which ADC
channel/port pin will be used as the input signal. The ADC overrides the
port I/O logic by forcing that pin as input to the ADC. The remaining ADC
channels/port pins are controlled by the port I/O logic and can be used
as general-purpose I/O. Writes to the port register or DDR will not have
any affect on the port pin that is selected by the ADC. Read of a port pin
in use by the ADC will return a logic 0.

INTERNAL
DATA BUS

READ DDRBx

WRITE DDRBx

RESET

WRITE PTBx

READ PTBx

PTBx

DDRBx

PTBx

INTERRUPT

LOGIC

CHANNEL

SELECT

ADC

CLOCK

GENERATOR

CONVERSION

COMPLETE

ADC

(V

ADIN

)

ADC CLOCK

CGMXCLK

BUS CLOCK

ADCH4–ADCH0

ADC DATA REGISTER

AIEN COCO

DISABLE

DISABLE

ADC CHANNEL x

ADIV2–ADIV0 ADICLK

VOLTAGE IN

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

90 Analog-to-Digital Converter (ADC) MOTOROLA

5.4.2 Voltage Conversion

When the input voltage to the ADC equals V

REFH

, the ADC converts the

signal to $FF (full scale). If the input voltage equals V

REFL

, the ADC

converts it to $00. Input voltages between V

REFH

and V

REFL

are a

straight-line linear conversion.

NOTE: Inside the ADC module, the reference voltages V

REFH

is connected to

the ADC analog power, V

DDAD

; and V

REFL

is connected to the ADC

analog ground, V

SSAD

. Therefore, the ADC input voltage should not

exceed these analog supply voltages.

Connect the V

DDAD

pin to the same voltage potential as the VDD pin, and

connect the V

SSAD

pin to the same voltage potential as the VSS pin.

The V

DDAD

pin should be routed carefully for maximum noise immunity.

5.4.3 Conversion Time

Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits
should be set to provide a 1-MHz ADC clock frequency.

5.4.4 Conversion

In continuous conversion mode, the ADC data register will be filled with
new data after each conversion. Data from the previous conversion will
be overwritten whether that data has been read or not. Conversions will
continue until the ADCO bit is cleared. The COCO bit is set after the first
conversion and will stay set until the next write of the ADC status and
control register or the next read of the ADC data register.

In single conversion mode, conversion begins with a write to the
ADSCR. Only one conversion occurs between writes to the ADSCR.

16 to 17 ADC cycles

ADC frequency

Conversion time =

Number of bus cycles = conversion time × bus frequency

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Analog-to-Digital Converter (ADC)

Interrupts

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 91

5.4.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.

5.5 Interrupts

When the AIEN bit is set, the ADC module is capable of generating CPU
interrupts after each ADC conversion. A CPU interrupt is generated if the
COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.

5.6 Low-Power Modes

The WAIT and STOP instruction can put the MCU in low power­consumption standby modes.

5.6.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4–ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.

5.6.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.

5.7 I/O Signals

The ADC module has eight pins shared with port B,
PTB7/AD7–PTB0/AD0.

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Analog-to-Digital Converter (ADC)

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92 Analog-to-Digital Converter (ADC) MOTOROLA

5.7.1 ADC Analog Power Pin (V

DDAD

)/ADC Voltage Reference High Pin (V

REFH

)

The ADC analog portion uses V

DDAD

as its power pin. Connect the

V

DDAD

pin to the same voltage potential as VDD. External filtering may

be necessary to ensure clean V

DDAD

for good results.

NOTE: For maximum noise immunity, route V

DDAD

carefully and place bypass

capacitors as close as possible to the package.

5.7.2 ADC Analog Ground Pin (V

SSAD

)/ADC Voltage Reference Low Pin (V

REFL

)

The ADC analog portion uses V

SSAD

as its ground pin. Connect the

V

SSAD

pin to the same voltage potential as VSS.

NOTE: Route V

SSAD

cleanly to avoid any offset errors.

5.7.3 ADC Voltage In (V

ADIN

)

V

ADIN

is the input voltage signal from one of the eight ADC channels to

the ADC module.

5.8 I/O Registers

These I/O registers control and monitor ADC operation:

• ADC status and control register (ADSCR)

• ADC data register (ADR)

• ADC clock register (ADCLK)

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Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 93

5.8.1 ADC Status and Control Register

Function of the ADC status and control register (ADSCR) is described
here.

COCO — Conversions Complete

When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed except in the continuous
conversion mode where it is set after the first conversion. This bit is
cleared whenever the ADSCR is written or whenever the ADR is read.

If the AIEN bit is a logic 1, the COCO becomes a read/write bit, which
should be cleared to logic 0 for CPU to service the ADC interrupt
request. Reset clears this bit.

1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)

AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.

1 = ADC interrupt enabled
0 = ADC interrupt disabled

ADCO — ADC Continuous Conversion Bit

When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.

1 = Continuous ADC conversion
0 = One ADC conversion

Address: $003C

Bit 7654321Bit 0

Read:

COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

Write:

Reset:00011111

Figure 5-2. ADC Status and Control Register (ADSCR)

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Analog-to-Digital Converter (ADC)

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

94 Analog-to-Digital Converter (ADC) MOTOROLA

ADCH4–ADCH0 — ADC Channel Select Bits

ADCH4–ADCH0 form a 5-bit field which is used to select one of 16
ADC channels. Only eight channels, AD7–AD0, are available on this
MCU. The channels are detailed in Table 5-1. Care should be taken
when using a port pin as both an analog and digital input
simultaneously to prevent switching noise from corrupting the analog
signal. (See Table 5-1.)

The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not being used.

NOTE: Recovery from the disabled state requires one conversion cycle to

stabilize.

The voltage levels supplied from internal reference nodes, as specified
in Table 5-1, are used to verify the operation of the ADC converter both
in production test and for user applications.

Table 5-1. Mux Channel Select

ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select

00000 PTB0/AD0

00001 PTB1/AD1

00010 PTB2/AD2

00011 PTB3/AD3

00100 PTB4/AD4

00101 PTB5/AD5

00110 PTB6/AD6

00111 PTB7/AD7

01000

Reserved

↓↓↓↓↓

11100

11101

V

REFH

11110

V

REFL

11111ADC power off

NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown

or reserved.

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Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Analog-to-Digital Converter (ADC) 95

5.8.2 ADC Data Register

One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.

5.8.3 ADC Clock Register

The ADC clock register (ADCLK) selects the clock frequency for the
ADC.

ADIV2–ADIV0 — ADC Clock Prescaler Bits

ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by
the ADC to generate the internal ADC clock. Table 5-2 shows the
available clock configurations. The ADC clock should be set to
approximately 1 MHz.

Address: $003D

Bit 7654321Bit 0

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:

Reset:00000000

= Unimplemented

Figure 5-3. ADC Data Register (ADR)

Address: $003E

Bit 7654321Bit 0

Read:

ADIV2 ADIV1 ADIV0 ADICLK

0000

Write:

Reset:00000000

= Unimplemented

Figure 5-4. ADC Clock Register (ADCLK)

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Analog-to-Digital Converter (ADC)

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96 Analog-to-Digital Converter (ADC) MOTOROLA

ADICLK — ADC Input Clock Select Bit

ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.

If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed.

1 = Internal bus clock
0 = External clock (CGMXCLK)

Table 5-2. ADC Clock Divide Ratio

ADIV2 ADIV1 ADIV0 ADC Clock Rate

0 0 0 ADC input clock

÷ 1

0 0 1 ADC input clock

÷ 2

0 1 0 ADC input clock

÷ 4

0 1 1 ADC input clock

÷ 8

1 X X ADC input clock ÷ 16

X = don’t care

ADC input clock frequency

ADIV2 ADIV0–

----------------------------------------------------------------------- 1 M H z=

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MC68HC908GP32•MC68HC08GP32 — Rev. 6 Technical Data

MOTOROLA Break Module (BRK) 97

Technical Data – MC68HC908GP32•MC68HC08GP32

Section 6. Break Module (BRK)

6.1 Contents

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

6.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .100

6.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

6.4.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . .100

6.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .100

6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

6.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

6.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .101

6.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .102

6.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6.6.4 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . .104

6.2 Introduction

This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.

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Break Module (BRK)

Technical Data MC68HC908GP32•MC68HC08GP32 — Rev. 6

98 Break Module (BRK) MOTOROLA

6.3 Features

Features of the break module include:

• Accessible input/output (I/O) registers during the break interrupt

• CPU-generated break interrupts

• Software-generated break interrupts

• COP disabling during break interrupts

6.4 Functional Description

When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.

• Software writes a logic 1 to the BRKA bit in the break status and
control register.

When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 6-1 shows the structure of the break module.

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