Motorola MC68HC908AB32 Technical Data Manual

MC68HC908AB32/D

REV. 1.0

MC68HC908AB32

HCMOS Microcontroller Unit

TECHNICAL DATA

Technical Data — MC68HC908AB32

Section 1. General Description . . . . . . . . . . . . . . . . . . . .29

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .41

Section 3. Random-Access Memory (RAM) . . . . . . . . . .57

Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .59

List of Sections

Section 5. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Section 6. Configuration Register (CONFIG) . . . . . . . . .85

Section 7. Central Processor Unit (CPU) . . . . . . . . . . . .89

Section 8. System Integration Module (SIM) . . . . . . . .109

Section 9. Clock Generator Module (CGM). . . . . . . . . .131

Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .157

Section 11. Timer Interface Module A (TIMA). . . . . . . .169

Section 12. Timer Interface Module B (TIMB). . . . . . . .195

Section 13. Programmable Interrupt Timer (PIT) . . . . .221

Section 14. Analog-to-Digital Converter (ADC) . . . . . .229

Section 15. Serial Communications Interface

Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Section 16. Serial Peripheral Interface Module (SPI). .279

Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . .311

Section 18. External Interrupt (IRQ) . . . . . . . . . . . . . . .339

Section 19. Keyboard Interrupt Module (KBI). . . . . . . .345

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Section 20. Computer Operating Properly (COP) . . . .353

Section 21. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .359

Section 22. Break Module (BRK) . . . . . . . . . . . . . . . . . .365

Section 23. Electrical Specifications. . . . . . . . . . . . . . .373

Section 24. Mechanical Specifications . . . . . . . . . . . . .387

Section 25. Ordering Information . . . . . . . . . . . . . . . . .389

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Section 1. General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table of Contents

1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.6.1 Power Supply Pins (V

DD

and V

). . . . . . . . . . . . . . . . . . . .34

SS

1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35

1.6.3 External Reset Pin (RST

1.6.4 External Interrupt Pin (IRQ

1.6.5 Analog Power Supply Pin (V

1.6.6 Analog Ground Pin (V

1.6.7 Analog Ground Pin (A

1.6.8 ADC Voltage Reference Pin (V

1.6.9 Analog Supply Pin (V

). . . . . . . . . . . . . . . . . . . . . . . . . . .35

) . . . . . . . . . . . . . . . . . . . . . . . . .35

). . . . . . . . . . . . . . . . . . . . .35

DDA

) . . . . . . . . . . . . . . . . . . . . . . . . . .35

SSA

/V

VSS

DDAREF

). . . . . . . . . . . . . . . . . . . . .35

REFL

). . . . . . . . . . . . . . . . . .36

REFH

) . . . . . . . . . . . . . . . . . . . . . . .36

1.6.10 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .36

1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .36

1.6.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . .36

1.6.13 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . .36

1.6.14 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .37

1.6.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . .37

1.6.16 Port F I/O Pins (PTF7–PTF0/TACH2) . . . . . . . . . . . . . . . . .37

1.6.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . . .37

1.6.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3). . . . . . . . . . . . .37

1.7 I/O Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.8 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

1.9 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

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Section 2. Memory Map

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .41

2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Section 3. Random-Access Memory (RAM)

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Section 4. FLASH Memory

4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .61

4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .62

4.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . . .63

4.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .66

4.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Section 5. EEPROM

5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

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5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.5 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.6 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . . .72

5.7 EEPROM Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.8 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.9 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . . .73

5.9.1 EEPROM Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . .74

5.9.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.10 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11 EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11.1 EEPROM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11.2 EEPROM Array Configuration Register . . . . . . . . . . . . . . . .79

5.11.2.1 EEPROM Non-Volatile Register . . . . . . . . . . . . . . . . . . .80

5.11.3 EEPROM Timebase Divider Register . . . . . . . . . . . . . . . . .80

5.11.3.1 EEPROM Timebase Divider Non-Volatile Register . . . . .82

Section 6. Configuration Register (CONFIG)

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

6.3 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

6.4 Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

6.5 Configuration Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Section 7. Central Processor Unit (CPU)

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

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7.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

7.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Section 8. System Integration Module (SIM)

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .112

8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

8.3.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . .113

8.3.3 Clocks in Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . .113

8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .113

8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . .114

8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

8.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . .116

8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .117

8.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . .117

8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .117

8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

8.5.1 SIM Counter during Power-On Reset. . . . . . . . . . . . . . . . .118

8.5.2 SIM Counter during Stop Mode Recovery . . . . . . . . . . . . .118

8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .118

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8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

8.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

8.6.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

8.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .123

8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

8.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

8.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .127

8.8.2 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . .128

8.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .129

Section 9. Clock Generator Module (CGM)

9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

9.4.1 Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . .134

9.4.2 Phase-Locked Loop (PLL) Circuit . . . . . . . . . . . . . . . . . . .135

9.4.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

9.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . .136

9.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . . .136

9.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . .138

9.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . . .139

9.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . .140

9.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . .140

9.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

9.5.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .142

9.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .142

9.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . .142

9.5.4 PLL Analog Power Pin (V

) . . . . . . . . . . . . . . . . . . . . . .142

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9.5.5 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .142

9.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . .143

9.5.7 CGM Base Clock Output (CGMOUT). . . . . . . . . . . . . . . . .143

9.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .143

9.6 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

9.6.1 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . .144

9.6.2 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . .146

9.6.3 PLL Programming Register (PPG). . . . . . . . . . . . . . . . . . .148

9.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

9.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

9.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

9.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

9.9 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .151

9.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .151

9.10.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .152

9.10.2 Parametric Influences On Reaction Time. . . . . . . . . . . . . .153

9.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . .154

9.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . .155

Section 10. Monitor ROM (MON)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

10.4.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .160

10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

10.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

10.4.4 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

10.4.5 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

10.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

10.6 Extended Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

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Section 11. Timer Interface Module A (TIMA)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

11.5.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .171

11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .175

11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .176

11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .177

11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .178

11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .179

11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

11.8 TIMA During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .182

11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.9.1 TIMA Clock Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.9.2 TIMA Channel I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .183

11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.10.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . .184

11.10.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .186

11.10.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .187

11.10.4 TIMA Channel Status and Control Registers . . . . . . . . . . .188

11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .192

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Section 12. Timer Interface Module B (TIMB)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

12.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

12.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

12.5.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .197

12.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

12.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

12.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .201

12.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .202

12.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .203

12.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .204

12.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .205

12.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

12.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

12.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

12.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

12.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

12.8 TIMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .208

12.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

12.9.1 TIMB Clock Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

12.9.2 TIMB Channel I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .209

12.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

12.10.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . .210

12.10.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .212

12.10.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .213

12.10.4 TIMB Channel Status and Control Registers . . . . . . . . . . .214

12.10.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . .218

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Section 13. Programmable Interrupt Timer (PIT)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

13.4.1 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

13.6 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .224

13.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

13.7.1 PIT Status and Control Register. . . . . . . . . . . . . . . . . . . . .225

13.7.2 PIT Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

13.7.3 PIT Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . .228

Section 14. Analog-to-Digital Converter (ADC)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

14.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

14.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

14.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

14.4.4 Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

14.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

14.7.1 ADC Analog Power Pin (V

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14.7.2 ADC Analog Ground Pin (A

14.7.3 ADC Voltage Reference High Pin (V

14.7.4 ADC Voltage In (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . .234

ADIN

VSS

/V

) . . . . . . . . . . . . . . .234

REFL

). . . . . . . . . . . . .234

REFH

14.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

14.8.1 ADC Status and Control Register (ADSCR). . . . . . . . . . . .235

14.8.2 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .237

14.8.3 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . .237

Section 15. Serial Communications Interface

Module (SCI)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

15.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

15.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

15.5.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

15.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

15.5.2.2 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . .247

15.5.2.3 Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

15.5.2.4 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

15.5.2.5 Inversion of Transmitted Output. . . . . . . . . . . . . . . . . . .249

15.5.2.6 Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .249

15.5.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

15.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

15.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . .250

15.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

15.5.3.4 Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

15.5.3.5 Baud Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . .254

15.5.3.6 Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

15.5.3.7 Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

15.5.3.8 Error Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

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15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

15.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .260

15.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

15.8.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . .260

15.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . .260

15.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

15.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

15.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

15.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .267

15.9.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

15.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

15.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

15.9.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . .275

Section 16. Serial Peripheral Interface Module (SPI)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

16.4 Pin Name Conventions and I/O Register Addresses . . . . . . .281

16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

16.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

16.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

16.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

16.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . .285

16.6.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . .286

16.6.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . .288

16.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . .289

16.7 Queuing Transmission Data. . . . . . . . . . . . . . . . . . . . . . . . . .291

16.8 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

16.8.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

16.8.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

16.9 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

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16.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

16.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

16.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

16.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

16.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .300

16.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

16.13.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . .301

16.13.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . .301

16.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . .302

16.13.4 SS

(Slave Select). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302

16.13.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

16.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

16.14.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

16.14.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . .306

16.14.3 SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

Section 17. Input/Output (I/O) Ports

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

17.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

17.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . .316

17.3.2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . .316

17.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

17.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . .318

17.4.2 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . .319

17.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

17.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . .320

17.5.2 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . .321

17.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

17.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . .323

17.6.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . .324

17.6.3 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . .325

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17.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326

17.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . .326

17.7.2 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . .328

17.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

17.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .329

17.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . .330

17.8.3 Port F Input Pullup Enable Register (PTFPUE) . . . . . . . . .332

17.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332

17.9.1 Port G Data Register (PTG). . . . . . . . . . . . . . . . . . . . . . . .332

17.9.2 Data Direction Register G (DDRG) . . . . . . . . . . . . . . . . . .333

17.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

17.10.1 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . .335

17.10.2 Data Direction Register H (DDRH). . . . . . . . . . . . . . . . . . .335

Section 18. External Interrupt (IRQ)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340

18.4.1 IRQ

Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

18.5 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .343

18.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .344

Section 19. Keyboard Interrupt Module (KBI)

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

19.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

19.5.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .349

19.5.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .349

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19.5.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .351

19.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

19.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

19.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .352

Section 20. Computer Operating Properly (COP)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353

20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

20.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

20.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

20.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

20.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

20.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355

20.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

20.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

20.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .356

20.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .356

20.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

20.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

20.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

20.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357

20.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

20.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

20.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .358

Section 21. Low-Voltage Inhibit (LVI)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

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21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360

21.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

21.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .361

21.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .361

21.5 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .362

21.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

21.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

21.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

21.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363

Section 22. Break Module (BRK)

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

22.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .368

22.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .368

22.4.3 PIT, TIMA, and TIMB During Break Interrupts . . . . . . . . . .368

22.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .368

22.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368

22.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368

22.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

22.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

22.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .369

22.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .370

22.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .370

22.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .372

Section 23. Electrical Specifications

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

23.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .374

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23.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .375

23.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375

23.6 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .376

23.7 EEPROM and Memory Characteristics . . . . . . . . . . . . . . . . .377

23.8 5.0-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378

23.9 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .378

23.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

23.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

23.12 Clock Generation Module Characteristics . . . . . . . . . . . . . . .383

23.12.1 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . .383

23.12.2 CGM Component Information . . . . . . . . . . . . . . . . . . . . . .383

23.12.3 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . .384

23.13 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . .385

Section 24. Mechanical Specifications

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387

24.3 64-Pin Plastic Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . .388

Section 25. Ordering Information

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

25.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

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1-1 MC68HC908AB32 Block Diagram . . . . . . . . . . . . . . . . . . . . . .32

1-2 64-Pin QFP Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . .33

1-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . . .45

4-1 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .60

4-2 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .65

4-4 FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . . . .66

4-3 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .66

List of Figures

5-1 EEPROM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .70

5-2 EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . . . .77

5-3 EEPROM Array Configuration Register (EEACR) . . . . . . . . . .79

5-4 EEPROM Non-Volatile Register (EENVR). . . . . . . . . . . . . . . .80

5-5 EEPROM Divider Register High (EEDIVH) . . . . . . . . . . . . . . .81

5-6 EEPROM Divider Register Low (EEDIVL) . . . . . . . . . . . . . . . .81

5-7 EEPROM Divider Non-volatile Register High(EEDIVHNVR) . .82
5-8 EEPROM Divider Non-volatile Register Low (EEDIVLNVR) . .82

6-1 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .86

6-2 Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .88

7-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7-6 Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . .94

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Figure Title Page

8-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

8-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .112

8-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

8-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

8-5 Internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

8-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .115

8-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

8-8 Interrupt Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

8-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .119

8-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

8-11 Interrupt Recognition Example. . . . . . . . . . . . . . . . . . . . . . . .121

8-12 Wait Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

8-13 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . .125

8-14 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .125

8-15 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

8-16 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .126

8-17 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .127

8-18 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .128

8-19 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .129

9-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

9-2 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .134

9-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .141

9-4 CGM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .144

9-5 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .144

9-7 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .146

9-8 PLL Programming Register (PPG). . . . . . . . . . . . . . . . . . . . .148

10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

10-3 Sample Monitor Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . .161

10-4 Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

10-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

10-6 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .167

11-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

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Figure Title Page

11-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .173

11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .177

11-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .184

11-5 TIMA Counter Register High (TACNTH). . . . . . . . . . . . . . . . .186

11-6 TIMA Counter Register Low (TACNTL) . . . . . . . . . . . . . . . . .187

11-7 TIMA Counter Modulo Register High (TAMODH). . . . . . . . . .187

11-8 TIMA Counter Modulo Register Low (TAMODL) . . . . . . . . . .187

11-9 TIMA Channel 0 Status and Control Register (TASC0) . . . . .188

11-10 TIMA Channel 1 Status and Control Register (TASC1) . . . . .188

11-11 TIMA Channel 2 Status and Control Register (TASC2) . . . . .189

11-12 TIMA Channel 3 Status and Control Register (TASC3) . . . . .189

11-13.CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

11-14 TIMA Channel 0 Register High (TACH0H). . . . . . . . . . . . . . .192

11-15 TIMA Channel 0 Register Low (TACH0L). . . . . . . . . . . . . . . .192

11-16 TIMA Channel 1 Register High (TACH1H). . . . . . . . . . . . . . .193

11-17 TIMA Channel 1 Register Low (TACH1L). . . . . . . . . . . . . . . .193

11-18 TIMA Channel 2 Register High (TACH2H). . . . . . . . . . . . . . .193

11-19 TIMA Channel 2 Register Low (TACH2L). . . . . . . . . . . . . . . .193

11-20 TIMA Channel 3 Register High (TACH3H). . . . . . . . . . . . . . .194

11-21 TIMA Channel 3 Register Low (TACH3L). . . . . . . . . . . . . . . .194

12-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

12-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .199

12-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .203

12-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .210

12-5 TIMB Counter Register High (TBCNTH). . . . . . . . . . . . . . . . .212

12-6 TIMB Counter Register Low (TBCNTL) . . . . . . . . . . . . . . . . .213

12-7 TIMB Counter Modulo Register High (TBMODH). . . . . . . . . .213

12-8 TIMB Counter Modulo Register Low (TBMODL) . . . . . . . . . .213

12-9 TIMB Channel 0 Status and Control Register (TBSC0) . . . . .214

12-10 TIMB Channel 1 Status and Control Register (TBSC1) . . . . .214

12-11 TIMB Channel 2 Status and Control Register (TBSC2) . . . . .215

12-12 TIMB Channel 3 Status and Control Register (TBSC3) . . . . .215

12-13.CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

12-14 TIMB Channel 0 Register High (TBCH0H). . . . . . . . . . . . . . .218

12-15 TIMB Channel 0 Register Low (TBCH0L). . . . . . . . . . . . . . . .218

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Figure Title Page

12-16 TIMB Channel 1 Register High (TBCH1H). . . . . . . . . . . . . . .219

12-17 TIMB Channel 1 Register Low (TBCH1L). . . . . . . . . . . . . . . .219

12-18 TIMB Channel 2 Register High (TBCH2H). . . . . . . . . . . . . . .219

12-19 TIMB Channel 2 Register Low (TBCH2L). . . . . . . . . . . . . . . .219

12-20 TIMB Channel 3 Register High (TBCH3H). . . . . . . . . . . . . . .220

12-21 TIMB Channel 3 Register Low (TBCH3L). . . . . . . . . . . . . . . .220

13-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

13-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .223

13-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . .225

13-4 PIT Counter Register High (PCNTH) . . . . . . . . . . . . . . . . . . .227

13-5 PIT Counter Register Low (PCNTL). . . . . . . . . . . . . . . . . . . .228

13-6 PIT Counter Modulo Register High (PMODH) . . . . . . . . . . . .228

13-7 PIT Counter Modulo Register Low (PMODL). . . . . . . . . . . . .228

14-1 ADC Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

14-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

14-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .235

14-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .237

14-5 ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . .237

15-1 SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .243

15-2 SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .244

15-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

15-4 SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

15-5 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .251

15-6 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

15-7 Slow Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

15-8 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

15-9 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .262

15-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .265

15-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .267

15-12 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .269

15-13 Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

15-14 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .273

15-15 SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .274

15-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .275

Technical Data MC68HC908AB32 — Rev. 1.0

24 List of Figures MOTOROLA

List of Figures

Figure Title Page

16-1 SPI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .281

16-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .282

16-3 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .283

16-4 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .287

16-5 CPHA/SS

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

16-6 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .288

16-7 Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . . .290

16-8 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .291

16-9 Missed Read of Overflow Condition. . . . . . . . . . . . . . . . . . . .293

16-10 Clearing SPRF When OVRF Interrupt Is Not Enabled. . . . . .294

16-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .297

16-12 CPHA/SS

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302

16-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .304

16-14 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .306

16-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .309

17-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .312

17-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .316

17-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .316

17-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

17-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .318

17-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .319

17-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

17-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .320

17-9 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .321

17-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

17-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .323

17-12 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .324

17-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

17-14 Port D Input Pullup Enable Register (PTDPUE). . . . . . . . . . .325

17-15 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .326

17-16 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .328

17-17 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

17-18 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .329

17-19 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .330

17-20 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA List of Figures 25

List of Figures

Figure Title Page

17-21 Port F Input Pullup Enable Register (PTFPUE) . . . . . . . . . . .332

17-22 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . .333

17-23 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . .333

17-24 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

17-25 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .335

17-26 Data Direction Register H (DDRH). . . . . . . . . . . . . . . . . . . . .336

17-27 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .336

18-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .341

18-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .341

18-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .343

19-1 KBI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .346

19-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .347

19-3 Keyboard Status and Control Register (KBSCR). . . . . . . . . .350

19-4 Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . .351

20-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354

20-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .356

20-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .357

21-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .360

21-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .361

21-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .362

22-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .367

22-2 Break Module I/O Register Summary. . . . . . . . . . . . . . . . . . .367

22-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .369

22-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .370

22-5 Break Address Register Low (BRKL). . . . . . . . . . . . . . . . . . .370

22-6 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .371

22-7 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .372

23-1 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

23-2 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

24-1 64-Pin Plastic Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . .388

Technical Data MC68HC908AB32

26

List of Figures MOTOROLA

Rev. 1.0

—

Technical Data — MC68HC908AB32

List of Tables

Table Title Page

1-1 I/O Pins Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1-2 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

1-3 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

2-1 Vector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

5-1 EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . .73

5-2 EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . .78

7-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

7-2 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

8-1 Signal naming conventions. . . . . . . . . . . . . . . . . . . . . . . . . . .111

8-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

8-3 Vector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

8-4 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

9-1 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . .149

10-1 Monitor Mode Entry Conditions . . . . . . . . . . . . . . . . . . . . . . .160

10-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

10-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .163

10-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .164

10-5 IREAD (Indexed Read) Command. . . . . . . . . . . . . . . . . . . . .164

10-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .165

10-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .165

10-8 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .166

10-9 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .166

11-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

11-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .191

MC68HC908AB32
MOTOROLA List of Tables

Rev. 1.0 Technical Data

—

27

List of Tables

Table Title Page

12-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

12-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

12-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .217

13-1 PIT Prescaler Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

14-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

14-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

15-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

15-2 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

15-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

15-4 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

15-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .264

15-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .275

15-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .276

15-8 SCI Baud Rate Selection Examples. . . . . . . . . . . . . . . . . . . .277

16-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

16-2 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

16-3 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

16-4 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .308

17-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .314

17-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

17-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

17-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

17-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325

17-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

17-7 Port F Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

17-8 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334

17-9 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

19-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

21-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362

25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

Technical Data MC68HC908AB32

28

List of Tables MOTOROLA

Rev. 1.0

—

Technical Data — MC68HC908AB32

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

1.6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

1.6.1 Power Supply Pins (V

1.6.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35

1.6.3 External Reset Pin (RST

1.6.4 External Interrupt Pin (IRQ

1.6.5 Analog Power Supply Pin (V

1.6.6 Analog Ground Pin (V

1.6.7 Analog Ground Pin (A

1.6.8 ADC Voltage Reference Pin (V

1.6.9 Analog Supply Pin (V

1.6.10 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . .36

1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . .36

1.6.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . .36

1.6.13 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . . .36

1.6.14 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .37

1.6.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . . .37

1.6.16 Port F I/O Pins (PTF7–PTF0/TACH2) . . . . . . . . . . . . . . . . .37

1.6.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . . .37

1.6.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3). . . . . . . . . . . . .37

Section 1. General Description

and VSS). . . . . . . . . . . . . . . . . . . .34

DD

). . . . . . . . . . . . . . . . . . . . . . . . . . .35

) . . . . . . . . . . . . . . . . . . . . . . . . .35

). . . . . . . . . . . . . . . . . . . . .35

DDA

) . . . . . . . . . . . . . . . . . . . . . . . . . .35

SSA
VSS/VREFL

DDAREF

). . . . . . . . . . . . . . . . . . . . .35

). . . . . . . . . . . . . . . . . .36

REFH

) . . . . . . . . . . . . . . . . . . . . . . .36

1.7 I/O Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

1.8 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

1.9 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 29

General Description

1.2 Introduction

The MC68HC908AB32 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs) with embedded
EEPROM for user data storage. All MCUs in the family use the
enhanced M68HC08 central processor unit (CPU08) and are available
with a variety of modules, memory sizes and types, and package types.

1.3 Features

Features of the MC68HC908AB32 include the following:

• High-performance M68HC08 architecture

• Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families

• Memory map and pin functions compatible with MC68HC08AB32
and MC68HC08AB16

• 8-MHz internal bus frequency

• 32K-bytes user program FLASH memory with security

1

feature

• 512 bytes of on-chip EEPROM with security feature

• 1K-byte of on-chip RAM

• Clock generator module (CGM)

• Two 16-bit, 4-channel timer interface modules (TIMA and TIMB)
with selectable input capture, output compare, and PWM
capability on each channel

• Programmable interrupt timer (PIT)

• Serial peripheral interface module (SPI)

• Serial communications interface module (SCI)

• 8-channel. 8-bit analog-to-digital converter (ADC)

• Low-power design (fully static with STOP and WAIT modes)

• Master reset pin and power-on reset

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.

Technical Data MC68HC908AB32 — Rev. 1.0

30 General Description MOTOROLA

• 51 general-purpose input/output (I/O) pins:
– 30 shared-function I/O pins
– 5-bit keyboard wakeup port
– Selectable pullups on inputs on port D and port F

• System protection features
– Optional computer operating properly (COP) reset
– Low-voltage detection with optional reset
– Illegal opcode detection with optional reset
– Illegal address detection with optional reset

• 64-pin quad flat pack (QFP)

Features of the CPU08 include the following:

General Description

MCU Block Diagram

• Enhanced HC05 programming model

• Extensive loop control functions

• 16 addressing modes (eight more than the HC05)

• 16-bit Index register and stack pointer

• Memory-to-memory data transfers

• Fast 8 × 8 multiply instruction

• Fast 16/8 divide instruction

• Binary-coded decimal (BCD) instructions

• Optimization for controller applications

• Efficient C language support

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908AB32.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 31

Technical Data MC68HC908AB32 — Rev. 1.0

32 General Description MOTOROLA

M68HC08 CPU

CPU

REGISTERS

ARITHMETIC/LOGIC

UNIT (ALU)

CONTROL AND STATUS REGISTERS — 80 BYTES

USER FLASH — 32,256 BYTES

USER RAM — 1024 BYTES

USER EEPROM — 512 BYTES

MONITOR ROM — 307 BYTES

USER FLASH VECTORS — 48 BYTES

CLOCK GENERATOR MODULE

OSC1

4.9125-MHz OSCILLATOR

OSC2

CGMXFC

* RST

* IRQ

PHASE-LOCKED LOOP

SYSTEM INTEGRATION

MODULE

SINGLE EXTERNAL IRQ

MODULE

V

REFH

A

VSS/VREFL

V

DDAREF

V

V

V

DD

V

SS

DDA

SSA

8-BIT ANALOG-TO-DIGITAL

CONVERTER MODULE

POWER

† Ports are software configurable with pullup device if input port.
‡ Higher current drive port pins
* Pin contains integrated pullup device
** Pullup enabled when configured as keyboard interrupt pin

INTERNAL BUS

4-CHANNEL TIMER INTERFACE

MODULE A

4-CHANNEL TIMER INTERFACE

MODULE B

PROGRAMMABLE INTERRUPT

TIMER MODULE

SERIAL COMMUNICATIONS

INTERFACE MODULE

SERIAL PERIPHERAL
INTERFACE MODULE

KEYBOARD

INTERRUPT MODULE

COMPUTER OPERATING

PROPERLY MODULE

LOW-VOLTAGE

INHIBIT MODULE

POWER-ON RESET

MODULE

DDRA

PORTA

DDRB

PORTB

DDRC

PORTC

DDRD

PORTD

DDRE

PORTE

DDRF

PORTF

DDRG

PORTG

DDRH

PORTH

PTA7 – PTA0

PTB7/ATD7 – PTB0/ATD0

PTC5 – PTC0
(PTC2/MCLK)

PTD7 – PTD0

†‡

(PTD6/TACLK)
(PTD4/TBCLK)

PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
PTE0/TxD

†

PTF7

†

PTF6
PTF5/TBCH1
PTF4/TBCH0
PTF3/TBCH3
PTF2/TBCH2
PTF1/TACH3
PTF0/TACH2

†
†
†
†
†
†

PTG2/KBD2 – PTG0/KBD0 **

PTH1/KBD4 – PTH0/KBD3 **

General Description

Figure 1-1. MC68HC908AB32 Block Diagram

1.5 Pin Assignments

Figure 1-2 shows the pin assignment for the MC68HC908AB32.

PTC5

PTC3

PTC2/MCLK

PTC1

PTC0

OSC1

OSC2

SSAVDDA

CGMXFC

V

VREFH

PTD7

PTD6/TACLK

PTD5

PTD4/TBCLK

General Description

Pin Assignments

PTH1/KBD4

PTC4

IRQ

RST
PTF0/TACH2
PTF1/TACH3
PTF2/TBCH2
PTF3/TBCH3
PTF4/TBCH0

NC

PTF7

PTF5/TBCH1

PTF6

PTE0/TxD

PTE1/RxD
PTE2/TACH0
PTE3/TACH1

1

16

64

2
3
4
5
6
7
8
9
10
11
12
13
14
15

17

PTE4/SS

63

62

61

18

19

20

PTE6/MOSI

PTE5/MISO

PTE7/SPSCK

60

21

V

SS

59

58

22

23

DD

V

PTG0/KBD0

57

56

55

24

25

26

PTA0

PTG1/KBD1

PTG2/KBD2

54

27

PTA1

53

28

PTA2

52

29

PTA3

51

30

PTA4

50

47
46
45
44
43
42
41
40
39
38
37
36
35
34

31

PTA5

49

48

33

32

PTA6

PTH0/KBD3
PTD3
PTD2
A

/VREFL

VSS

V

DDAREF

PTD1
PTD0

PTB7/ATD7
PTB6/ATD6

PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTA7

Figure 1-2. 64-Pin QFP Pin Assignment

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 33

General Description

1.6 Pin Functions

Description of pin functions are provided here.

1.6.1 Power Supply Pins (V

and VSS)

DD

and VSS are the power supply and ground pins. The MCU operates

V

DD

from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-3
shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.

MCU

V

DD

C1

0.1 µF

V

SS

+

C2

V

DD

NOTE: Component values shown

represent typical applications.

Figure 1-3. Power Supply Bypassing

V

is also the ground for the port output buffers and the ground return

SS

for the serial clock in the serial peripheral interface module (SPI). See

Section 16. Serial Peripheral Interface Module (SPI).

V

must be grounded for proper MCU operation.

SS

Technical Data MC68HC908AB32 — Rev. 1.0

34 General Description MOTOROLA

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Section 9. Clock Generator Module (CGM).

General Description

Pin Functions

1.6.3 External Reset Pin (RST

)

A logic 0 on the RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor. See Section 8. System Integration Module (SIM).

1.6.4 External Interrupt Pin (IRQ

is an asynchronous external interrupt pin. This pin contains an

IRQ

)

internal pullup resistor. See Section 18. External Interrupt (IRQ).

1.6.5 Analog Power Supply Pin (V

is the power supply pin for the clock generator module (CGM).

V

DDA

1.6.6 Analog Ground Pin (V

SSA

)

DDA

pin forces the MCU to a known start-up state. RST

)

The V

analog ground pin is used only for the ground connections for

SSA

the clock generator module (CGM) section of the circuit and should be
decoupled as per the V

digital ground pin. See Section 9. Clock

SS

Generator Module (CGM).

1.6.7 Analog Ground Pin (A

The A

/VREFL)

VSS

analog ground pin is used only for the ground connections for

VSS

the analog to digital convertor (ADC) and should be decoupled as per
the V

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 35

digital ground pin.

SS

General Description

1.6.8 ADC Voltage Reference Pin (VREFH)

VREFH is the power supply for setting the reference voltage VREFH.
Connect this pin to a voltage such that 1.5V < VREFH ≤ V

DDAREF

.

1.6.9 Analog Supply Pin (V

The V

DDAREF

DDAREF

)

analog supply pin is used only for the supply connections

for the analog-to-digital convertor (ADC).

1.6.10 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Section 9. Clock Generator Module (CGM).

1.6.11 Port A Input/Output (I/O) Pins (PTA7–PTA0)

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See

Section 17. Input/Output (I/O) Ports.

1.6.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)

PTB7–PTB0 are special function, bidirectional port pins. PTB7–PTB0
are shared with the analog to digital convertor (ADC) input pins
ATD7–ATD0. See Section 14. Analog-to-Digital Converter (ADC) and

Section 17. Input/Output (I/O) Ports.

1.6.13 Port C I/O Pins (PTC5–PTC0)

PTC5–PTC0 are general-purpose bidirectional I/O port pins. PTC2 is a
special function port pin that is shared with the system clock output pin,
MCLK. See Section 17. Input/Output (I/O) Ports.

Technical Data MC68HC908AB32 — Rev. 1.0

36 General Description MOTOROLA

1.6.14 Port D I/O Pins (PTD7–PTD0)

PTD7–PTD0 are general-purpose bidirectional I/O port pins. PTD6 and
PTD4 are special function port pins that are shared with the timer
interface modules (TIMA and TIMB). See Section 11. Timer Interface

Module A (TIMA) and Section 12. Timer Interface Module B (TIMB).

1.6.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)

PTE7–PTE0 are special function, bidirectional port pins. PTE7–PTE4
are shared with the serial peripheral interface mode (SPI), PTE3–PTE2
are shared with timer A (TIMA), and PTE1–PTE0 are shared with the
serial communications interface (SCI). See Section 15. Serial

Communications Interface Module (SCI), Section 16. Serial
Peripheral Interface Module (SPI), Section 11. Timer Interface
Module A (TIMA), and Section 17. Input/Output (I/O) Ports.

General Description

Pin Functions

1.6.16 Port F I/O Pins (PTF7–PTF0/TACH2)

PTF7–PTF6 are general-purpose bidirectional I/O port pins.
PTF5–PTF0 are special function, bidirectional port pins. PTF5–PTF2
are shared with timer B (TIMB), and PTF1–PTF0 are shared with timer
A (TIMA). See Section 11. Timer Interface Module A (TIMA), Section

12. Timer Interface Module B (TIMB), and Section 17. Input/Output
(I/O) Ports.

1.6.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0)

PTG2–PTG0 are general-purpose bidirectional I/O pins with keyboard
wakeup function. See Section 19. Keyboard Interrupt Module (KBI)
and Section 17. Input/Output (I/O) Ports.

1.6.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)

PTH1–PTH0 are general-purpose bidirectional I/O pins with Keyboard
wakeup function. See Section 19. Keyboard Interrupt Module (KBI)
and Section 17. Input/Output (I/O) Ports.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 37

General Description

1.7 I/O Pin Summary

Table 1-1. I/O Pins Summary

Pin Name Function Driver Type Hysteresis Reset State

PTA7–PTA0 General purpose I/O Dual State No Input (Hi-Z)

PTB7/ATD7–PTB0/ATD0

PTC5–PTC3 General purpose I/O Dual State No Input (Hi-Z)

PTC2/MCLK

PTC1–PTC0 General purpose I/O Dual State No Input (Hi-Z)
PTD7 General purpose I/O Dual State No Input (Hi-Z)

PTD6/TACLK

PTD5 General purpose I/O Dual State No Input (Hi-Z)

PTD4/TBCLK

PTD3–PTD0 General purpose I/O Dual State No Input (Hi-Z)

PTE7/SPSCK

PTE6/MOSI

PTE5/MISO

General purpose I/O
/ ADC channel

General purpose I/O
/ System clock

General purpose I/O
/ Timer external input clock

General purpose I/O
/ Timer external input clock

General purpose I/O
/ SPI clock

General purpose I/O
/ SPI data path

General purpose I/O
/ SPI data path

Dual State No Input (Hi-Z)

Dual State No Input (Hi-Z)

Dual State No Input (Hi-Z)

Dual State No Input (Hi-Z)

Dual State

(open drain)

Dual State

(open drain)

Dual State

(open drain)

Yes Input (Hi-Z)

Yes Input (Hi-Z)

Yes Input (Hi-Z)

PTE4/SS

PTE3/TACH1

PTE2/TACH0

PTE1/RxD

PTE0/TxD

PTF7–PTF6 General purpose I/O Dual State Yes Input (Hi-Z)

PTF5/TBCH1

Technical Data MC68HC908AB32 — Rev. 1.0

General purpose I/O
/ SPI slave select

General purpose I/O
/ Timer A channel 1

General purpose I/O
/ Timer A channel 0

General purpose I/O
/ SCI receive data

General purpose I/O
/ SCI transmit data

General purpose I/O
/ Timer B channel 1

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

38 General Description MOTOROLA

General Description

I/O Pin Summary

Table 1-1. I/O Pins Summary

Pin Name Function Driver Type Hysteresis Reset State

PTF4/TBCH0

PTF3/TBCH3

PTF2/TBCH2

PTF1/TACH3

PTF0/TACH2

PTG2/KBD2–PTG0/KBD0

PTH1/KBD4–PTH0/KBD3

V

DD

V

SS

V

DDA

V

SSA

General purpose I/O
/ Timer B channel 0

General purpose I/O
/ Timer B channel 3

General purpose I/O
/ Timer B channel 2

General purpose I/O
/ Timer A channel 3

General purpose I/O
/ Timer A channel 2

General purpose I/O with
key wakeup feature

General purpose I/O with
key wakeup feature

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Dual State Yes Input (Hi-Z)

Logical chip power supply NA NA NA
Logical chip ground NA NA NA
Analog power supply (CGM) NA NA NA
Analog ground (CGM) NA NA NA

V

REFH

A

VSS/VREFL

V

DDAREF

ADC reference voltage NA NA NA
ADC ground and reference

voltage

NA NA NA

ADC power supply NA NA NA
OSC1 External clock in NA NA Input (Hi-Z)
OSC2 External clock out NA NA Output
CGMXFC PLL loop filter cap NA NA NA
IRQ External interrupt request NA NA Input (pullup)
RST Reset NA NA Input (pullup)

Details of the clock connections to each of the modules on the
MC68HC908AB32 are shown in Table 1-2. A short description of each
clock source is also given in Table 1-3.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA General Description 39

General Description

1.8 Signal Name Conventions

Signal name Description

CGMXCLK Buffered version of OSC1 from clock generator module (CGM)

CGMOUT PLL-based or OSC1-based clock output from CGM module)

Bus clock CGMOUT divided by two

Table 1-2. Signal Name Conventions

1.9 Clock Source Summary

SPSCK

TACLK

TBCLK

SPI serial clock
(see 16.13.3 SPSCK (Serial Clock))

External clock input for TIMA
(see 11.9.1 TIMA Clock Pin)

External clock input for TIMB
(see 12.9.1 TIMB Clock Pin)

Table 1-3. Clock Source Summary

Module Clock Source

ADC CGMXCLK or bus clock
COP CGMXCLK
CPU Bus clock

EEPROM CGMXCLK or bus clock

ROM Bus clock
RAM Bus clock

SPI SPSCK

SCI CGMXCLK
TIMA Bus clock or PTD6/TACLK
TIMB Bus clock or PTD4/TBCLK

PIT Bus clock

KBI Bus clock

Technical Data MC68HC908AB32 — Rev. 1.0

40 General Description MOTOROLA

Technical Data — MC68HC908AB32

2.1 Contents

2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .41

2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.2 Introduction

The CPU08 can address 64K-bytes of memory space. The memory
map, shown in Figure 2-1, includes:

Section 2. Memory Map

• 32, 256 bytes of user FLASH memory

• 512 bytes of EEPROM

• 1024 bytes of random-access memory (RAM)

• 48 bytes of user-defined vectors

• 307 bytes of monitor ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map
(Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 41

Memory Map

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page
$0000–$004F. Additional I/O registers have the following addresses:

• $FE00; SIM break status register, SBSR

• $FE01; SIM reset status register, SRSR

• $FE03; SIM break flag control register, SBFCR

• $FE08; FLASH control register, FLCR

• $FE0C; break address register high, BRKH

• $FE0D; break address register low, BRKL

• $FE0E; break status and control register, BRKSCR

• $FE0F; LVI status register, LVISR

• $FE10; EEPROM divider non-volatile register high, EEDIVHNVR

• $FE11; EEPROM divider non-volatile register low, EEDIVLNVR

• $FE1A; EEPROM timebase divider register high, EEDIVH

• $FE1B; EEPROM timebase divider register low, EEDIVL

• $FE1C; EEPROM non-volatile register, EENVR

• $FE1D; EEPROM control register, EECR

• $FE1F; EEPROM array configuration register, EEACR

• $FF7E; FLASH block protect register, FLBPR

• $FFFF; COP control register, COPCTL

Data registers are shown in Figure 2-2, Table 2-1 is a list of vector
locations.

Technical Data MC68HC908AB32 — Rev. 1.0

42 Memory Map MOTOROLA

$0000

↓

$004F
$0050

↓

$044F
$0450

↓

$04FF

$0500

↓

$057F
$0580

↓

$07FF

Memory Map

Input/Output (I/O) Section

I/O Registers

80 Bytes

RAM

1,024 Bytes

Unimplemented

176 Bytes

Reserved

128 Bytes

Unimplemented

640 Bytes

$0800

↓

$09FF
$0A00

↓

$7FFF

$8000

↓

$FDFF
$FE00 SIM Break Status Register (SBSR)
$FE01 SIM Reset Status Register (SRSR)
$FE02 Reserved
$FE03 SIM Break Flag Control Register (SBFCR)
$FE04

↓

$FE07
$FE08 FLASH Control Register (FLCR)

EEPROM
512 Bytes

Unimplemented

30,208 Bytes

FLASH Memory

32,256 Bytes

Reserved

4 Bytes

Figure 2-1. Memory Map

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 43

Memory Map

$FE09

↓

$FE0B
$FE0C Break Address Register High (BRKH)
$FE0D Break Address Register Low (BRKL)
$FE0E Break Status and Control Register (BRKSCR)
$FE0F LVI Status Register (LVISR)
$FE10 EEPROM Divider Non-volatile Register High (EEDIVHNVR)
$FE11 EEPROM Divider Non-volatile Register Low (EEDIVLNVR)
$FE12

↓

$FE19
$FE1A EEPROM Timebase Divider Register High (EEDIVH)
$FE1B EEPROM Timebase Divider Register Low (EEDIVL)
$FE1C EEPROM Non-volatile Register (EENVR)
$FE1D EEPROM Control Register (EECR)
$FE1E Reserved
$FE1F EEPROM Array Configuration Register (EEACR)
$FE20

↓

$FF52

Reserved

3 Bytes

Reserved

8 Bytes

Monitor ROM

307 Bytes

$FF53

↓

$FF7D
$FF7E FLASH Block Protect Register (FLBPR)
$FF7F

↓

$FFBF
$FFC0

↓

$FFCF
$FFD0

↓

$FFFF

Reserved for Compatibility with HC08AB16/24/32

Unimplemented

43 Bytes

Unimplemented

65 Bytes

Reserved FLASH Memory

16 Bytes

FLASH Vectors

48 Bytes

Figure 2-1. Memory Map (Continued)

Technical Data MC68HC908AB32 — Rev. 1.0

44 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

$0000

$0001

$0002

$0003

$0004

$0005

Read:

Port A Data Register

Port B Data Register

Port C Data Register

Port D Data Register

Data Direction Register A

(DDRA)

Data Direction Register B

(DDRB)

Write:

(PTA)

Reset: Unaffected by reset

Read:

Write:

(PTB)

Reset: Unaffected by reset

Read: 0 0

Write:

(PTC)

Reset: Unaffected by reset

Read:

Write:

(PTD)

Reset: Unaffected by reset

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0

PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

$0006

$0007

$0008

$0009

Read:

Data Direction Register C

(DDRC)

Data Direction Register D

(DDRD)

Port E Data Register

Port F Data Register

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read:

Write:

(PTE)

Reset: Unaffected by reset

Read:

Write:

(PTF)

Reset: Unaffected by reset

MCLKEN

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0

PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0

0

DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 11)

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 45

Memory Map

Addr. Register Name Bit 7 654321Bit 0

Read: 00000

$000A

$000B

$000C

$000D

$000E

$000F

Port G Data Register

Port H Data Register

Data Direction Register E

(DDRE)

Data Direction Register F

(DDRF)

Data Direction Register G

(DDRG)

Data Direction Register H

(DDRH)

Write:

(PTG)

Reset: Unaffected by reset

Read: 000000

Write:

(PTH)

Reset: Unaffected by reset

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read: 00000

Write:

Reset: 00000000

Read: 000000

Write:

Reset: 00000000

DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0

DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

PTG2 PTG1 PTG0

PTH1 PTH0

DDRG2 DDRG1 DDRG0

DDRH1 DDRH0

$0010

$0011

$0012

$0013

Read:

SPI Control Register

(SPCR)

SPI Status and Control

Register

(SPSCR)

SPI Data Register

(SPDR)

SCI Control Register 1

(SCC1)

Write:

Reset: 00101000

Read: SPRF

Write:

Reset: 00001000

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

Read:

Write:

Reset: 00000000

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 11)

SPRIE R SPMSTR CPOL CPHA SPWOM SPE

ERRIE

LOOPS ENSCI TXINV M WAKE ILTY PEN PTY

= Unimplemented R = Reserved

OVRF MODF SPTE

MODFEN SPR1 SPR0

SPTIE

Technical Data MC68HC908AB32 — Rev. 1.0

46 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

$0014

$0015

$0016

$0017

$0018

$0019

Read:

SCI Control Register 2

(SCC2)

SCI Control Register 3

(SCC3)

SCI Status Register 1

(SCS1)

SCI Status Register 2

(SCS2)

SCI Data Register

(SCDR)

SCI Baud Rate Register

(SCBR)

Write:

Reset: 00000000

Read: R8

Write:

Reset:

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset: 11000000

Read: 000000BKFRPF

Write:

Reset: 00000000

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by reset

Read: 0 0

Write:

Reset: 00000000

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

T8 R R ORIE NEIE FEIE PEIE

Unaffected Unaffected

000000

SCP1 SCP0 R SCR2 SCR1 SCR0

$001A

$001B

$001C

$001D

IRQ Status and Control

Register

(ISCR)

Keyboard Status and

Control Register

(KBSCR)

PLL Control Register

(PCTL)

PLL Bandwidth Control

Register

(PBWC)

Read: 0000IRQF 0

Write: ACK

Reset: 00000000

Read: 0000KEYF 0

Write: ACKK

Reset: 00000000

Read:

Write:

Reset: 00101111

Read:

Write:

Reset: 00000000

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 11)

PLLIE

AUTO

PLLF

PLLON BCS

LOCK

ACQ XLD

= Unimplemented R = Reserved

1111

0000

IMASK MODE

IMASKK MODEK

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 47

Memory Map

Addr. Register Name Bit 7 654321Bit 0

PLL Programming

$001E

$001F

† One-time writable register after each reset.

$0020

$0021

$0022

Configuration Register 1

Timer A Status and

Keyboard Interrupt Enable

Register

(CONFIG1)

Control Register

(TASC)

Register

(KBIER)

Timer A Counter

Register High

(TACNTH)

Timer A Counter

$0023

Register Low

(TACNTL)

Read:

Write:

(PPG)

Reset: 01100110

Read:

Write:

†

Reset: 00000000

Read: TOF

Write: 0 TRST

Reset: 00100000

Read: 0 0 0

Write:

Reset: 00000000

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 00000000

Read: Bit 7 654321Bit 0

Write:

Reset: 00000000

MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4

LVISTOP R LVIRSTD LVIPWRD SSREC COPRS STOP COPD

TOIE TSTOP

00

PS2 PS1 PS0

KBIE4 KBIE3 KBIE2 KBIE1 KBIE0

Timer A Counter Modulo

$0024

Timer A Counter Modulo

$0025

Timer A Channel 0 Status

$0026

$0027

Register High

Register Low

and Control Register

Timer A Channel 0

Register High

(TAMODH)

(TAMODL)

(TASC0)

(TACH0H)

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 11111111

Read:

Bit 7 654321Bit 0

Write:

Reset: 11111111

Read: CH0F

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset: 00000000

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 11)

Technical Data MC68HC908AB32 — Rev. 1.0

48 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

$0028

$0029

$002A

$002B

$002C

$002D

Timer A Channel 0

Register Low

(TACH0L)

Timer A Channel 1 Status

and Control Register

(TASC1)

Timer A Channel 1

Register High

(TACH1H)

Timer A Channel 1

Register Low

(TACH1L)

Timer A Channel 2 Status

and Control Register

(TASC2)

Timer A Channel 2

Register High

(TACH2H)

Read:

Write:

Reset: Indeterminate after reset

Read: CH1F

Write: 0

Reset: 00000000

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Read: CH2F

Write: 0

Reset: 00000000

Read:

Write:

Reset: Indeterminate after reset

Bit 7 654321Bit 0

CH1IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX

Bit 15 14 13 12 11 10 9 Bit 8

0

MS1A ELS1B ELS1A TOV1 CH1MAX

Timer A Channel 2

$002E

Timer A Channel 3 Status

$002F

$0030

$0031

Register Low

and Control Register

Timer A Channel 3

Register High

Timer A Channel 3

Register Low

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 11)

(TACH2L)

(TASC3)

(TACH3H)

(TACH3L)

Read:

Write:

Reset: Indeterminate after reset

Read: CH3F

Write: 0

Reset: 00000000

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Bit 7 654321Bit 0

CH3IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

= Unimplemented R = Reserved

0

MS3A ELS3B ELS3A TOV3 CH3MAX

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 49

Memory Map

Addr. Register Name Bit 7 654321Bit 0

Timer B Channel 2 Status

$0032

$0033

$0034

$0035

$0036

$0037

and Control Register

(TBSC2)

Timer B Channel 2

Register High

(TBCH2H)

Timer B Channel 2

Register Low

(TBCH2L)

Timer B Channel 3 Status

and Control Register

(TBSC3)

Timer B Channel 3

Register High

(TACH3H)

Timer B Channel 3

Register Low

(TBCH3L)

Read: CH2F

Write: 0

Reset: 00000000

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Read:

Bit 7 654321Bit 0

Write:

Reset: Indeterminate after reset

Read: CH3F

Write: 0

Reset: 00000000

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: Indeterminate after reset

Read:

Bit 7 654321Bit 0

Write:

Reset: Indeterminate after reset

CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX

CH3IE

0

MS3A ELS3B ELS3A TOV3 CH3MAX

Analog-to-Digital Status

$0038

$0039

$003A

$003B Reserved

and Control Register

(ADSCR)

Analog-to-Digital Data

Register

(ADR)

Analog-to-Digital Clock

Register

(ADCLK)

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 11)

Read:

Write:

Reset: 00011111

Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read:

Write:

Reset:

COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0

0000

ADIV2 ADIV1 ADIV0 ADICLK

RRRRRRRR

= Unimplemented R = Reserved

Technical Data MC68HC908AB32 — Rev. 1.0

50 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

Read:

$003C Reserved

Port D Input Pullup Enable

$003D

Port F Input Pullup Enable

$003E

$003F

† One-time writable register after each reset.

$0040

$0041

Configuration Register 2

Timer B Status and

Register

(PTDPUE)

Register

(PTFPUE)

(CONFIG2)

Control Register

(TBSC)

Timer B Counter

Register High

(TBCNTH)

Write:

Reset:

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read:

Write:

†

Reset: 0

Read: TOF

Write: 0 TRST

Reset: 00100000

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 00000000

RRRRRRRR

PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

PTFPUE7 PTFPUE6 PTFPUE5 PTFPUE4 PTFPUE3 PTFPUE2 PTFPUE1 PTFPUE0

R

EEDIVCLK

TOIE TSTOP

RRRRRR

00

PS2 PS1 PS0

Timer B Counter

$0042

Timer B Counter Modulo

$0043

Timer B Counter Modulo

$0044

Timer B Channel 0 Status

$0045

Register Low

Register High

Register Low

and Control Register

(TBCNTL)

(TBMODH)

(TBMODL)

(TBSC0)

Read: Bit 7 654321Bit 0

Write:

Reset: 00000000

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 11111111

Read:

Bit 7 654321Bit 0

Write:

Reset: 11111111

Read: CH0F

CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX

Write: 0

Reset: 00000000

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 11)

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 51

Memory Map

Addr. Register Name Bit 7 654321Bit 0

Timer B Channel 0

$0046

$0047

Timer B Channel 1 Status

$0048

$0049

$004A

$004B

PIT Status and Control

Register High

(TBCH0H)

Timer B Channel 0

Register Low

(TBCH0L)

and Control Register

(TBSC1)

Timer B Channel 1

Register High

(TBCH1H)

Timer B Channel 1

Register Low

(TBCH1L)

Register

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Read: CH1F

Write: 0

Reset: 00000000

Read:

Write:

Reset: Indeterminate after reset

Read:

Write:

Reset: Indeterminate after reset

Read: POF

Write: 0 PRST

(PSC)

Reset: 00100000

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

CH1IE

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

POIE PSTOP

0

MS1A ELS1B ELS1A TOV1 CH1MAX

00

PPS2 PPS1 PPS0

PIT Counter Register High

$004C

PIT Counter Register Low

$004D

PIT Counter Modulo

$004E

$004F

Register High

PIT Counter Modulo

Register Low

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 11)

(PCNTH)

(PCNTL)

(PMODH)

(PMODL)

Read: Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 00000000

Read: Bit 7 654321Bit 0

Write:

Reset: 00000000

Read:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset: 11111111

Read:

Bit 7 654321Bit 0

Write:

Reset: 11111111

= Unimplemented R = Reserved

Technical Data MC68HC908AB32 — Rev. 1.0

52 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

Read:

SIM Break Status Register

$FE00

Note: Writing a logic 0 clears SBSW.

SIM Reset Status Register

$FE01

$FE02 Reserved

SIM Break Flag Control

$FE03

$FE04 Reserved

$FE05 Reserved

(SBSR)

(SRSR)

Register

(SBFCR)

Write: Note

Reset: 00000000

Read: POR PIN COP ILOP ILAD 0 LVI 0

Write:

POR: 10000000

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 0

Read:

Write:

Reset:

Read:

Write:

RRRRRR

RRRRRRRR

BCFE RRRRRRR

RRRRRRRR

SBSW

R

RRRRRRRR

$FE06 Reserved

$FE07 Reserved

$FE08

$FE09 Reserved

FLASH Control Register

(FLCR)

Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 11)

Reset:

Read:

RRRRRRRR

Write:

Reset:

Read:

RRRRRRRR

Write:

Reset:

Read: 0000

HVEN MASS ERASE PGM

Write:

Reset: 00000000

Read:

RRRRRRRR

Write:

Reset:

= Unimplemented R = Reserved

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 53

Memory Map

Addr. Register Name Bit 7 654321Bit 0

$FE0A Reserved

$FE0B Reserved

Break Address Register

$FE0C

Break Address Register

$FE0D

Break Status and Control

$FE0E

Low-Voltage Inhibit Status

$FE0F

High

(BRKH)

Low

(BRKL)

Register

(BRKSCR)

Register

(LVISR)

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read:

Write:

Reset: 00000000

Read: LVIOUT 0000000

Write:

Reset: 00000000

RRRRRRRR

RRRRRRRR

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

000000

BRKE BRKA

EEDIV Non-volatile

$FE10

$FE11

* Non-volatile FLASH register; write by programming.

$FE1A

$FE1B

EE Divider Register High

EE Divider Register Low

Register High

(EEDIVHNVR)*

EEDIV Non-volatile

Register Low

(EEDIVLNVR)*

(EEDIVH)

(EEDIVL)

Read:

EEDIVSECD

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIVSECD

Write:

Reset: Contents of EEDIVHNVR ($FE10)

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Contents of EEDIVLNVR ($FE11)

RRRREEDIV10 EEDIV9 EEDIV8

RRRREEDIV10 EEDIV9 EEDIV8

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 11)

Technical Data MC68HC908AB32 — Rev. 1.0

54 Memory Map MOTOROLA

Memory Map

Input/Output (I/O) Section

Addr. Register Name Bit 7 654321Bit 0

EEPROM Non-volatile

$FE1C

EEPROM Control Register

$FE1D

$FE1E Reserved

$FE1F

$FF7E

* Non-volatile FLASH register; write by programming.

Configuration Register

FLASH Block Protect

Register (FLBPR)*

Register

(EENVR)*

(EECR)

EEPROM Array

(EEACR)

Read:

Write:

Reset: Unaffected by reset; $FF when blank

Read:

Write:

Reset: 00000000

Read:

Write:

Reset:

Read: CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

Write:

Reset: Contents of EENVR ($FE1C)

Read:

Write:

Reset: Unaffected by reset

CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

0

EEDUM

RRRRRRRR

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

$FFFF

Read: Low byte of reset vector

COP Control Register

(COPCTL)

Write: Writing clears COP counter (any value)

Reset: Unaffected by reset

= Unimplemented R = Reserved

Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 11)

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Memory Map 55

Memory Map

Table 2-1. Vector Addresses

Vector Priority Address Vector

Lowest

Highest

$FFD0 ADC Conversion Complete Vector (High)
$FFD1 ADC Conversion Complete Vector (Low)
$FFD2 Keyboard V ector (High)
$FFD3 Keyboard V ector (Low)
$FFD4 SCI T ransmit Vector (High)
$FFD5 SCI T ransmit Vector (Low)
$FFD6 SCI Receive Vector (High)
$FFD7 SCI Receive Vector (Low)
$FFD8 SCI Error Vector (High)
$FFD9 SCI Error Vector (Low)

$FFDA Reserved
$FFDB Reserved
$FFDC Reserved
$FFDD Reserved
$FFDE Timer B Channel 3 Vector (High)
$FFDF Timer B Channel 3 Vector (Low)
$FFE0 Timer B Channel 2 Vector (High)
$FFE1 Timer B Channel 2 Vector (Low)
$FFE2 SPI Tr ansmit V ector (High)
$FFE3 SPI Tr ansmit V ector (Low)
$FFE4 SPI Receive Vector (High)
$FFE5 SPI Receive Vector (Low)
$FFE6 Timer B Overflow Vector (High)
$FFE7 Timer B Overflow Vector (Low)
$FFE8 Timer B Channel 1 Vector (High)
$FFE9 Timer B Channel 1 Vector (Low)
$FFEA Timer B Channel 0 Vector (High)
$FFEB Timer B Channel 0 Vector (Low)
$FFEC Timer A Overflow Vector (High)
$FFED Timer A Overflow Vector (Low)
$FFEE Timer A Channel 3 Vector (High)
$FFEF Timer A Channel 3 Vector (Low)

$FFF0 Timer A Channel 2 Vector (High)

$FFF1 Timer A Channel 2 Vector (Low)

$FFF2 Timer A Channel 1 Vector (High)

$FFF3 Timer A Channel 1 Vector (Low)

$FFF4 Timer A Channel 0 Vector (High)

$FFF5 Timer A Channel 0 Vector (Low)

$FFF6 Programmable Interrupt Timer (High)

$FFF7 Programmable Interrupt Timer (Low)

$FFF8 PLL Vector (High)

$FFF9 PLL Vector (Low)

$FFFA IRQ Vector (High)
$FFFB IRQ Vector (Low)
$FFFC SWI V ector (High)
$FFFD SWI V ector (Low)
$FFFE Reset Vector (High)

$FFFF Reset Vector (Low)

Technical Data MC68HC908AB32 — Rev. 1.0

56 Memory Map MOTOROLA

Technical Data — MC68HC908AB32

Section 3. Random-Access Memory (RAM)

3.1 Contents

3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

3.2 Introduction

This section describes the 1024 bytes of RAM (random-access
memory).

3.3 Functional Description

Addresses $0050 through $044F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K-byte memory space.

NOTE:

For correct operation, the stack pointer must point only to RAM
locations.

Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.

NOTE:

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Random-Access Memory (RAM) 57

For M6805 compatibility, the H register is not stacked.

Random-Access Memory (RAM)

During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.

NOTE:

Be careful when using nested subroutines. The CPU may overwrite
data in the RAM during a subroutine or during the interrupt stacking
operation.

Technical Data MC68HC908AB32 — Rev. 1.0

58 Random-Access Memory (RAM) MOTOROLA

Technical Data — MC68HC908AB32

4.1 Contents

4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.4 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .61

4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .62

4.7 FLASH Program/Read Operation. . . . . . . . . . . . . . . . . . . . . . .63

4.8 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.8.1 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . .66

Section 4. FLASH Memory

4.9 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.2 Introduction

This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.

4.3 Functional Description

The FLASH memory is an array of 32,256 bytes with an additional 48
bytes of user vectors and one byte of block protection.

reads as logic 1 and a programmed bit reads as a logic 0

FLASH array is organized into two rows per page basis. For the 32K
word by 8-Bit Embedded FLASH Memory, the page size is 128 bytes per

An erased bit

. Memory in the

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA FLASH Memory 59

FLASH Memory

page. Hence the minimum erase page size is 128 bytes. Program and
erase operations are facilitated through control bits in the FLASH Control
Register (FLCR). Details for these operations appear later in this
section. The address ranges for the user memory and vectors are:

• $8000–$FDFF; user memory.

• $FF7E; FLASH block protect register.

Programming tools are available from Motorola. Contact your local
Motorola representative for more information.

NOTE:

A security feature prevents viewing of the FLASH contents.

4.4 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase
operations.

Address: $FE08

Read: 0000

Write:

Reset: 00000000

• $FE08

;

FLASH control register.

• $FFDC–$FFFF; these locations are reserved for user-defined
interrupt and reset vectors.

1

Bit 7 654321Bit 0

HVEN MASS ERASE PGM

Figure 4-1. FLASH Control Register (FLCR)

HVEN — High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.

1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.

Technical Data MC68HC908AB32 — Rev. 1.0

60 FLASH Memory MOTOROLA

FLASH Memory

FLASH Page Erase Operation

MASS — Mass Erase Control Bit

Setting this read/write bit configures the 32K-byte FLASH array for
mass erase operation.

1 = MASS erase operation selected
0 = MASS erase operation unselected

ERASE — Erase Control Bit

This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.

1 = Erase operation selected
0 = Erase operation unselected

PGM — Program Control Bit

This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.

1 = Program operation selected
0 = Program operation unselected

4.5 FLASH Page Erase Operation

Use this step-by-step procedure to erase a page (128 bytes) of FLASH
memory to read as logic 1:

1. Set the ERASE bit, and clear the MASS bit in the FLASH control
register.

2. Read the FLASH block protect register.

3. Write any data to any FLASH address within the page address
range desired.

4. Wait for a time, t

5. Set the HVEN bit.

6. Wait for a time, t

7. Clear the ERASE bit.

8. Wait for a time, t

(min. 10µs)

nvs

(min. 1ms)

Erase

(min. 5µs)

nvh

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA FLASH Memory 61

FLASH Memory

9. Clear the HVEN bit.

10. After a time, t
read mode.

NOTE:

While these operations must be performed in the order shown, other
unrelated operations may occur between the steps.

4.6 FLASH Mass Erase Operation

Use this step-by-step procedure to erase entire FLASH memory to read
as logic 1:

1. Set both the ERASE bit, and the MASS bit in the FLASH control
register.

2. Read from the FLASH block protect register.

3. Write any data to any FLASH address* within the FLASH memory
address range.

4. Wait for a time, t

(typ. 1µs), the memory can be accessed again in

rcv

(min. 10µs)

nvs

NOTE:

5. Set the HVEN bit.

6. Wait for a time, t

MErase

(min. 4ms)

7. Clear the ERASE bit.

8. Wait for a time, t

(min. 100µs)

nvhl

9. Clear the HVEN bit.

10. After a time, t

(min. 1µs), the memory can be accessed again in

rcv

read mode.

* When in Monitor mode, with security sequence failed (see 10.5 Security), write to the FLASH
block protect register instead of any FLASH address.

Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.

Technical Data MC68HC908AB32 — Rev. 1.0

62 FLASH Memory MOTOROLA

4.7 FLASH Program/Read Operation

Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $0080 and $XXC0. Use this step-by-step procedure to program
a row of FLASH memory (Figure 4-2 is a flowchart representation):

FLASH Memory

FLASH Program/Read Operation

NOTE:

In order to avoid program disturbs, the row must be erased before any
byte on that row is programmed.

1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.

2. Read from the FLASH block protect register.

3. Write any data to any FLASH address within the row address
range desired.

4. Wait for a time, t

(min. 10µs).

nvs

5. Set the HVEN bit.

6. Wait for a time, t

(min. 5µs).

pgs

7. Write data to the FLASH address to be programmed.*

8. Wait for a time, t

(min. 30µs).

PROG

9. Repeat step 7 and 8 until all the bytes within the row are
programmed.

10. Clear the PGM bit.*

11. Wait for a time, t

(min. 5µs).

nvh

12. Clear the HVEN bit.

13. After time, t

(min. 1µs), the memory can be accessed in read

rcv

mode again.

* The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, t

PROG

max.

This program sequence is repeated throughout the memory until all data
is programmed.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA FLASH Memory 63

FLASH Memory

NOTE:

Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t

FLASH Memory Characteristics .

4.8 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
a block of memory from unintentional erase or program operations due
to system malfunction. This protection is done by using of a FLASH
Block Protect Register (FLBPR). The FLBPR determines the range of
the FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends at the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.

NOTE:

In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit

maximum. See 23.13

PROG

When the FLBPR is program with all 0’s, the entire memory is protected
from being programmed and erased. When all the bits are erased (all
1’s), the entire memory is accessible for program and erase.

When bits within the FLBPR are programmed, they lock a block of
memory, address ranges as shown in 4.8.1 FLASH Block Protect

Register . Once the FLBPR is programmed with a value other than $FF,

any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. The FLBPR itself can be erased or programmed
only with an external voltage, V

, present on the IRQ

TST

pin. This voltage

also allows entry from reset into the monitor mode.

Technical Data MC68HC908AB32

Rev. 1.0

—

64

FLASH Memory MOTOROLA

FLASH Memory

FLASH Block Protection

Algorithm for programming
a row (64 bytes) of FLASH memory

1

2

Read the FLASH block protect register

3

Write any data to any FLASH address

Set PGM bit

within the row address range desired

4

5

6

7

Wait for a time, t

nvs

Set HVEN bit

Wait for a time, t

pgs

Write data to the FLASH address
to be programmed

8

Wait for a time, t

PROG

Completed

programming

this row?

N

NOTE:

10

The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed

11

to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming

PROG

max.

12

time, t
This row program algorithm assumes the row/s

to be programmed are initially erased.

13

Y

Clear PGM bit

Wait for a time, t

Clear HVEN bit

Wait for a time, t

End of programming

nvh

rcv

Figure 4-2. FLASH Programming Flowchart

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA FLASH Memory 65

FLASH Memory

4.8.1 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.

Address: $FF7E

Bit 7 654321Bit 0

Read:

BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0

Write:

Reset: UUUUUUUU

U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.

Figure 4-3. FLASH Block Protect Register (FLBPR)

BPR[7:0] — FLASH Block Protect Bits

These eight bits represent bits [14:7] of a 16-bit memory address.
Bit-15 is logic 1 and bits [6:0] are logic 0s.

The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00 and XX80
(128 bytes page boundaries) within the FLASH memory.

16-bit memory address

Start address of FLASH block protect

1

FLBPR value

0000000

Figure 4-4. FLASH Block Protect Start Address

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4.9 Wait Mode

FLASH Memory

Wait Mode

Examples of protect start address:

BPR[7:0] Start of Address of Protect Range

$00 The entire FLASH memory is protected.
$01 (0000 0001) $8080 (1000 0000 1000 0000)
$02 (0000 0010) $8100 (1000 0001 0000 0000)

and so on...

$FE (1111 1110) $FF00 (1111 1111 0000 0000)

$FF The entire FLASH memory is not protected.

Note:
The end address of the protected range is always $FFFF.

4.10 Stop Mode

NOTE:

Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.

The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode.

Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.

The STOP instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode

Standby Mode is the power saving mode of the FLASH module in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.

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Technical Data MC68HC908AB32 — Rev. 1.0

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Technical Data — MC68HC908AB32

5.1 Contents

5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.5 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.6 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . . .72

5.7 EEPROM Security Options. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.8 EEPROM Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.9 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . . .73

5.9.1 EEPROM Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . .74

5.9.2 EEPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Section 5. EEPROM

5.10 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11 EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11.1 EEPROM Control Register. . . . . . . . . . . . . . . . . . . . . . . . . .77

5.11.2 EEPROM Array Configuration Register . . . . . . . . . . . . . . . .79

5.11.2.1 EEPROM Non-Volatile Register . . . . . . . . . . . . . . . . . . .80

5.11.3 EEPROM Timebase Divider Register . . . . . . . . . . . . . . . . .80

5.11.3.1 EEPROM Timebase Divider Non-Volatile Register . . . . .82

5.2 Introduction

This section describes the 512 bytes electrically erasable programmable
read-only-memory (EEPROM).

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EEPROM

5.3 Features

Features of the EEPROM include the following:

• 512 bytes non-volatile memory

• Byte, block or bulk erasable operations

• Non-volatile EEPROM configuration and block protection options

• On-chip charge pump for programming/erasing

• Security option

Addr. Register Name Bit 7 654321Bit 0

EEDIV Non-volatile

$FE10

$FE11

$FE1A

$FE1B

$FE1C

$FE1D

EE Divider Register High

EE Divider Register Low

EEPROM Non-volatile

EEPROM Control Register

Register High

(EEDIVHNVR)*

EEDIV Non-volatile

Register Low

(EEDIVLNVR)*

(EEDIVH)

(EEDIVL)

Register

(EENVR)*

(EECR)

Read:

EEDIVSECD

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Unaffected by reset; $FF when blank

Read:

EEDIVSECD

Write:

Reset: Contents of EEDIVHNVR ($FE10)

Read:
Write:

Reset: Contents of EEDIVLNVR ($FE11)

Read:
Write:

Reset: Unaffected by reset; $FF when blank; factory programmed $10

Read:
Write:

Reset: 00000000

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

EEDUM

RRRREEDIV10 EEDIV9 EEDIV8

RRRREEDIV10 EEDIV9 EEDIV8

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

EEPROM Array

$FE1F

* Non-volatile EEPROM register; write by programming.

Configuration Register

(EEACR)

Read: CON3 CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
Write:

Reset: Contents of EENVR ($FE1C)

= Unimplemented R = Reserved

Figure 5-1. EEPROM I/O Register Summary

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5.4 Functional Description

The 512 bytes of EEPROM is located at $0800–$09FF, and can be
programmed or erased without an additional external high voltage
supply. The program and erase operations are enabled through the use
of an internal charge pump. For each byte of EEPROM, the write/erase
endurance is 10,000 cycles.

5.5 EEPROM Configuration

The 8-bit EEPROM non-volatile register (EENVR) and the 16-bit
EEPROM timebase divider non-volatile register (EEDIVNVR) contain
the default settings for the following EEPROM configurations:

• Security option

EEPROM

Functional Description

• Block protection

• EEPROM timebase reference

EENVR and EEDIVNVR are non-volatile, EEPROM registers. They are
programmed and erased in the same way as EEPROM bytes. The
contents of these registers are loaded into their respective volatile
registers during a MCU reset. The values in these read/write, volatile
registers define the EEPROM configurations.

For EENVR, the corresponding volatile register is the EEPROM array
configuration register (EEACR).

For the EEDIVNVR (two 8-bit registers: EEDIVHNVR and EEDIVLNVR),
the corresponding volatile register is the EEPROM timebase divider
register (EEDIV: EEDIVH and EEDIVL)

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EEPROM

5.6 EEPROM Timebase Requirements

A 35µs timebase is required by the EEPROM control circuit for program
and erase of EEPROM content. This timebase is derived from dividing
the CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG2
register) using a timebase divider circuit, controlled by the 16-bit
EEPROM timebase divider register (EEDIVH and EEDIVL).

As the CGMXCLK or bus clock is user selected, the EEPROM timebase
divider register must be configured with the appropriate value to obtain
the 35µs. The timebase divider is calculated using the following formula:

This value is written to the EEPROM timebase divider register (EEDIVH
and EEDIVL) or programmed into the EEPROM timebase divider non­volatile register prior to any EEPROM program or erase operations (see

5.5 EEPROM Configuration and 5.11.3.1 EEPROM Timebase Divider
Non-Volatile Register).

5.7 EEPROM Security Options

The EEPROM has a special security option, enabled by programming
the EEPRTCT bit to 0 in the EEPROM non-volatile register (EENVR).
Once security is enabled, the following limitations apply to the EEPROM:

• The 16-byte EEPROM locations from $08F0 to $08FF are

• The block erase and bulk erase modes are disabled. Byte erase

EEDIV = INT

protected from erase and program operations.

can be used for all EEPROM locations except $08F0 to $08FF.

[Reference frequency (Hz) × 35 × 10

–6

+ 0.5]

• The EENVR is protected from further erase or program
operations.

5.8 EEPROM Block Protection

The 512 bytes of EEPROM is divided into four 128-byte blocks. Each of
these blocks can be protected from erase/program operations by setting
the EEBPx bit in the EENVR. Table 5-1 shows the address ranges for
the blocks.

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Table 5-1. EEPROM Array Address Blocks

Block Number (EEBPx) Address Range

EEBP0 $0800–$087F
EEBP1 $0880–$08FF
EEBP2 $0900–$097F
EEBP3 $0980–$09FF

These bits are effective after a reset or a read to EENVR register. The
block protect configuration can be modified by erasing/programming the
corresponding bits in the EENVR register and then reading the EENVR
register.

5.9 EEPROM Programming and Erasing

EEPROM

EEPROM Programming and Erasing

NOTE:

The unprogrammed or erased state of an EEPROM bit is a logic 1. The
factory default for the EEPROM array is $FF for all bytes.

The programming operation changes an EEPROM bit from logic 1 to
logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a
single programming operation, the minimum EEPROM programming
size is zero bits; the maximum is eight bits (one byte).

The erase operation changes an EEPROM bit from logic 0 to logic 1. In
a single erase operation, the minimum EEPROM erase size is one byte;
the maximum is the entire EEPROM array.

For each EEPROM byte, the write/erase endurance is 10,000 cycles.
One write/erase cycle is defined as:

a maximum of eight programming
operations on the same byte followed by an erase operation of the that
byte

. Therefore, it is possible to program a byte, bit by bit to logic 0

before requiring an erase on that byte.

Although programming a bit (from 0 or 1) with a logic 1 does not change
the state of that bit, it is still regarded as a programming operation. That
is, if the same byte is programmed eight times (with any value), that byte
must be erased before it can be successfully programmed again.

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EEPROM

5.9.1 EEPROM Programming

The unprogrammed or erased state of an EEPROM bit is a logic 1.
Programming changes the state to a logic 0. Only EEPROM bytes in the
non-protected blocks and the EENVR register can be programmed.

Use the following procedure to program a byte of EEPROM:

1. Clear EERAS1 and EERAS0, and set EELAT in the EECR.

2. Write the desired data to the desired EEPROM address.

3. Set the EEPGM bit.

(C)

(A)

(B)

Go to step 7 if AUTO is set.

4. Wait for a time, t

EEPGM

, to program the byte.

5. Clear EEPGM bit.

6. Wait for a time, t

EEFPV

, for the programming voltage to fall.

Go to step 8.

7. Poll the EEPGM bit until it is cleared by the internal timer.

NOTE:

8. Clear EELAT bit.

A. EERAS1 and EERAS0 must be cleared for programming. Setting the

(E)

(D)

EELAT bit configures the address and data buses to latch data for
programming the array. Only data with a valid EEPROM address will be
latched. If EELAT is set, other writes to the EECR will be allowed after a
valid EEPROM write.

B. If more than one valid EEPROM writes occur, the last address and
data will be latched, overriding the previous address and data. Once
written data to the desired address, do not read EEPROM locations
other than the written location. (Reading an EEPROM location returns
the latched data, and causes the read address to be latched.)

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non­valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any EEPROM
locations, otherwise the current program cycle will be unsuccessful.
When EEPGM is set, the on-board programming sequence will be
activated.

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5.9.2 EEPROM Erasing

EEPROM

EEPROM Programming and Erasing

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t

EEPGM

. However, on other MCUs, this delay time may be different.
For forward compatibility, software should not make any dependency on
this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM array.

The programmed state of an EEPROM bit is logic 0. Erasing changes
the state to a logic 1. Only EEPROM bytes in the non-protected blocks
and EENVR register can be erased.

Use the following procedure to erase a byte, block, or the entire
EEPROM:

1. Configure EERAS1 and EERAS0 for byte, block, or bulk erase; set
EELAT in EECR.

2. Byte erase: write any data to the desired address.

(A)

(B)

Block erase: write any data to an address within the desired
block.
Bulk erase: write any data to an address within the array.

3. Set the EEPGM bit.

(B)

(B)

(C)

Go to step 7 if AUTO is set.

4. Wait for a time: t
t

EBULK

for bulk erase.

EBYTE

for byte erase; t

EBLOCK

for block erase;

5. Clear EEPGM bit.

6. Wait for a time, t

EEFPV

, for the erasing voltage to fall.

Go to step 8.

7. Poll the EEPGM bit until it is cleared by the internal timer.

8. Clear EELAT bits.

(E)

(D)

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EEPROM

NOTE:

A. Setting the EELAT bit configures the address and data buses to latch

data for erasing the array. Only valid EEPROM addresses will be
latched. If EELAT is set, other writes to the EECR will be allowed after a
valid EEPROM write.

B. If more than one valid EEPROM writes occur, the last address and
data will be latched, overriding the previous address and data. Once
written data to the desired address, do not read EEPROM locations
other than the written location. (Reading an EEPROM location returns
the latched data, and causes the read address to be latched.)
EENVR is not affected by block or bulk erase.

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non­valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any EEPROM
locations, otherwise the current erase cycle will be unsuccessful. When
EEPGM is set, the erase mode cannot be changed, and the on-board
erasing sequence will be activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t

EBYTE

/ t

EBLOCK

/ t

EBULK

. However, on other MCUs, this delay time
may be different. For forward compatibility, software should not make
any dependency on this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM array.

5.10 Low Power Modes

The WAIT and STOP instructions can put the MCU in low power
consumption standby modes.

5.10.1 Wait Mode

The WAIT instruction does not affect the EEPROM. It is possible to start
the program or erase sequence on the EEPROM and put the MCU in
wait mode.

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5.10.2 Stop Mode

EEPROM

EEPROM Registers

The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while the
programming and erasing sequence is in progress.

If stop mode is entered while EELAT and EEPGM is set, the
programming sequence will be stopped and the programming voltage to
the EEPROM array removed. The programming sequence will be
restarted after leaving stop mode; access to the EEPROM is only
possible after the programming sequence has completed.

If stop mode is entered while EELAT and EEPGM is cleared, the
programming sequence will be terminated abruptly.

In either case, the data integrity of the EEPROM is not guaranteed.

5.11 EEPROM Registers

Four I/O registers and three non-volatile registers control program,
erase, and options of the EEPROM array.

5.11.1 EEPROM Control Register

This read/write register controls programming/erasing of the EEPROM
array.

Address: $FE1D

Bit 7 654321Bit 0

Read:

EEDUM

Write:

Reset: 00000000

EEDUM — Dummy Bit

0

EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM

Figure 5-2. EEPROM Control Register (EECR)

This read/write bit has no function.

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EEPROM

EEOFF — EEPROM Power-Off

This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.

1 = Disable EEPROM array
0 = Enable EEPROM array

EERAS[1:0] — Erase/Program Mode Select Bits

These read/write bits set the erase modes. Reset clears these bits.

Table 5-2. EEPROM Program/Erase Mode Select

EEBPx EERAS1 EERAS0 Mode

0 0 0 Byte Program
0 0 1 Byte Erase
0 1 0 Block Erase
0 1 1 Bulk Erase
1 X X No Erase/Program

X = don’t care

EELAT — EEPROM Latch Control

This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT can not be cleared if
EEPGM is still set. Reset clears this bit.

1 = Buses configured for EEPROM program or erase operation
0 = Buses configured for normal operation

AUTO — Automatic termination of program/erase cycle

When AUTO is set, EEPGM is cleared automatically after the
program/erase cycle is terminated by the internal timer.
(See note D for 5.9.1 EEPROM Programming and 5.9.2 EEPROM

Erasing.)

0 = Automatic clear of EEPGM is disabled
1 = Automatic clear of EEPGM is enabled

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EEPROM

EEPROM Registers

EEPGM — EEPROM Program/Erase Enable

This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.

1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off

NOTE:

Writing 0s to both the EELAT and EEPGM bits with a single instruction
will only clear EEPGM. This is to allow time for the removal of high
voltage.

5.11.2 EEPROM Array Configuration Register

The EEPROM array configuration register configures EEPROM security
and EEPROM block protection.

This read-only register is loaded with the contents of the EEPROM non­volatile register (EENVR) after a reset.

Address: $FE1F

Bit 7 654321Bit 0

Read: CON3 CON2 CON1

Write:

Reset: Contents of EENVR ($FE1C)

Figure 5-3. EEPROM Array Configuration Register (EEACR)

EEPRTCT

EEBP3 EEBP2 EEBP1 EEBP0

CON[3:1] — Unused
EEPRTCT — EEPROM Protection Bit

The EEPRTCT bit is used to enable the security feature in the
EEPROM (see 5.7 EEPROM Security Options).

1 = EEPROM security disabled
0 = EEPROM security enabled

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EEPROM

EEBP[3:0] — EEPROM Block Protection Bits

These bits prevent blocks of EEPROM array from being programmed
or erased.

1 = EEPROM array block is protected
0 = EEPROM array block is unprotected

Block Number (EEBPx) Address Range

5.11.2.1 EEPROM Non-Volatile Register

The contents of this register is loaded into the EEPROM array
configuration register (EEACR) after a reset.

EEBP0 $0800–$087F
EEBP1 $0880–$08FF
EEBP2 $0900–$097F
EEBP3 $0980–$09FF

This register is erased and programmed in the same way as an
EEPROM byte.

Address: $FE1C

Bit 7 654321Bit 0

Read:

CON3 CON2 CON1

Write:

Reset: Unaffected by reset; $FF when blank; factory programmed $10

Note: Non-volatile EEPROM register; write by programming.

Figure 5-4. EEPROM Non-Volatile Register (EENVR)

NOTE:

The EENVR is factory programmed with $10.

5.11.3 EEPROM Timebase Divider Register

The 16-bit EEPROM timebase divider register consists of two 8-bit
registers: EEDIVH and EEDIVL. The 11-bit value in this register is used
to configure the timebase divider circuit to obtain the 35µs timebase for
EEPROM control.

EEPRTCT

EEBP3 EEBP2 EEBP1 EEBP0

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80 EEPROM MOTOROLA

EEPROM

EEPROM Registers

These two read/write registers are respectively loaded with the contents
of the EEPROM timebase divider non-volatile registers (EEDIVHNVR
and EEDIVLNVR) after a reset.

Address: $FE1A

Bit 7 654321Bit 0

Read:

EEDIVSECD

Write:

Reset: Contents of EEDIVHNVR ($FE10)

RRRREEDIV10 EEDIV9 EEDIV8

Figure 5-5. EEPROM Divider Register High (EEDIVH)

Address: $FE1B

Bit 7 654321Bit 0

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Contents of EEDIVLNVR ($FE11)

Figure 5-6. EEPROM Divider Register Low (EEDIVL)

EEDIVSECD — EEPROM Divider Security Disable

This bit enables/disables the security feature of the EEDIV registers.
When EEDIV security feature is enabled, the state of the registers
EEDIVH and EEDIVL are locked (including this EEDIVSECD bit). The
EEDIVHNVR and EEDIVLNVR non-volatile memory registers are
also protected from being erased/programmed.

1 = EEDIV security feature disabled
0 = EEDIV security feature enabled

EEDIV[10:0] — EEPROM Timebase Prescaler

These prescaler bits store the value of EEDIV which is used as the
divisor to derive a timebase of 35µs from the selected reference clock
source (CGMXCLK or bus clock, see 6.5 Configuration Register 2)
for the EEPROM related internal timer and circuits. EEDIV[10:0] bits
are readable at any time. They are writable when EELAT=0 and
EEDIVSECD=1.

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EEPROM

The EEDIV value is calculated by the following formula:

EEDIV = INT

[Reference frequency (Hz) × 35 × 10

Where the result inside the bracket is rounded down to the nearest
integer value.

For example, if the reference frequency is 4.9152MHz, the EEDIV
value is 172.

NOTE:

Programming/erasing the EEPROM with an improper EEDIV value may
result in data lost and reduce endurance of the EEPROM device.

5.11.3.1 EEPROM Timebase Divider Non-Volatile Register

The 16-bit EEPROM timebase divider non-volatile register consists of
two 8-bit registers: EEDIVHNVR and EEDIVLNVR. The contents of
these two registers are respectively loaded into the EEPROM timebase
divider registers, EEDIVH and EEDIVL, after a reset.

These two registers are erased and programmed in the same way as an
EEPROM byte.

–6

+ 0.5]

Address: $FE10

Bit 7 654321Bit 0

Read:

EEDIVSECD

Write:

Reset: Unaffected by reset; $FF when blank

RRRREEDIV10 EEDIV9 EEDIV8

Figure 5-7. EEPROM Divider Non-volatile Register High(EEDIVHNVR)

Address: $FE11

Bit 7 654321Bit 0

Read:

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset: Unaffected by reset; $FF when blank

Figure 5-8. EEPROM Divider Non-volatile Register Low (EEDIVLNVR)

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EEPROM

EEPROM Registers

These two registers are protected from erase and program operations if
the EEDIVSECD is set to logic 1 in the EEDIVH (see 5.11.3 EEPROM

Timebase Divider Register), or programmed to a logic 1 in the

EEDIVHNVR.

NOTE:

Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a
system reset, the EEDIV security feature is permanently enabled
because the EEDIVSECD bit in the EEDIVH is always loaded with a 0
thereafter. Once this security feature is armed, erase and program
operations are disabled for EEDIVHNVR and EEDIVLNVR.
Modifications to the EEDIVH and EEDIVL registers are also disabled.
Therefore, care should be taken before programming a value into the
EEDIVHNVR.

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Technical Data MC68HC908AB32 — Rev. 1.0

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Technical Data — MC68HC908AB32

Section 6. Configuration Register (CONFIG)

6.1 Contents

6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

6.3 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

6.4 Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

6.5 Configuration Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

6.2 Introduction

This section describes the configuration registers, CONFIG1 and
CONFIG2. The configuration registers enable or disable these options:

• Low-voltage inhibit (LVI) in stop mode

• LVI reset

• LVI module power

• Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)

• COP timeout period (2

• STOP instruction

• Computer operating properly module (COP)

• EEPROM reference clock source (CPU bus clock or CGMXCLK)

18

– 24 or 213 – 24 CGMXCLK cycles)

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Configuration Register (CONFIG) 85

Configuration Register (CONFIG)

6.3 Functional description

The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001F and $003F. The configuration register
may be read at anytime.

6.4 Configuration Register 1

Address: $001F

Bit 7 654321Bit 0

Read:

LVISTOP R LVIRSTD LVIPWRD SSREC COPRS STOP COPD

Write:

Reset: 00000000

R = Reserved

Figure 6-1. Configuration Register 1 (CONFIG1)

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate in stop mode. Reset clears LVISTOP. (See Section

21. Low-Voltage Inhibit (LVI).)

1 = LVI enabled during stop mode
0 = LVI disabled during stop mode

LVIRSTD — LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. (See

Section 21. Low-Voltage Inhibit (LVI).)

1 = LVI module resets disabled
0 = LVI module resets enabled

Technical Data MC68HC908AB32 — Rev. 1.0

86 Configuration Register (CONFIG) MOTOROLA

Configuration Register (CONFIG)

Configuration Register 1

LVIPWRD — LVI Power Disable Bit

LVIPWRD disables the LVI module. (See Section 21. Low-Voltage

Inhibit (LVI).)

1 = LVI module power disabled
0 = LVI module power enabled

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.

1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles

NOTE:

If using an external crystal oscillator, do not set the SSREC bit.

COPRS — COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. (See

Section 20. Computer Operating Properly (COP).)

1 = COP timeout period is 2
0 = COP timeout period is 2

18

– 24 CGMXCLK cycles

13

– 24 CGMXCLK cycles

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. (See Section 20. Computer

Operating Properly (COP).)

1 = COP module disabled
0 = COP module enabled

Extra care should be exercised when using this emulation part for
development of code to be run in ROM AB, AS or AZ parts that the
options selected by setting the CONFIG1 register match exactly the
options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AB, AS, and AZ families. If in doubt, check with your local field
applications representative.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Configuration Register (CONFIG) 87

Configuration Register (CONFIG)

6.5 Configuration Register 2

Address: $003F

Bit 7 654321Bit 0
Read:
Write:

Reset: 0

EEDIVCLK

R

R = Reserved

RRRRRR

Figure 6-2. Configuration Register 2 (CONFIG2)

EEDIVCLK — EEPROM Timebase Divider Clock Select Bit

EEDIVCLK selects the reference clock source for the EEPROM
timebase divider. (See Section 5. EEPROM.)

1 = CPU bus clock drives the EEPROM timebase divider
0 = CGMXCLK drives the EEPROM timebase divider

Extra care should be exercised when using this emulation part for
development of code to be run in ROM AB, AS or AZ parts that the
options selected by setting the CONFIG2 register match exactly the
options selected on any ROM code request submitted. The
enable/disable logic is not necessarily identical in all parts of the
AB, AS, and AZ families. If in doubt, check with your local field
applications representative.

Technical Data MC68HC908AB32 — Rev. 1.0

88 Configuration Register (CONFIG) MOTOROLA

Technical Data — MC68HC908AB32

Section 7. Central Processor Unit (CPU)

7.1 Contents

7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

7.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

7.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

7.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .93

7.2 Introduction

7.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

7.9 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The

Reference Manual

contains a description of the CPU instruction set, addressing modes,
and architecture.

(Motorola document order number CPU08RM/AD)

CPU08

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 89

Central Processor Unit (CPU)

7.3 Features

• Object code fully upward-compatible with M68HC05 Family

• 16-bit stack pointer with stack manipulation instructions

• 16-bit index register with x-register manipulation instructions

• 8-MHz CPU internal bus frequency

• 64K-byte program/data memory space

• 16 addressing modes

• Memory-to-memory data moves without using accumulator

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• Enhanced binary-coded decimal (BCD) data handling

• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64K-bytes

7.4 CPU Registers

• Low-power stop and wait modes

Figure 7-1 shows the five CPU registers. CPU registers are not part of

the memory map.

Technical Data MC68HC908AB32 — Rev. 1.0

90 Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

CPU Registers

7.4.1 Accumulator

7

15

H X

15

15

70

V11H I NZC

0

ACCUMULATOR (A)

0

INDEX REGISTER (H:X)

0

STACK POINTER (SP)

0

PROGRAM COUNTER (PC)

CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG

Figure 7-1. CPU Registers

The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.

Bit 7 654321Bit 0

Read:
Write:

Reset: Unaffected by reset

Figure 7-2. Accumulator (A)

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 91

Central Processor Unit (CPU)

7.4.2 Index Register

The 16-bit index register allows indexed addressing of a 64K-byte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.

The index register can serve also as a temporary data storage location.

7.4.3 Stack Pointer

Bit

1413121110987654321

15

Read:
Write:

Reset: 00000000XXXXXXXX

X = Indeterminate

Bit

0

Figure 7-3. Index Register (H:X)

The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.

Technical Data MC68HC908AB32 — Rev. 1.0

92 Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

CPU Registers

NOTE:

7.4.4 Program Counter

Bit

1413121110987654321

15

Read:
Write:

Reset: 0000000011111111

Bit

0

Figure 7-4. Stack Pointer (SP)

The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.

The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.

During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.

Bit

1413121110987654321

15

Read:
Write:

Reset: Loaded with Vector from $FFFE and $FFFF

Bit

0

Figure 7-5. Program Counter (PC)

7.4.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 93

Central Processor Unit (CPU)

5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.

Bit 7 654321Bit 0

Read:
Write:

Reset: X 1 1X1XXX

V11H I NZC

X = Indeterminate

Figure 7-6. Condition Code Register (CCR)

V — Overflow Flag

The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.

1 = Overflow
0 = No overflow

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add­with-carry (ADC) operation. The half-carry flag is required for binary­coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.

1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4

Technical Data MC68HC908AB32 — Rev. 1.0

94 Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

CPU Registers

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.

1 = Interrupts disabled
0 = Interrupts enabled

NOTE:

To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.

After the I bit is cleared, the highest-priority interrupt request is
serviced first.

A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).

N — Negative flag

The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.

1 = Negative result
0 = Non-negative result

Z — Zero flag

The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.

1 = Zero result
0 = Non-zero result

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 95

Central Processor Unit (CPU)

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.

1 = Carry out of bit 7
0 = No carry out of bit 7

7.5 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the
instruction set.

7.6 Low-Power Modes

7.6.1 Wait Mode

Refer to the
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.

The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.

The WAIT instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

CPU08 Reference Manual

(Motorola document order

Technical Data MC68HC908AB32 — Rev. 1.0

96 Central Processor Unit (CPU) MOTOROLA

7.6.2 Stop Mode

The STOP instruction:

• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.

7.7 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break
interrupt by:

Central Processor Unit (CPU)

CPU During Break Interrupts

• Loading the instruction register with the SWI instruction

• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode

The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.

A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.

7.8 Instruction Set Summary

7.9 Opcode Map

See Table 7-2.

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 97

Central Processor Unit (CPU)

Table 7-1. Instruction Set Summary

Source

ADC #
ADC
ADC
ADC
ADC
ADC ,X
ADC
ADC

ADD #
ADD
ADD
ADD
ADD
ADD ,X
ADD
ADD

Form

opr
opr
opr
opr
opr

opr
opr

opr
opr
opr
opr
opr

opr
opr

,X
,X

,SP
,SP

,X
,X

,SP
,SP

Add with Carry A ← (A) + (M) + (C) ↕↕– ↕↕↕

Add without Carry A ← (A) + (M) ↕↕– ↕↕↕

Operation Description

Effect on

CCR

VHINZC

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

Address

Mode

A9

B9
C9
D9

E9

F9

9EE9
9ED9

AB
BB
CB
DB
EB
FB

9EEB
9EDB

Opcode

ii
dd
hh ll
ee ff
ff

ff
ee ff

ii
dd
hh ll
ee ff
ff

ff
ee ff

Operand

Cycles

2
3
4
4
3
2
4
5

2
3
4
4
3
2
4
5

AIS #

opr

AIX #

opr

AND #

opr

AND

opr

AND

opr

AND

opr

AND

opr

AND ,X

opr

AND
AND

opr

opr

ASL
ASLA
ASLX
ASL

opr

ASL ,X
ASL

opr

ASR

opr

ASRA
ASRX
ASR

opr

ASR

opr

ASR

opr

BCC

rel

BCLR n,

,X
,X

,SP
,SP

,X

,SP

,X
,X
,SP

opr

Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) ––––––IMM A7 ii 2
Add Immediate V alue (Signed) to H:X H:X ← (H:X) + (16 « M) ––––––IMM AF ii 2

IMM
DIR
EXT

Logical AND A ← (A) & (M) 0 – – ↕↕–

Arithmetic Shift Left
(Same as LSL)

Arithmetic Shift Right ↕ ––↕↕↕

Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

Clear Bit n in M Mn ← 0 ––––––

C

b7

b7

0

b0

C

b0

↕ ––↕↕↕

IX2
IX1
IX
SP1
SP2

DIR
INH
INH
IX1
IX
SP1

DIR
INH
INH
IX1
IX
SP1

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

A4

B4
C4
D4

E4

F4

9EE4
9ED4

38

48

58

68

78

9E68

37

47

57

67

77

9E67

11

13

15

17

19

1B
1D

1F

ii
dd
hh ll
ee ff
ff

ff
ee ff

dd

ff

ff
dd

ff

ff

dd
dd
dd
dd
dd
dd
dd
dd

2
3
4
4
3
2
4
5

4
1
1
4
3
5

4
1
1
4
3
5

4
4
4
4
4
4
4
4

Technical Data MC68HC908AB32 — Rev. 1.0

98 Central Processor Unit (CPU) MOTOROLA

BCS
BEQ

Source

Form

rel
rel

Table 7-1. Instruction Set Summary (Continued)

Operation Description

Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +
Branch if Equal PC ← (PC) + 2 +

Central Processor Unit (CPU)

Opcode Map

Effect on

CCR

VHINZC

rel

? (C) = 1 ––––––REL 25 rr 3

rel

? (Z) = 1 ––––––REL 27 rr 3

Address

Mode

Opcode

Operand

Cycles

BGE

BGT

BHCC
BHCS
BHI

rel

BHS

BIH

rel

BIL

rel

BIT #
BIT

opr

BIT

opr

BIT

opr

BIT

opr

BIT ,X
BIT

opr

BIT

opr

BLE

BLO

opr

opr

rel

opr

opr

rel

rel

rel

,X
,X

,SP
,SP

Branch if Greater Than or Equal To
(Signed Operands)

Branch if Greater Than (Signed
Operands)

Branch if Half Carry Bit Clear PC ← (PC) + 2 +
Branch if Half Carry Bit Set PC ← (PC) + 2 +
Branch if Higher PC ← (PC) + 2 +
Branch if Higher or Same

(Same as BCC)
Branch if IRQ Pin High PC ← (PC) + 2 +
Branch if IRQ Pin Low PC ← (PC) + 2 +

Bit Test (A) & (M) 0 – – ↕↕–

Branch if Less Than or Equal To
(Signed Operands)

Branch if Lower (Same as BCS) PC ← (PC) + 2 +

PC ← (PC) + 2 +

PC ← (PC) + 2 +

PC ← (PC) + 2 +

PC ← (PC) + 2 +

rel

? (N ⊕ V) = 0 ––––––REL 90 rr 3

rel

? (Z) | (N ⊕ V) =

0

rel

? (H) = 0 ––––––REL 28 rr 3

rel

? (H) = 1 ––––––REL 29 rr 3

rel

? (C) | (Z) = 0 ––––––REL 22 rr 3

rel

? (C) = 0 ––––––REL 24 rr 3

rel

? IRQ = 1 ––––––REL 2F rr 3

rel

? IRQ = 0 ––––––REL 2E rr 3

rel

? (Z) | (N ⊕ V) =

1

rel

? (C) = 1 ––––––REL 25 rr 3

––––––REL 92 rr 3

––––––REL 93 rr 3

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A5

B5
C5
D5

E5

F5

9EE5
9ED5

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

BLS
BLT
BMC
BMI
BMS
BNE
BPL
BRA

rel

opr

rel

rel

rel

rel

rel

rel

Branch if Lower or Same PC ← (PC) + 2 +
Branch if Less Than (Signed Operands) PC ← (PC) + 2 +
Branch if Interrupt Mask Clear PC ← (PC) + 2 +
Branch if Minus PC ← (PC) + 2 +
Branch if Interrupt Mask Set PC ← (PC) + 2 +
Branch if Not Equal PC ← (PC) + 2 +
Branch if Plus PC ← (PC) + 2 +
Branch Always PC ← (PC) + 2 +

rel

? (C) | (Z) = 1 ––––––REL 23 rr 3

rel

? (N ⊕ V) =1 ––––––REL 91 rr 3

rel

rel

? (N) = 1 ––––––REL 2B rr 3

rel

rel

rel

? (N) = 0 ––––––REL 2A rr 3

? (I) = 0 ––––––REL 2C rr 3

? (I) = 1 ––––––REL 2D rr 3

? (Z) = 0 ––––––REL 26 rr 3

rel

––––––REL 20 rr 3

MC68HC908AB32 — Rev. 1.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 99

Central Processor Unit (CPU)

Table 7-1. Instruction Set Summary (Continued)

Source

Form

BRCLR n,

BRN

rel

opr,rel

Branch if Bit n in M Clear PC ← (PC) + 3 +

Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3

Operation Description

Effect on

CCR

VHINZC

rel

? (Mn) = 0 –––––↕

Address

Mode

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

Opcode

01

03

05

07

09

0B
0D

0F

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

Operand

Cycles

5
5
5
5
5
5
5
5

BRSET n,

BSET n,

rel

BSR

CBEQ

opr,rel

CBEQA #
CBEQX #
CBEQ

opr,X+,rel

CBEQ X+
CBEQ

opr,SP,rel

opr,rel

opr

opr,rel
opr,rel

,rel

Branch if Bit n in M Set PC ← (PC) + 3 +

Set Bit n in M Mn ← 1 ––––––

PC ← (PC) + 2; push (PCL)

Branch to Subroutine

Compare and Branch if Equal

SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

PC ← (PC) +

PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00

rel

? (Mn) = 1 –––––↕

––––––REL AD rr 4

rel

––––––

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

DIR
IMM
IMM
IX1+
IX+
SP1

00

02

04

06

08

0A
0C

0E

10

12

14

16

18

1A
1C

1E

31

41

51

61

71

9E61

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

dd
dd
dd
dd
dd
dd
dd
dd

dd rr
ii rr
ii rr
ff rr
rr
ff rr

5
5
5
5
5
5
5
5

4
4
4
4
4
4
4
4

5
4
4
5
4

6
CLC Clear Carry Bit C ← 0 –––––0INH 98 1
CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
CLR

CLRA
CLRX
CLRH
CLR
CLR ,X
CLR

opr

opr
opr

Clear

,X

,SP

M ← $00

A ← $00
X ← $00

H ← $00
M ← $00
M ← $00
M ← $00

0––01–

DIR
INH
INH
INH
IX1
IX
SP1

3F
4F
5F

8C

6F
7F

9E6F

dd

ff

ff

3
1
1
1
3
2
4

Technical Data MC68HC908AB32 — Rev. 1.0

100 Central Processor Unit (CPU) MOTOROLA