Motorola MC68HC68T1DW, MC68HC68T1P Datasheet
MC68HC68T1MOTOROLA
1
CMOS
The MC68HC68T1 HCMOS Clock/RAM p eripheral contains a real–time
clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three–wire
interface for communication with a microcontroller or processor. Operating in a
burst mode, successive Clock/RAM locations can be read or written using only
a single starting a ddress. An on–chip o scillator a llows acceptance o f a
selectable crystal frequency or the device can be programmed to accept a
50/60 Hz line input frequency.
The LINE and system voltage (V
SYS
) pins g ive the MC68HC68T1 the
capability for sensing power–up/power–down conditions, a capability useful for
battery–backup systems. The device has an interrupt output capable of
signaling a microcontroller or processor of an alarm, periodic interrupt, or power
sense condition. An alarm can be set for comparison with the seconds, minutes,
and hours registers. This alarm can be used in conjunction with the power
supply enable (PSE) output to initiate a system power–up sequence if the V
SYS
pin is powered to the proper level.
A software power–down sequence can be initiated by setting a bit in the
interrupt control register. This applies a reset to the CPU via the CPUR
pin, sets
the clock out (CLKOUT) and PSE pins low, and disables the serial interface.
This condition is held until a rising edge is sensed on the V
SYS
input pin,
signaling system power coming on, or by activation of a previously enabled
interrupt if the V
SYS
pin is powered up.
A watchdog circuit can be enabled that r equires t he microcontroller or
processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically
without performing a serial transfer. If this condition is not met, the CPUR
line
resets the CPU.
• Full Clock Features — Seconds, Minutes, Hours (AM/PM), Day–of–Week,
Date, Month, Year (0 – 99), Auto Leap Year
• 32–Byte General Purpose RAM
• Direct Interface to Motorola SPI and National MICROWIREt Serial Data
Ports
• Minimum Timekeeping Voltage: 2.2 V
• Burst Mode for Reading/Writing Successive Addresses in Clock/RAM
• Selectable Crystal or 50/60 Hz Line Input Frequency
• Clock Registers Utilize BCD Data
• Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD
Backplane
• Power–On Reset with First Time–Up Bit
• Freeze Circuit Eliminates Software Overhead During a Clock Read
• Three Independent Interrupt Modes — Alarm, Periodic, or Power–Down
• CPU Reset Output — Provides Orderly Power–Up/Power–Down
• Watchdog Circuit
• Pin–for–Pin Replacement for CDP68HC68T1
• Chip Complexity: 8500 FETs or 2125 Equivalent Gates
• Also See Application Notes ANE425 “Use of the MC68HC68T1 RTC with
M6805 Microprocessor”, AN457 “Providing a Real–Time Clock for the
MC68302”, and AN1065 “Use of the MC68HC68T1 Real–Time Clock with
Multiple Time Bases”
MICROWIRE is a trademark of National Semiconductor Inc.
Order this document
by MC68HC68T1/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
P SUFFIX
PLASTIC DIP
CASE 648
DW SUFFIX
SOG PACKAGE
CASE 751G
ORDERING INFORMATION
MC68HC68T1P Plastic DIP
MC68HC68T1DW SOG Package
16
1
16
1
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
V
SYS
V
BATT
XTAL
in
XTAL
out
V
DD
PSE
POR
LINE
SCK
INT
CPUR
CLKOUT
V
SS
SS
MISO
MOSI
Motorola, Inc. 1996
REV 2
2/96
MC68HC68T1 MOTOROLA
2
OSCILLATOR PRESCALE SECOND MINUTE HOUR
DAY/
DATE
MONTH
AM/PM
AND HOUR LOGIC
CALENDAR
LOGIC
50/60 Hz
STOP
/START
PRESCALE
SELECT
CLOCK
SELECT
CLOCK
CONTROL REG
INTERRUPT
CONTROL REG
8–BIT DATA BUS
COMPARATOR
YEAR
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
CLOCK
AND
INT
LOGIC
STATUS
REGISTER
POWER
SENSE
CONTROL
SERIAL
INTERFACE
FREEZE
CIRCUIT
32 x 8
RAM
PIN 16 = V
DD
PIN 8 = V
SS
XTAL
in
XTAL
out
V
BATT
LINE
CLKOUT
INT
V
SYS
POR
PSE
CPUR
SCK
MISO
MOSI
SS
12
10
14
15
13
11
1
3
9
2
4
6
5
7
BLOCK DIAGRAM
MC68HC68T1MOTOROLA
3
ABSOLUTE MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage (except Line Input**) – 0.5 to VDD + 0.5 V
V
out
DC Output Voltage – 0.5 to VDD + 0.5 V
I
in
DC Input Current, per Pin ± 10 mA
I
out
DC Output Current, per Pin ± 10 mA
I
DD
DC Supply Current, VDD and VSS Pins ± 30 mA
P
D
Power Dissipation, per Package*** 500 mW
T
stg
Storage Temperature – 65 to + 150 °C
T
L
Lead Temperature (10–Second Soldering) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
**See Electrical Characteristics Table.
***Power Dissipation Temperature Derating: 12 mW/_C from 65 to 85_C.
ELECTRICAL CHARACTERISTICS (T
A
= – 40 to + 85_C, Voltages Referenced to VSS)
Symbol
Parameter Test Condition
V
DD
V
Guaranteed
Limit
Unit
V
DD
Power Supply Voltage Range — 3.0 to 6.0 V
V
(stdby)
Minimum Standby (Timekeeping) Voltage* — 2.2 V
V
IL
Maximum Low–Level Input Voltage 3.0
4.5
6.0
0.9
1.35
1.8
V
V
IH
Minimum High–Level Input Voltage 3.0
4.5
6.0
2.1
3.15
4.2
V
V
in
Maximum Input Voltage, Line Input Power Sense Mode 5.0 12 V p–p
V
OL
Maximum Low–Level Output Voltage
I
out
= 0 mA
I
out
= 1.6 mA
4.5 0.1
0.4
V
V
OH
Minimum High–Level Output Voltage
I
out
= 0 mA
I
out
= 1.6 mA
4.5 4.4
3.7
V
I
in
Maximum Input Current, Except SS Vin = VDD or V
SS
6.0 ± 1
m
A
I
IL
Maximum Low–Level Input Current, SS Vin = V
SS
6.0 – 1.0
m
A
I
IH
Maximum Pull–Down Current, SS Vin = V
DD
6.0 100
m
A
I
OZ
Maximum Three–State Leakage Current V
out
= VDD or V
SS
6.0 ± 10
m
A
I
DD
Maximum Quiescent Supply Current
Vin = VDD or VSS, All Input; I
out
= 0 mA
6.0 50
m
A
I
DD
Maximum RMS Operating Supply Current
Crystal Operation
I
out
= 0 mA,
f
XTALin = 32 kHz
Vin = VDD or VSS, all
f
XTALin = 1 MHz
inputs except XTALin,
f
XTALin = 2 MHz
Clock Out Disabled,
f
XTALin = 4 MHz
No Serial Access Cycles
5.0 0.1
0.6
0.84
1.2
mA
Maximum RMS Operating Supply Current
External Frequency Source
Driving XTALin, XTAL
out
Open
I
out
= 0 mA,
f
XTALin = 32 kHz
Vin = VDD or VSS,
f
XTALin = 1 MHz
Clock Out Disabled,
f
XTALin = 2 MHz
No Serial Access
f
XTALin = 4 MHz
Cycles
5.0 0.024
0.12
0.24
0.5
I
batt
Maximum RMS Standby Current
Crystal Operation
V
BATT
= 3.0 V,
f
XTALin = 32 kHz
V
SYS
= 0.0 V,
f
XTALin = 1 MHz
VDD = 0.0 V,
f
XTALin = 2 MHz
I
out
= 0 mA,
f
XTALin = 4 MHz
Vin = Don’t Care, all inputs except XTALin,
Clock Out Disabled, No Serial Access Cycles
0.0 25
250
360
600
m
A
*Timekeeping function only, no read/write accesses. Data in the registers and RAM retained.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields. However, pre
cautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
MC68HC68T1 MOTOROLA
4
AC ELECTRICAL CHARACTERISTICS (T
A
= – 40 to + 85_C, CL = 200 pF, Input tr = tf = 6 ns, Voltages Referenced to VSS)
Symbol
Parameter
Figure
No.
V
DD
V
Guaranteed
Limit
Unit
f
SCK
Maximum Clock Frequency (Refer to SCK tw, below) 1, 2, 3 3.0
4.5
6.0
—
2.1
2.1
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, SCK to MISO 2, 3 3.0
4.5
6.0
200
100
100
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, SS to MISO 2, 4 3.0
4.5
6.0
200
100
100
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, SCK to MISO 2, 4 3.0
4.5
6.0
200
100
100
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output (Measured Between 70% V
DD
and 20% VDD)
2, 3 3.0
4.5
6.0
200
100
100
ns
C
in
Maximum Input Capacitance — 10 pF
TIMING REQUIREMENTS (T
A
= – 40 to + 85_C, Input tr = tf = 6 ns, Voltages Referenced to VSS)
Symbol
Parameter
Figure
No.
V
DD
V
Guaranteed
Limit
Unit
t
su
Minimum Setup Time, SS to SCK 1, 2 3.0
4.5
6.0
200
100
100
ns
t
su
Minimum Setup Time, MOSI to SCK 1, 2 3.0
4.5
6.0
200
100
100
ns
t
h
Minimum Hold Time, SCK to SS 1, 2 3.0
4.5
6.0
250
125
125
ns
t
h
Minimum Hold Time, SCK to MOSI 1, 2 3.0
4.5
6.0
200
100
100
ns
t
rec
Minimum Recovery Time, SCK 1, 2 3.0
4.5
6.0
200
200
200
ns
t
w(H)
,
t
w(L
)
Minimum Pulse Width, SCK 1, 2 3.0
4.5
6.0
400
200
200
ns
t
w
Minimum Pulse Width, POR 3.0
4.5
6.0
—
100
100
ns
tr, t
f
Maximum Input Rise and Fall Times (Except XTALin and POR) (Measured
Between 70% VDD and 20% VDD)
1, 2 3.0
4.5
6.0
—
2
2
m
s
MC68HC68T1MOTOROLA
5
MOSI
SCK
SS
t
su
t
w(L)
t
r
t
w(H)
1/f
SCK
t
h
t
rec
t
h
t
su
t
f
A6 A5 A0 D7
O
D6
O
D0
N
NOTE: Measurement points are VIL and VIH unless otherwise noted on the AC Electrical Characteristics table.
— V
DD
— V
SS
— V
DD
— V
SS
— V
DD
— V
SS
D1
N
W/R
Figure 1. Write Cycle
MOSI
SCK
SS
t
su
t
w(L)
t
r
t
w(H)
1/f
SCK
t
h
t
rec
t
h
W/R
A6 A5 A0
D6
O
D0
N
NOTE: Measurement points are VOL, VOH, VIL, and VIH unless otherwise noted on the AC Electrical Characteristics table.
— V
DD
— V
SS
— V
DD
— V
SS
— V
DD
— V
SS
D1
N
D7
O
MISO
t
su
t
f
t
TLH
, t
THL
t
PLZ
, t
PHZ
t
PLH
, t
PHL
tpZL, tp
ZH
HIGH
IMPEDANCE
Figure 2. Read Cycle
DEVICE
UNDER
TEST
OUTPUT
TEST POINT
CL*
*Includes all probe and fixture capacitance.
DEVICE
UNDER
TEST
OUTPUT
TEST POINT
CL*
*Includes all probe and fixture capacitance.
CONNECT TO VDD WHEN
TESTING t
PLZ
AND t
PZL
CONNECT TO VSS WHEN
TESTING t
PHZ
AND t
PZH
Figure 3. Test Circuit Figure 4. Test Circuit
MC68HC68T1 MOTOROLA
6
OPERATING CHARACTERISTICS
The real–time clock consists of a clock/calendar and a
32 x 8 RAM (see Figure 5). Communication with the device
may be established via a serial peripheral interface (SPI) or
MICROWIRE bus. In addition to the clock/calendar data from
seconds to years, and systems flexibility provided by the
32–byte RAM, the clock features computer handshaking with
an interrupt output and a separate square–wave clock output
that can be one of seven different frequencies. An alarm circuit is available that compares the alarm latches with the seconds, minutes, and hours time counters and activates the
interrupt output when they are equal. The clock is specifically
designed to aid in power–up/power–down applications and
offers several pins to aid the designer of battery–backup systems.
CLOCK/CALENDAR
The clock/calendar portion of this device consists of a long
string of counters that is toggled by a 1 Hz input. The 1 Hz
input is derived from the on–chip oscillator that utilizes one of
four possible external crystals or that can be driven by an external frequency source. The 1 Hz trigger to the counters can
also be supplied by a 50 or 60 Hz source that is connected to
the LINE input pin.
The time counters offer seconds, minutes, and hours data
in 12– or 24–hour format. An AM/PM indicator is available
that once set, toggles at 12:00 AM and 12:00 PM. The calendar counters consist of day of week, date of month, month,
and year information. Data in the counters is in BCD format.
The hours counter utilizes BCD for hours data plus bits for
12/24 hour and AM/PM modes. The seven time counters are
read serially at addresses $20 through $26. The time counters are written to at addresses $A0 through $A6. (See Figures 5 and 6 and Table 1.)
32 x 8 GENERAL–PURPOSE RAM
The real–time clock also has a static 32 x 8 RAM. The
RAM is read at addresses $00 through $1F and written to at
addresses $80 through $9F (see Figure 5).
ALARM
The alarm is set by accessing the three alarm latches and
loading the desired data. (See Serial Peripheral Interface.)
The alarm latches consist of seconds, minutes, and hours
registers. When their outputs equal the values of the seconds, minutes, and hours time counters, an interrupt is generated. The interrupt output goes low if the alarm bit in the
status register is set and the interrupt output is activated after
an alarm time is sensed (see Pin Descriptions, INT
Pin). To
preclude a false interrupt when loading the time counters, the
alarm interrupt bit in the interrupt control register should be
reset. This procedure is not required when the alarm time is
being loaded.
WATCHDOG FUNCTION
When Watchdog (bit 7) in the interrupt control register is
set high, the clock’s slave select pin must be toggled at regular intervals without a serial data transfer. If SS is not toggled
at the rate shown in Table 2, the MC68HC68T1 supplies a
CPU reset pulse at Pin 2 and Watchdog (bit 6) in the status
register is set (see Figure 7). Typical service and reset times
are shown in Table 2.
CLOCK OUT
The value in the three least significant bits of the clock
control r egister selects one of seven possible output frequencies. (See Clock Control Register.) This square–wave
signal is available at the CLKOUT pin. When the power–
down operation is initialized, the output is reset low.
CONTROL REGISTER AND STATUS REGISTER
The operation of the real–time clock is controlled by the
clock control and interrupt control registers, which are read/
write registers. Another register, the status register, is available to indicate the operating conditions. The status register
is a read–only register, and a read operation resets status
bits.
MODE SELECT
The voltage level that is present at the V
SYS
input pin at the
end of power–on reset selects the device to be in the single–
supply mode or battery–backup mode.
Single–Supply Mode
If V
SYS
is powered up when power–on reset is completed;
CLKOUT, PSE, and CPUR
are enabled high and the device
is completely operational. CPUR
is asserted low if the volt-
age level at the V
SYS
pin subsequently falls below V
BATT
+
0.7 V. If CLKOUT, PSE, and CPUR
are reset low due to a
power–down instruction, V
SYS
brought low and then pow-
ered high re–enables these outputs.
An example of the single–supply mode is where only one
supply is available and VDD, V
BATT
, and V
SYS
are tied to-
gether to the supply.
Battery–Backup Mode
If V
SYS
is not powered up (V
SYS
= 0 V) at the end of pow-
er–on reset, CLKOUT, PSE, CPUR
, and SS are disabled
(CLKOUT, PSE, and CPUR
low). This condition is held until
V
SYS
rises to a threshold (approximately 0.7 V) above V
BATT
.
CLKOUT, PSE, and CPUR are then enabled and the device
is operational. If V
SYS
falls below a threshold above V
BATT
,
the outputs CLKOUT, PSE, and CPUR
are reset low.
An example of battery–backup operation occurs if V
SYS
is
tied to the 5 V supply and is not receiving voltage from a supply. A rechargeable battery is connected to the V
BATT
pin,
causing a POR while V
SYS
= 0 V. The device retains data
and keeps time down to a minimum V
BATT
voltage of 2.2 V.
The power consumption may not settle to the specified lim-
it until main power is cycled once.
POWER CONTROL
Power control is composed of t wo operations, power–
sense and power–down/power–up. Two pins are involved in
power sensing, the LINE input pin and the INT
output pin.
Two additional pins, PSE and V
SYS
, are utilized during
power–down/power–up operation.
MC68HC68T1MOTOROLA
7
FREEZE FUNCTION
The freeze function p revents an i ncrement o f the time
counters, if any of the registers are being read. Also, alarm
operation is delayed if the registers are being read. This
causes the clock to lose time with increasing rates of acceleration.
POWER SENSING
When power sensing is enabled (Power Sense Bit in the
interrupt control register), ac/dc transitions are sensed at the
LINE input pin. Threshold detectors determine when transitions cease. After a delay of 2.68 to 4.64 ms plus the external input RC circuit time constant, an interrupt true bit is set
high in the status register. This bit can then be sampled to
see if system power has turned back on (see Figure 8).
The power–sense circuitry operates by sensing the level of
the voltage present at the LINE input pin. This voltage is centered around VDD, and as long as the voltage is either plus or
minus a threshold (approximately 0.7 V) from VDD, a power
sense failure is not indicated. With an ac signal present,
remaining in this VDD window longer than a maximum of
4.64 ms activates the power–sense circuit. The larger the
amplitude of the signal, the less likely a power failure would
be detected. A 50 or 60 Hz, 10 V p–p sine–wave voltage is
an acceptable signal to present at the LINE input pin to set
up the power–sense function. When ac power fails, an internal circuit pulls the voltage at the line pin within the detection
window.
Power–Down
Power–down is a p rocessor–directed operation. The
power–down bit is set in the interrupt control register to initi-
ate power–down operation. During power–down, the power
supply enable (PSE) output, normally high, is driven low. The
CLKOUT pin is driven low. The CPUR
output, connected to
the processor reset input pin, is also driven low. In addition,
the serial interface (MOSI and MISO) is disabled (see Figure 9).
Power–Up
There are four methods that can initiate the power–up
mode. Two of the methods require an interrupt to the microcontroller or processor by programming the interrupt control
register. The interrupts can be generated by the alarm circuit
by setting the alarm bit and the appropriate alarm registers.
Also, an interrupt can be generated by programming the periodic interrupt bits in the interrupt control register. V
SYS
must
be at 5 volts for this operation to occur.
The third method is by initiating the power sense circuit
with the power sense bit in the interrupt control register set to
sense power loss along with the V
SYS
pin to sense subsequent power–up condition (see Figure 10). (Reference Figure 19 for application circuit for third method.)
The fourth method that initiates power–up occurs when the
level on the V
SYS
pin rises 0.7 V above the level of the V
BATT
pin, after previously falling to the level of V
BATT
while in the
battery–backup mode. An interrupt is not generated when
the fourth method is utilized.
While in the single–supply mode, power–up i s initiated
when the V
SYS
pin loses power and then returns high. There
is no interrupt generated when using this method (see Figure 11).
MC68HC68T1 MOTOROLA
8
SECONDS
MINUTES
HOURS
DAY OF THE WEEK
DATE OF THE MONTH
MONTH
YEAR
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
STATUS REGISTER
CLOCK CONTROL REGISTER
INTERRUPT CONTROL REGISTER
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
$32
$00
$1F
$20
$32
$33
$7F
$80
$9F
$A0
$B2
T
H
R
U
T
H
R
U
T
H
R
U
T
H
R
U
T
H
R
U
WRITE ADDRESSES ONLY
WRITE ADDRESSES ONLY
NOT USED
READ ADDRESSES ONLY
READ ADDRESSES ONLY
32 BYTES GENERAL–PURPOSE USER
32 BYTES GENERAL–PURPOSE USER
RAM
CLOCK/CALENDAR
RAM
HEXADECIMAL
SECONDS
MINUTES
HOURS
DAY OF THE WEEK
DATE OF THE MONTH
MONTH
YEAR
NOT USED
SECONDS ALARM
MINUTES ALARM
HOURS ALARM
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
CLOCK CONTROL REGISTER
INTERRUPT CONTROL REGISTER
$A0
$A1
$A2
$A3
$A4
$A5
$A6
$A7
$A8
$A9
$AA
$AB
$AC
$AD
$AE
$AF
$B0
$B1
$B2
HEXADECIMAL
HEXADECIMAL
CLOCK/CALENDAR
Figure 5. Address Map
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