Motorola MC68HC2681FN, MC68HC2681P, MC68HC681FN Datasheet



MOTOROLA, 1996 All Rights Reserved.

µ

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MC68HC681

DUAL ASYNCHRONOUS

RECEIVER/TRANSMITTER

(DUART)

™

MOTOROLA

MC68HC681 USER’S MANUAL

iii

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MC68HC681 USER’S MANUAL

MOTOROLA

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MOTOROLA

MC68HC681 USER’S MANUAL

v

TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 Internal Control Logic........................................................................... 1-4

1.2 Timing Logic......................................................................................... 1-4

1.3 Interrupt Control Logic.......................................................................... 1-5

1.4 Data Bus Buffer.................................................................................... 1-5

1.5 Communication Channels A and B ...................................................... 1-5

1.6 Input Port.............................................................................................. 1-5

1.7 Output Port........................................................................................... 1-6

Section 2

Signal Descriptions

2.1 V

CC

and GND ....................................................................................... 2-2

2.2 Crystal Input or External CLOCK (X1).................................................. 2-2

2.3 Crystal Input (X2) ................................................................................. 2-3

2.4 RESET (RESET

).................................................................................. 2-3

2.5 Chip-Select (CS

) .................................................................................. 2-3

2.6 Read/Write (R/W

)................................................................................. 2-3

2.7 Data Transfer Ackowledge (DTACK

) ................................................... 2-4

2.8 Register-Select Bus (RS1–RS4).......................................................... 2-4

2.9 Data Bus (D0–D7)................................................................................ 2-4

2.10 Interupt Request (IRQ

)......................................................................... 2-4

2.11 Interupt Ackowledge (IACK

)................................................................. 2-4

2.12 Channel A/B Transmitter Serial-Data Output (TxDA/TxDB)................. 2-4

2.13 Channel A/B Receiver Serial-Data Input (RxDA/RxDB)....................... 2-4

2.14 Parallel Inputs (IP0–IP5) ...................................................................... 2-4

2.14.1 IP0.............................................................................................. 2-4

2.14.2 IP1.............................................................................................. 2-5

2.14.3 IP2.............................................................................................. 2-5

2.14.4 IP3.............................................................................................. 2-5

2.14.5 IP4.............................................................................................. 2-5

2.14.6 IP5.............................................................................................. 2-5

2.15 Parallel Outputs (OP0–OP7)................................................................ 2-5

2.15.1 OP0 ............................................................................................ 2-5

2.15.2 OP1 ............................................................................................ 2-5

2.15.3 OP2 ............................................................................................ 2-6

2.15.4 OP3 ............................................................................................ 2-6

TABLE OF CONTENTS (Continued)

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2.15.5 OP4............................................................................................ 2-6

2.15.6 OP5............................................................................................ 2-6

2.15.7 OP6............................................................................................ 2-6

2.15.8 OP7............................................................................................ 2-6

Section 3

Operation

3.1 Transmitter........................................................................................... 3-1

3.2 Receiver............................................................................................... 3-2

3.3 Looping Modes..................................................................................... 3-4

3.3.1 Automatic-Echo Mode................................................................ 3-5

3.3.2 Local-Loopback Mode................................................................ 3-5

3.3.3 Remote-Loopback Mode............................................................ 3-5

3.4 Multidrop Mode .................................................................................... 3-5

3.5 Counter/Timer...................................................................................... 3-6

3.5.1 Counter Mode............................................................................ 3-6

3.5.2 Timer Mode................................................................................ 3-7

Section 4

Programming and Register Descriptions

4.1 Programming Descriptions................................................................... 4-1

4.2 Register Bit Formats ............................................................................ 4-6

4.3 Register Description........................................................................... 4-13

4.3.1 Channel A Mode Register 1 (MR1A)........................................ 4-13

4.3.1.1 Channel A Receiver Ready-To-Receive

Control — MR1A[7]. ..................................................... 4-13

4.3.1.2 Channel A Receiver-Interrupt Select - MR1A[6]........... 4-13

4.3.1.3 Channel A Error Mode Select - MR1A[5]...................... 4-13

4.3.1.4 Channel A Parity Mode Select - MR1A[4:3]. ................ 4-13

4.3.1.5 Channel A Parity Type Select - MR1A[2]. .................... 4-13

4.3.1.6 Channel A Bits-Per-Character Select - MR1A[1:0]........4-13

4.3.2 Channel A Mode Register 2 (MR2A)........................................ 4-14

4.3.2.1 Channel A Mode Select - MR2A[7:6]............................ 4-14

4.3.2.2 Channel A Transmitter Request-to-Send

Control - MR2A[5]. ........................................................4-15

4.3.2.3 Channel A Clear-to-Send Control - MR2A[4]................ 4-16

4.3.2.4 Channel A Stop Bit Length Select - MR2A[3:2]............ 4-16

4.3.3 Channel B Mode Register 1 (MR1B)........................................ 4-16

4.3.4 Channel B Mode Register 2 (MR2B)........................................ 4-16

4.3.5 Channel A Clock-Select Register (CSRA) ............................... 4-16

TABLE OF CONTENTS (Continued)

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Number Title Number

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4.3.5.1 Channel A Receiver Clock Select - CSRA[7:4]............. 4-16

4.3.5.2 Channel A Transmitter Clock Select - CSRA[3:0]......... 4-16

4.3.6 Channel B Clock-Select Register (CSRB)................................ 4-17

4.3.6.1 Channel B Receiver Clock Select - CSRB[7:4]............. 4-17

4.3.6.2 Channel B Transmitter Clock Select - CSRB[3:0]......... 4-17

4.3.7 Channel A Command Register (CRA)...................................... 4-17

4.3.7.1 CRA[7]. ......................................................................... 4-17

4.3.7.2 Channel A Miscellaneous Commands - CRA[6:4]........ 4-17

4.3.7.3 Channel A Transmitter Commands - CRA[3:2]............. 4-18

4.3.7.4 Channel A Receiver Commands - CRA[1:0]................. 4-18

4.3.8 Channel B Command Register (CRB)...................................... 4-19

4.3.9 Channel A Status Register (SRA)............................................ 4-19

4.3.9.1 Channel A Received Break - SRA[7]............................ 4-19

4.3.9.2 Channel A Framing Error - SRA[6]. .............................. 4-19

4.3.9.3 Channel A Parity Error - SRA[5]. .................................. 4-19

4.3.9.4 Channel A Overrun Error - SRA[4]. .............................. 4-19

4.3.9.5 Channel A Transmitter Empty - SRA[3]........................ 4-19

4.3.9.6 Channel A Transmitter Ready - SRA[2]........................ 4-20

4.3.9.7 Channel A FIFO Full - SRA[1]. ..................................... 4-20

4.3.9.8 Channel A Receiver Ready - SRA[0]............................ 4-20

4.3.10 Channel B Status Register (SRB) ............................................ 4-20

4.3.11 Output Port Configuration Register (OPCR) ............................ 4-20

4.3.11.1 OP7 Output Select - OPCR[7]...................................... 4-20

4.3.11.2 OP6 Output Select - OPCR[6]...................................... 4-20

4.3.11.3 OP5 Output Select - OPCR[5]...................................... 4-20

4.3.11.4 OP4 Output Select - OPCR[4]...................................... 4-20

4.3.11.5 OP3 Output Select - OPCR[3:2]................................... 4-21

4.3.11.6 OP2 Output Select - OPCR[1:0]................................... 4-21

4.3.12 Output Port Register - OPR[7:0]............................................... 4-21

4.3.13 Auxiliary Control Register (ACR).............................................. 4-21

4.3.13.1 Baud-Rate Generator Set Select - ACR[7]................... 4-21

4.3.13.2 Counter/Timer Mode and Clock Source

Select — ACR[6:4]. .......................................................4-22

4.3.13.3 IP3, IP2, IP1, and IP0 Change-of-State Interrupt

Enable — ACR[3:0]. .....................................................4-22

4.3.14 Input Port Change Register (IPCR).......................................... 4-22

4.3.14.1 IP3, IP2, IP1, and IP0 Change of State - IPCR[7:4]. .... 4-22

4.3.14.2 IP31 IP2F IP1, and IP0 Current State — IPCR[3:0]. .... 4-22

4.3.15 Interrupt Status Register (ISR)................................................. 4-22

4.3.15.1 Input Port Change Status - ISR[7]............................... 4-23

4.3.15.2 Channel B Change in Break — ISR[6].......................... 4-23

4.3.15.3 Channel B Receiver Ready or FIFO Full — ISR[5]....... 4-23

TABLE OF CONTENTS (Continued)

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4.3.15.4 Channel B Transmitter Ready — ISR[4]....................... 4-23

4.3.15.5 Counter/Timer Ready — ISR[3].................................... 4-23

4.3.15.6 Channel A Change in Break — ISR[2]. ........................ 4-23

4.3.15.7 Channel A Receiver Ready or FIFO Full — ISR[1]. ..... 4-23

4.3.15.8 Channel A Transmitter Ready — ISR[0]....................... 4-23

4.3.16 Interrupt Mask Register (IMR).................................................. 4-23

4.3.17 Count Registers (CUR and CLR)............................................. 4-24

4.3.18 Counter/Timer Preload Registers (CTUR and CTLR).............. 4-24

4.3.19 Interrupt Vector Register (IVR)................................................. 4-24

Section 5

Electrical Specifications

5.1 Absolute Maximum Ratings ................................................................. 5-1

5.2 Thermal Characteristics....................................................................... 5-1

5.3 Power Considerations.......................................................................... 5-1

5.4 DC Electrical Characteristics................................................................ 5-2

5.5 AC Electrical Characteristics................................................................ 5-3

5.5.1 Clock Timing .............................................................................. 5-3

5.5.2 RESET

Timing ........................................................................... 5-4

5.5.3 Read and Write Bus Cycle Timing............................................. 5-4

5.5.4 Interrupt Bus Cycle Timing......................................................... 5-5

5.5.5 Port Timing................................................................................. 5-7

5.5.6 Interrupt Reset Timing................................................................ 5-8

5.5.7 Transmitter Timing..................................................................... 5-8

5.5.8 Receiver Timing......................................................................... 5-9

5.5.9 Transmit And Receive Operation............................................. 5-10

Section 6

Mechanical Data and Ordering Information

6.1 Pin Assignments .................................................................................. 6-1

6.2 Ordering Information............................................................................ 6-1

6.3 Package Dimensions ........................................................................... 6-2

6.4 Pin Assignment–40 Pin Dual-In-Line Plastic Package..........................6-3

6.5 Ordering Information.............................................................................6-3

6.6 Package Dimensions–40 Pin Dual-In-Line Package.............................6-4

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

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ix

Appendix A

MC68HC2681

A.1 Introduction ......................................................................................... A-1

A.1.1 Interrupt Control Logic.............................................................. A-1

A.1.2 Input Port.................................................................................. A-1

A.2 Signal Description................................................................................ A-1

A.2.1 Reset (RESET

)......................................................................... A-4

A.2.2 Chip-Select (CS

) ...................................................................... A-4

A.2.3 Write Strobe (W

)....................................................................... A-4

A.2.4 Read Strobe (R) ....................................................................... A-4

A.2.5 Parallel Input 6 (IP6)................................................................. A-4

A.2.6 Parallel Input 2 (IP2)................................................................. A-4

A.3 Programming and Register Description.............................................. A-4

A.4 Electrical Specifications ...................................................................... A-6

A.4.1 Absolute Maximum Ratings...................................................... A-6

A.4.2 Thermal Characteristics ........................................................... A-6

A.4.3 DC Electrical Characteristics.................................................... A-6

A.4.4 AC Electrical Characteristics.................................................... A-7

A.4.4.1 Clock Timing................................................................. A-7

A.4.4.2 RESET

Timing.............................................................. A-8

A.4.4.3 Bus Timing..................................................................... A-8

A.4.4.4 Port Timing................................................................... A-9

A.4.4.5 Interrupt Reset Timing................................................. A-9

A.4.4.6 Transmitter Timing....................................................... A-10

A.4.4.7 Receiver Timing.......................................................... A-10

A.5 Mechanical Data and Ordering Information ....................................... A-14

A.5.1 Pin Assignment—44 Pin Plastic Leaded Chip Carrier.............. A-14

A.5.2 FN Suffix Ordering Information................................................. A-14

A.5.3 FN Suffix Packaging Dimensions............................................. A-15

A.5.4 Pin Assignment—40 Pin Dual-In Line Plastic Package............ A-16

A.5.5 P Suffix Ordering Information................................................... A-16

A.5.6 Packaging Dimensions—Plastic............................................... A-17

Index

TABLE OF CONTENTS (Continued)

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Number Title Number

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MC68HC681 USER’S MANUAL

xiii

LIST OF TABLES

Table Page

Number Title Number

2-1. Signal Summary ..............................................................................................2-1

4-1. Register Addressing and Address-Triggered Commands ...............................4-3

4-2. Programming of Input Port Functions .............................................................4-3

4-3. Programming of Output Port Functions ...........................................................4-4

4-4. Selection of Clock Sources for the Counter/Timer ..........................................4-5

4-5. Baud-Rate Generator Characteristics Crystal or Clock = 3.6864 MHz .........4-22

A-1. MC68HC2681 Signal Summary ..................................................................... A-3

A-2. MC68HC2681 Register Addressing and Address-Triggered Commands ...... A-5

MOTOROLA

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xi

LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

1-1. 68HC681Block Diagram ...................................................................................1-2

4-1. Programming Block Diagram ...........................................................................4-2

5-1. Clock Timing ....................................................................................................5-3

5-2. RESET Timing .................................................................................................5-4

5-3. Read Cycle Bus Timing ....................................................................................5-6

5-4. Write Cycle Bus Timing ....................................................................................5-6

5-5. Interrupt Cycle Bus Timing ...............................................................................5-7

5-6. Port Timing .......................................................................................................5-7

5-7. Interrupt Reset Timing ......................................................................................5-8

5-8. Transmitter Timing ...........................................................................................5-8

5-9. Receiver Timing ...............................................................................................5-9

5-10. Transmitter Operation ....................................................................................5-10

5-11. Receiver Operation ........................................................................................5-11

5-12. Wake-Up Mode Operation .............................................................................5-12

A-1. MC68HC2681 Block Diagram ......................................................................... A-2

A-2. Clock Timing ................................................................................................... A-7

A-3. RESET

Timing ................................................................................................ A-8

A-4. Bus Timing ...................................................................................................... A-8

A-5. Port Timing ...................................................................................................... A-9

A-6. Interrupt Reset Timing .................................................................................... A-9

A-7. Transmitter Timing ........................................................................................ A-10

A-8. Receiver Timing ............................................................................................ A-10

A-9. Transmitter Operation ................................................................................... A-11

A-10. Receiver Operation ....................................................................................... A-12

A-11. Wake-Up Mode Operation ............................................................................ A-13

MOTOROLA

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1-1

1

SECTION 1
INTRODUCTION

The MC68HC681 dual universal asynchronous receiver/transmitter (DUART) is part of the
M68000 Family of peripherals and directly interfaces to the MC68000 processor via an
asynchronous bus structure. The MC68HC681 consists of these major sections:

• Internal Control Logic

• Timing Logic

• Interrupt Control Logic

• Bidirectional 8-bit Data Bus Buffer

• Two Independent Communication Channels (A and B)

• 6-bit Parallel Input Port

• 8-bit Parallel Output Port

The MC68HC2681 dual asynchronous receiver/transmitter (DUART) is functionally
equivalent to the MC68HC681 with some minor differences. The description of the
MC68HC681 applies to the MC68HC2681 except for the areas described in Appendix A

MC68HC2681 located in the back of this document.

Figure 1-1 is a basic block diagram of the MC68HC681 and should be referred to during the
discussion of its features, which include the following:

• M68000 Bus Compatible

• Two Independent Full-Duplex Asynchronous Receiver/Transmitter Channels

• Maximum Data Transfer Rate:
— 1X — 1 Mbits/second

— 16X — 250 kbits/second

• Quadruple-Buffered Receiver Data Registers

• Double-Buffered Transmitter Data Registers

• Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable
From:

— 18 Fixed Rates: 50 to 38.4k Baud
— One User Defined Rate Derived from a Programmable Timer/Counter
— External 1X Clock or 16X Clock

Introduction

1-2

MC68HC681 USER’S MANUAL

MOTOROLA

1

Figure 1-1. MC68HC681 Block Diagram

INTERNAL CONTROL LOGIC

CHANNEL A

RS4-RS1

EXTERNAL
INTERFACE

TxDA

RxDA

X1

X2

PROCESSOR

INTERFACE

V

CC

IRQ

DTACK

R/W

CS

INTERNAL DATA BUS

CRA

COMMAND REGISTER W

MR1A MODE REGISTER 

1

R/W

MR2A

MODE REGISTER 2 R/W

SRA STATUS REGISTER

R

THRA TRANSMIT HOLDING REG W

RHRA RECEIVE HOLDING REG (3)

R

RHRA (2)

TBA

RBA

TRANSMIT SHIFT REG

RHRA (1)

RECEIVE SHIFT REGISTER

CHANNEL B

TxDB

RxDB

CRB COMMAND REGISTER

W

MR1B MODE REGISTER 1

R/W
MR2B MODE REGISTER 2 R/W
SRB STATUS REGISTER R

THRB TRANSMIT HOLDING REG

W

RHRB

RECEIVE HOLDING REG (3)

R

RHRB (2)

TBB

RBB

TRANSMIT SHIFT REGISTER

RHRB (1)

RECEIVE SHIFT REGISTER

INPUT PORT

IPCR

INPUT PORT CHANGE REG

R

AUX CONTROL REG (4 BITS) W

ACR

INPUT PORT (6 BITS)

R

ACR

*

Same ACR as in Interrupt Control Logic

*

OUTPUT PORT

OPCR OUTPUT PORT CONFIG REG

W

OUTPUT PORT REG (8 BITS)

W

OPR

FIFO

TIMING LOGIC

Current Count in Counter Mode may be Read

*

INTERRUPT CONTROL LOGIC

IMR INTERRUPT MASK REG W

INTERRUPT STATUS REG R

AUX CONTROL REG (4 BITS) W

ACR

*

Same ACR as in Input Port

*

D7-D0

DATA BUS BUFFER

CSRA CHANNEL A CLOCK SELECT REG W

CHANNEL B CLOCK SELECT REG

W

ACR AUXILIARY CONTROL REG (4 BITS) W

CSRB

COUNTER/TIMER

UPPER REGISTER

(MOST SIGNIF 8 BITS)

W

*

COUNTER/TIMER

LOWER REGISTER

(LEAST SIGNIF 8 BITS)

W

*

ISR

GND

OP7-OP0

RESET

IP5-IP0

INTERRUPT VECTOR REG

R/W

IVR

IACK

FIFO

Introduction

MOTOROLA

MC68HC681 USER’S MANUAL

1-3

1

• Programmable Data Format
— Five to eight data bits

— Odd, Even, force parity, or no parity
— One, one and one-half, or two stop bits

• Programmable Channel Modes
— Normal (full duplex)

— Automatic echo
— Local loopback
— Remote loopback

• Automatic Wake-up Mode for Multidrop Applications

• Multifunction 6-Bit Input Port
— Clock or control input functions

— Change-of-state detection on four inputs

• Multifunction 8-Bit Output Port
— Individual bit set/reset capability

— Status/Interrupt signal programmable outputs

• Multifunction 16-Bit Programmable Counter/Timer

• Versatile Interrupt System
— Single interrupt output with eight maskable interrupting conditions

— Interrupt vector output on interrupt acknowledge
— Programmable output port can be configured to provide as many as six separate

wire-ORable interrupt outputs

• Parity, Framing, and Overrun Error Detection

• False-Start Bit Detection

• Line-Break Detection and Generation

• Break Detection starting in the Middle of a Character

• Start-End Break Interrupt/Status

• On-Chip Crystal Oscillator

• TTL Compatible

• Single +5V Power Supply

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1.1 INTERNAL CONTROL LOGIC

The internal control logic receives operation commands from the central processing unit
(CPU) and generates appropriate signals to the internal sections to control device operation.
The internal control logic allows access to the registers within the DUART and performs
various commands by decoding the four register-select lines (RS1 through RS4). Besides
the four register-select lines, there are three other inputs to the internal control logic from the
CPU: read/write (R/W

), which allows read and write transfers between the CPU and DUART

via the data bus buffer; chip-select (CS

), which is the DUART chip-select; and reset

(RESET

), which initializes or resets the DUART. The data transfer acknowledge (DTACK)
signal, which is asserted during read, write, or interrupt-acknowledge cycles, is the internal
control logic output. The DTACK

signal indicates to the CPU that data has been latched on
a CPU write cycle or that valid data is present on the data bus during a CPU read cycle or
interrupt-acknowledge (IACK

) cycle.

1.2 TIMING LOGIC

The timing logic consists of a crystal oscillator, a baud-rate generator (BRG), a
programmable 16-bit counter/timer (C/T), and four clock selectors. The crystal oscillator
operates directly from a 3.6864 MHz crystal connected across the X1 and X2 inputs or from
an external clock of the appropriate frequency connected to X1. The X1 clock serves as the
basic timing reference for the baud-rate generator, the C/T, and other internal circuits. The
part can operate without an X1 clock but with the following restrictions:

• The X1 input must be connected to GND or V

CC

• The receiver(s) and transmitter(s), if used, must not be programmed to select any of the
18 standard rates generated by the BRG

• The counter/timer, if used, must not be programmed to the X1 or X1/16 selection

• The change-detect on IP0-IP3 will not operate

• DTACK

will not be generated on any bus cycle

The baud-rate generator operates from the X1 clock input and can generate 18 commonly
used data communication baud rates ranging from 50 to 38.4k by producing internal clock
outputs at 16 times the actual baud rate. The C/T can produce a 16X clock for other baud
rates by counting down its programmed clock source. Other baud rates can also be derived
by connecting 16X or 1X clocks to certain input port pins that have alternate functions as
receiver or transmitter clock inputs. Four clock selectors allow the independent selection of
any of these baud rates for each receiver and transmitter. Customers can program the 16­bit C/T within the DUART to use one of several clock sources as its input. The output of the
C/T is available to the internal clock selectors and can also be programmed to appear at
parallel output OP3. In the timer mode, the C/T acts as a programmable divider and can
generate a square-wave output at OP3. In the counter mode, the C/T can be started and
stopped under program control. When stopped, the CPU can read its contents. The counter
counts down the number of pulses stored in the concatenation of the C/T upper register and
C/T lower register and produces an interrupt. This is a system-oriented feature that can be
used to record timeouts when implementing various application protocols.

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1.3 INTERRUPT CONTROL LOGIC

The following registers are associated with the interrupt control logic:

• Interrupt Mask Register (IMR)

• Interrupt Status Register (ISR)

• Auxiliary Control Register (ACR)

• Interrupt Vector Register (IVR)

Refer to Section 4 Programming and Register Descriptions for more complete
information on these registers.

A single active-low interrupt output (IRQ

) can notify the processor that any of eight internal
events has occurred. These eight events are described in the discussion of the interrupt
status register (ISR) in Section 4 Programming and Register Descriptions . Customers
can program the interrupt mask register (IMR) to allow only certain conditions to cause IRQ
to be asserted while the CPU can read the ISR to determine all currently active interrupting
conditions. When an active-low interrupt acknowledge signal (IACK

) from the processor is
asserted while the DUART has an interrupt pending, the DUART will place the contents of
the interrupt vector register (IVR) on the data bus and assert the data transfer acknowledge
signal (DTACK

). If the DUART has no pending interrupt, it ignores IACK cycles. In addition,
customers can program the parallel outputs OP3 through OP7 to provide discrete interrupt
outputs for the transmitters, the receivers, and the C/T.

1.4 DATA BUS BUFFER

The data bus buffer provides the interface between the external and internal data buses. It
is controlled by the internal control logic to allow read and write data transfer operations to
occur between the controlling CPU and DUART by way of the eight parallel data lines (DO
through D7).

1.5 COMMUNICATION CHANNELS A AND B

Each communication channel comprises a full-duplex asynchronous receiver/transmitter
(UART). The operating frequency for each receiver and each transmitter can be selected
independently from the baud-rate generator, the C/T, or from an external clock. The
transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the
appropriate start, stop, and optional parity bits, and outputs a composite serial stream of
data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this
serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break
condition, and transfers an assembled character to the CPU during read operations.

1.6 INPUT PORT

The CPU reads the inputs to this 6-bit port (IP0 through IP5). High or low inputs to the input
port result in the CPU reading a logic one or logic zero, respectively; that is, there is no
inversion of the logic level. Each input port bit also has an alternate control function
capability. The alternate functions can be enabled/disabled on a bit-by-bit basis.

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Four change-of-state detectors are associated with inputs IP0, IP1, IP2, and IP3. If a high­to-low or low-to-high transition occurs on any of these inputs and the new level is stable for
more than 25 to 50 microseconds (best-to-worst case times), the corresponding bit in the
input port change register (IPCR) will be set. The sampling clock of the change detectors is
the X1/96 tap of the baud-rate generator (the 2400 baud tap), which is 38.4kHz if X1 is

3.6864MHz. A new input level must be sampled on two consecutive sample clocks to
produce a change detect. Also, customers can program the DUART to allow a change of
state

to

generate an interrupt to the CPU. The IPCR bits are cleared when the CPU reads

the register.

1.7 OUTPUT PORT

This 8-bit multipurpose output port can be used as a general-purpose output port.
Associated with the output port is an output port register (OPR). All bits of the OPR can be
individually set and reset. A bit is set by performing a write operation at the appropriate
address with the accompanying data specifying the bits to be set (one equals set and zero
equals no change). Similarly, a bit is reset by performing a write operation at another
address with the accompanying data specifying the bits to be reset (one equals reset and
zero equals no change).

The OPR stores data that is to be output at the output port pins. Unlike the input port, if a
particular bit of the OPR is set to a logic one or logic zero, the output pin will be at a low or
high level, respectively. Thus, a logic inversion occurs internal to the DUART with respect
to this register. The outputs are complements of the data contained in the OPR. Table 4-1
and Section 4 Programming and Register Descriptions provide more information on the
address location of the output port register and setting and resetting bits of this register.
Besides general-purpose outputs, the outputs can be individually assigned specific auxiliary
functions serving the communication channels. The assignment is accomplished by
appropriately programming the channel A and B mode registers (MR1A, MR1B, MR2A, and
MR2B) and the output port configuration register (OPCR). Section 4 Programming and

Register Descriptions provides more information on the mode registers and the OPCR.

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SECTION 2
SIGNAL DESCRIPTIONS

This section briefly describes the input and output signals. Table 2-1 provides a quick
reference for determining a signal’s pin number, its use as an input or output, whether it is
active high or low, and the section that contains more information about its operation.

NOTE

The terms assertion and negation will be used extensively to
avoid confusion when dealing with a mixture of "active low" and
"active high" signals. The term assert or assertion indicates
that a signal is active or true, independent of whether that level
is represented by a high or low voltage. The term negate or

negation indicates that a signal is inactive or false.

Table 2-1. Signal Summary

SIGNAL NAME MNEMONIC

PIN NO.

IN/OUT

ACTIVE

STATE

REFER TO
PARA. NO.

P PKG. FN PKG.

Power Supply (5 V) V

CC

40 44 In High 2.1
Ground GND 20 22 In Low 2.1
Crystal Input or External Clock X1 32 36 In — 2.2
Crystal Output X2 33 37 Out — 2.3
Reset RESET

34 38 In Low 2.4
Chip Select CS

35 39 In Low 2.5
Read/Write R/W

8 9 In High/Low 2.6

Data Transfer Acknowledge DTACK

9 10 Out

1

Low 2.7
Register-Select Bus Bit 4 RS4 6 7 In High 2.8
Register-Select Bus Bit 3 RS3 5 6 In High 2.8
Register-Select Bus Bit 2 RS2 3 4 In High 2.8
Register-Select Bus Bit 1 RS1 1 2 In High 2.8
Bidirectional-Data Bus Bit 7 D7 19 21 In/Out High 2.9
Bidirectional-Data Bus Bit 6 D6 22 25 In/Out High 2.9
Bidirectional-Data Bus Bit 5 D5 18 20 In/Out High 2.9
Bidirectional-Data Bus Bit 4 D4 23 26 In/Out High 2.9
Bidirectional-Data Bus Bit 3 D3 17 19 In/Out High 2.9

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2.1 V

CC

AND GND

Power is supplied to the DUART using these two signals. V

CC

is power ( + 5 volts) and GND

is the ground connection.

2.2 CRYSTAL INPUT OR EXTERNAL CLOCK (X1)

This input is one of two connections to a crystal or a connection to an external CMOS-level
clock. If a crystal is used, a capacitor of approximately 10 to 15 picofarads should be
connected from this pin to ground.

Bidirectional-Data Bus Bit 2 D2 24 27 In/Out High 2.9
Bidirectional-Data Bus Bit 1 D1 16 18 In/Out High 2.9
Bidirectional-Data Bus Bit 0

(Least-Significant Bit)

D0 25 28 In/Out High 2.9

Interrupt Request IRQ

21 24 Out

1

Low 2.10

Interrupt Acknowledge IACK

37 41 In Low 2.11
Channel A Transmitter Serial Data TxDA 30 33 Out — 2.12
Channel A Receiver Serial Data RxDA 31 35 In — 2.13
Channel B Transmitter Serial Data TxDB 11 13 Out — 2.14
Channel B Receiver Serial Data RxDB 10 11 In — 2.15
Parallel Input 5 IP5 38 42 In — 2.16.1
Parallel Input 4 IP4 39 43 In — 2.16.2
Parallel Input 3 IP3 2 3 In — 2.16.3
Parallel Input 2 IP2 36 40 In — 2.16.4
Parallel Input 1 IP1 4 5 In — 2.16.5
Parallel Input 0 IP0 7 8 In — 2.16.6
Parallel Output 7 OP7 15 17 Out

2

— 2.17.1

Parallel Output 6 OP6 26 29 Out

2

— 2.17.2

Parallel Output 5 OP5 14 16 Out

2

— 2.17.3

Parallel Output 4 OP4 27 30 Out

2

— 2.17.4

Parallel Output 3 OP3 13 15 Out

2

— 2.17.5
Parallel Output 2 OP2 28 31 Out — 2.17.6
Parallel Output 1 OP1 12 14 Out — 2.17.7
Parallel Output 0 OP0 29 32 Out — 2.17.8

NOTES:

1. Requires a pullup resistor

2. May require a pullup resistor, depending on its programmed function.

Table 2-1. Signal Summary (Continued)

SIGNAL NAME MNEMONIC

PIN NO.

IN/OUT

ACTIVE

STATE

REFER TO
PARA. NO.

P PKG. FN PKG.

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2.3 CRYSTAL INPUT (X2)

This input is an additional connection to a crystal (see Section 2 Signal Descriptions). If an
external CMOS-level clock is used, this pin must be left open. If a crystal is used, a capacitor
of approximately 10 to 15 picofarads should be connected from this pin to ground.

2.4 RESET (RESET)

The DUART can be reset by asserting the RESET

signal or by programming the appropriate

command register. A hardware reset (assertion of RESET

) clears the following registers:

• Status registers A and B (SRA and SRB)

• Interrupt mask register (IMR)

• Interrupt status register (ISR)

• Output port register (OPR)

• Output port configuration register (OPCR)

RESET

performs the following operations:

• Initializes the interrupt vector register (IVR) to 0F

16

• Places parallel outputs OP0 through OP7 in the high state

• Places the counter/timer in timer mode

• Places channels A and B in the inactive state with the transmitter serial-data outputs
(TxDA and TxDB) in the mark (high) state.

Software resets are not as encompassing and are achieved by appropriately programming
the channel A and/or B command registers. Reset commands can be programmed through
the command register to reset the receiver, transmitter, error status, or break-change
interrupts for each channel. Refer to Section 4 Programming and Register Descriptions
for more information.

2.5 CHIP-SELECT (CS)

This active-low input signal, when low, enables data transfers between the CPU and DUART
on the data lines (D0 through D7). These data transfers are controlled by read/write (R/W

)
and the register-select inputs (RS1 through RS4). When chip-select is high, the D0 through
D7 data lines are placed in the high-impedance state.

2.6 READ/WRITE (R/W)

When high, this input indicates a read cycle; when low, it indicates a write cycle. Assertion
of the chip-select input initiates a cycle.

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2.7 DATA TRANSFER ACKOWLEDGE (DTACK)

This three-state active low output is asserted in read, write, or interrupt-acknowledge (IACK

)
cycles to indicate the proper transfer of data between the CPU and DUART. If there is no
pending interrupt on an IACK cycle, DTACK

is not asserted. DTACK is an “active rescind”
signal: at the end of a transfer, it drives high momentarily, then is three-stated so that it can
be wire-ANDed with other DTACK

sources, like an open-drain signal.

2.8 REGISTER-SELECT BUS (RS1–RS4)

The register-select bus lines during read/write operations select the DUART internal
registers, ports, or commands.

2.9 DATA BUS (D0–D7)

These bidirectional three-state data lines transfer commands, data, and status between the
CPU and DUART. D0 is the least-significant bit.

2.10 INTERUPT REQUEST (IRQ)

This active-low, open-drain output signals the CPU that one or more of the eight maskable
interrupting conditions are true.

2.11 INTERUPT ACKOWLEDGE (IACK)

This active-low input indicates an interrupt-acknowledge cycle. If there is an interrupt
pending (IRQ

asserted) and this pin is asserted, the DUART responds by placing the

interrupt vector on the data bus and then asserting DTACK

. If there is no interrupt pending

(IRQ

negated), the DUART ignores this pin.

2.12 CHANNEL A/B TRANSMITTER SERIAL-DATA OUTPUT (TxDA/TxDB)

The independent transmitter serial-data outputs for channel A and B transmit the
least-significant bit first. The output is held high (mark condition) when its associated
transmitter is disabled, idle, or operating in the local loopback mode. (‘‘Mark’’ is high and
‘‘space’’ is low.) Data is shifted out from this pin on the falling edge of the programmed clock
source.

2.13 CHANNEL A/B RECEIVER SERIAL-DATA INPUT (RxDA/RxDB)

The independent receiver serial-data inputs for channel A and B receive the least-significant
bit first. Data on these pins is sampled on the rising edge of the programmed clock source.

2.14 PARALLEL INPUTS (IP0–IP5)

The parallel inputs can be used as general-purpose inputs. However, each pin also has an
alternate function(s) described below.

2.14.1 IP0

This input can be used as the channel A clear-to-send active-low input (CTSA

). A change-of-

state detector is also associated with this input.

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2.14.2 IP1

This input can be used as the channel B clear-to-send active-low input (CTSB

). A change-of-

state detector is also associated with this input.

2.14.3 IP2

This input can be used as the channel B receiver external clock input (RxCB), or the
counter/timer external clock input. When this input functions as the external clock to the
receiver, the received data is sampled on the rising edge of the clock. A change-of-state
detector is also associated with this input.

2.14.4 IP3

This input can serve as the channel A transmitter external clock input (TxCA). When this
input functions as the external clock to the transmitter, the transmitted data is clocked on the
falling edge of the clock. A change-of-state detector is also associated with this input.

2.14.5 IP4

This input can be used as the channel A receiver external clock input (RxCA). When this
input functions as the external clock to the receiver, the received data is sampled on the
rising edge of the clock.

2.14.6 IP5

This input can serve as the channel B transmitter external clock (TxCB). When this input is
used as the external clock to the transmitter, the transmitted data is clocked on the falling
edge of the clock.

2.15 PARALLEL OUTPUTS (OP0–OP7)

The parallel outputs can be used as general-purpose outputs; however, each pin also has
an alternate function(s), described below.

2.15.1 OP0

This output can function as the channel A transmitter active-low request-to-send (RTSA

)

output, or as the channel A receiver active-low ready-to-receive (RTRA

) output. When used

for RTSA

, it is automatically negated by the transmitter. When used for RTRA, the receiver

automatically negates and reasserts OP0.

2.15.2 OP1

This output can serve as the channel B transmitter active-low request-to-send (RTSB

)

output, or as the channel B receiver active-low ready-to-receive (RTRB

) output. When used

for RTSB

, the transmitter automatically negates OP1 by the transmitter. When used for

RTRB

, the receiver automatically negates and reasserts OP1.

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2.15.3 OP2

This output can be used as the channel A transmitter 1X-clock or 16X-clock output or the
channel A receiver 1X-clock output.

2.15.4 OP3

This output can function as the open-drain active-low counter-ready output, the open-drain
timer output, the channel B transmitter 1X-clock output, or the channel B receiver 1X-clock
output.

2.15.5 OP4

This output can serve as the channel A open-drain active-low receiver-ready or buffer-full
interrupt outputs (RxRDYA

/FFULLA) by appropriately programming bit 6 of mode

register 1A.

2.15.6 OP5

This output can be used as the channel B open-drain active-low receiver-ready or buffer-full
interrupt outputs (RxRDYB

/FFULLB) by appropriately programming bit 6 of mode

register 1B.

2.15.7 OP6

This output can function as the channel A open-drain active-low transmitter-ready interrupt
output (TxRDYA

).

2.15.8 OP7

This output can serve as the channel B open-drain active-low transmitter-ready interrupt
output (TxRDYB

).

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SECTION 3
OPERATION

3.1 TRANSMITTER

The channel A and B transmitters are enabled for data transmission through their respective
command registers (refer to Section 4 Programming and Register Descriptions ). The
DUART signals the CPU it is ready to accept a character by setting the transmitter-ready bit
in the channel’s status register. Customers can program this condition to generate an
interrupt request on the IRQ

output, an interrupt request for channel A’s transmitter on
parallel output OP6, or for channel B’s transmitter on parallel output OP7. When a character
is loaded into the transmit buffer (TB), the above conditions for the respective channel are
negated. Data is transferred from the transmit holding register to the transmit shift register
when the shift register is idle or has completed transmission of the previous character. The
transmitter ready conditions are then re-asserted, providing one full character time of
buffering. Characters cannot be loaded into the transmit buffer while the transmitter is
disabled.

The transmitter converts the parallel data from the CPU to a serial bit stream on the
transmitter serial-data output pin. It automatically sends a start bit followed by the
programmed number of data bits, an optional parity bit, and the programmed number of stop
bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output
pin on the failing edge of the programmed clock source. After the transmission of the stop
bits, if a new character is not available in the transmit holding register the transmitter
serial-data output remains high and the transmitter-empty bit in the status register (SRA and
SRB) will be set to a one. Transmission resumes and the transmitter-empty bit is cleared
when the CPU loads a new character into the transmit buffer (TBA or TBB). If the transmitter
receives a disable command, it will continue operating until the character in the transmit shift
register is completely sent out. Another character in the holding register is not sent but is not
discarded; it will be sent when the transmitter is re-enabled. The transmitter can be reset
through a software command (refer to Section 2.4 RESET ). If it is reset, operation ceases
immediately and must be enabled through the command register before resuming
operation. Reset also discards any character in the holding register.

If clear-to-send (CTS

) operation is enabled, the CTS input (alternate function of IP0 or IP1)
must be low in order for the character to be transmitted. If it goes high in the middle of a
transmission, the character in the shift register is transmitted and TxD then remains in the
marking state until CTS

again goes low. The transmitter can also be forced to send a

continuous low condition by issuing a send-break command. The state of CTS

is ignored by

the transmitter when it is to send a break.

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A send-break is deferred as long as the transmitter has characters to send, but if normal
character transmission is inhibited by CTS

, the send-break will proceed. The send-break
must be terminated by a stop-break, disable, or reset before normal character transmission
can resume.

Customers can program the transmitter to automatically negate the request-to-send (RTS)
output (alternate function of OP0 and OP1) on completion of a message transmission. If the
transmitter is programmed to operate in this manner, the RTS

output must be manually
asserted before each message is transmitted. If OP0 (or OP1) is programmed in automatic
RTS mode, the RTS

output will be automatically negated when the transmitter is disabled
and the transmit-shift register and holding register are both empty. In automatic RTS mode,
a character in the holding register is not held back by a disable, but no more characters can
be written to the holding register after the transmitter is disabled.

3.2 RECEIVER

The channel A and B receivers are enabled for data reception through the respective
channel’s command register. The channel’s receiver looks for the high-to-low (mark-to­space) transition of a start bit on the receiver serial-data input pin. If operating in 16X clock
mode, the serial input data is re-sampled on the next 7 clocks. If the receiver serial data is
sampled high, the start bit is invalid and the search for a valid start bit begins again. If
receiver serial data is still low, a valid start bit is assumed and the receiver continues to
sample the input at one bit time intervals (at the theoretical center of the bit) until the proper
number of data bits and the parity bit (if any) have been assembled and one stop bit has
been detected. Data on the receiver serial data input pin is sampled on the rising edge of
the programmed clock source.

During this process, the least-significant bit is received first. The data is then transferred to
a receive holding register (RHR) and the receiver-ready bit in the status register (SRA or
SRB) is set to a one (see Figure 3-1). This condition can be programmed to generate an
interrupt request on the IRQ

output, an interrupt request for channel A’s receiver on parallel
output OP4, or an interrupt request for channel B’s receiver on parallel output OP5. If the
character length is less than eight bits, the most significant unused bits in the receive holding
register (RHR) are set to zero.

If the stop bit is sampled as a 1, the receiver will immediately look for the next start bit.
However, if the stop bit is sampled as a 0, either a framing error or a received break has
occurred. If the stop bit is 0 and the data and parity (if any) are not all zero, it is a framing
error; the damaged character is transferred to a holding register with the framing error flag
set. If the receiver serial data remains low for one-half of the bit period after the stop bit was
sampled, the receiver operates as if a new start bit transition has been detected. If the stop
bit is 0 and the data and parity (if any) are also all zero, it is a break. A character consisting
of all zeros will be loaded into a receive holding register (RHR) with the received-break bit
(but not the framing error bit) set to a one. The receiver serial-data input must return to a
high condition for at least one-half bit time before a search for the next start bit begins.

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The receiver can detect a break that starts in the middle of a character provided the break
persists completely through the next character time or longer. When the break begins in the
middle of a character, the receiver will place the damaged character in a holding register
with the framing error bit set. Then, provided the break persists through the next character
time, the receiver will also place an all-zero character in the next holding register with the
received-break bit set.

The parity error, framing error, overrun error, and received-break conditions (if any) set error
and break flags in the status register at the received character boundary and are valid only
when the receiver-ready bit (RxRDY) in the status register is set. A first-in first-out (FIFO)
stack is used in each channel’s receive buffer logic and consists of three receive holding
registers. The receiver buffer (RBA or RBB) is composed of the FIFO and a receive shift
register connected to the receiver serial-data input. Data is assembled in the shift register
and loaded into the top-most empty FIFO receive holding register position. Thus, data
flowing from the receiver to the CPU is quadruply buffered.

The receiver-ready bit in the status register (SRA or SRB) is set whenever one or more
characters are available to be read. A read of the receiver buffer produces an output of data
from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and
its associated status bits are "popped" and new data can be added at the bottom of the stack
by the receive shift register. The FIFO-full status bit is set if all three stack positions are filled
with data. Either the receiver-ready or the FIFO-full status bits can be selected to cause an
interrupt. In addition to the data byte, three status bits (parity error, framing error, and
received break) are appended to each data character in the FIFO (overrun is not). By
programming the error-mode control bit in the channel’s mode register, status can be
provided for "character" or "block" modes.

In the "character" mode, the status register (SRA or SRB) is updated on a character-by­character basis and applies only to the character at the top of the FIFO. Thus, the status
must be read before the character is read. Reading the character pops it and its error flags
off the FIFO.

In the "block" mode, the status provided in the status register for the parity error, framing
error, and received-break conditions is the logical OR of these respective bits for all
characters coming to the top of the FIFO stack since the last reset error command was
issued. That is, beginning at the last reset-error command issued, a continuous logical-OR
function of corresponding status bits is produced in the status register as each character
comes to the top of the FIFO stack.

The block mode is useful in applications requiring the exchange of blocks of information
where the software overhead of checking each character’s error flags cannot be tolerated.
In this mode, entire messages can be received and only one data integrity check is
performed at the end of each message. Although data reception in this manner has speed
advantages, there are also disadvantages. Because each character is not individually
checked for error conditions by the software, if an error occurs within a message the error
will not be recognized until the final check is performed. Also, there is no indication of which
character(s) is in error within the message.

Operation

3-4

MC68HC681 USER’S MANUAL

MOTOROLA

3

The block mode can only be used if either (or both) of two conditions can be guaranteed:

1. The length of the block is known before the last character of the block is read, so that
the block error status can be read and cleared before reading the last character;

2. There will never be another character already present in the FIFO until the last char­acter of the message is read (leaving the FIFO empty), the status is read, and a reset
error command is issued. Otherwise, errors in the first character of the next block could
be reported erroneously on the current block, or they could be prematurely cleared and
not reported in the error status of the next block.

In either mode, reading the status register (SR) does not affect the FIFO. The FIFO is
"popped" only when the receive buffer (RBA or RBB) is read. If all three of the FIFO’s receive
holding registers are full when a new character is received, that character is held in the
receive shift register until a FIFO position is available. If an additional character is received
while this state exists, the contents of the FIFO are not affected, but the character previously
in the shift register is lost and the overrun-error status bit will be set upon receipt of the start
bit of the new overrunning character.

To support flow control, a receiver can automatically negate and reassert the ready-to­receive (RT

R) output (alternate function of parallel outputs OP0 and OP1). The RTS and

RTR

functions both use OP0 (channel A) and/or OP1 (channel B). Both functions should not
be enabled for the same channel at the same time. If programmed to operate in this mode,
the ready-to-receive output will automatically be negated by the receiver when a valid start
bit is received and the FIFO stack is full. When a FIFO position becomes available, the
ready-to-receive output will be reasserted automatically by the receiver. Connecting the
ready-to-receive output to the clear-to-send (CTS

) input of a transmitting device, prevents

overrun errors in the receiver. The RT

R output must be manually asserted the first time.

Thereafter, the receiver will control the RT

R output.

If the FIFO stack contains characters and the receiver is then disabled, the characters in the
stack can still be read but no additional characters can be received until the receiver is again
enabled. If the receiver is disabled while receiving a character, or while there is a character
in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is
reset, the FIFO stack and all of the receiver status bits, the corresponding output ports, and
the interrupt request are reset. No additional characters can be received until the receiver is
again enabled.

3.3 LOOPING MODES

Besides the normal operation mode in which the receiver and transmitter operate
independently, each DUART channel can be configured to operate in various looping modes
that are useful for local and remote system diagnostic functions. These modes are described
in the following paragraphs with additional information available in Section 4 Programming

and Register Descriptions .