Motorola MC68HC05T16, MC68HC705T16 Technical Data Manual

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Page 1

MC68HC05T16

HC05

TECHNICAL DATA

MC68HC05T16D/H

MC68HC05T16 MC68HC705T16

TECHNICAL DA TA

!MOTOROLA

Page 2

Page 3

GENERAL DESCRIPTION

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

MEMORY AND REGISTERS

RESETS AND INTERRUPTS

TIMERS

M-BUS SERIAL INTERFACE

PULSE ACCUMULATOR

PULSE WIDTH MODULATOR

2 3 4 5 6 7 8

ON-SCREEN DISPLAY

ANALOG TO DIGITAL CONVERTER

CPU CORE AND INSTRUCTION SET

LOW POWER MODES

OPERATING MODES

ELECTRICAL SPECIFICATIONS

MECHANICAL SPECIFICATIONS

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9 10 11 12 13 14 15

Page 4

GENERAL DESCRIPTION

2 3 4 5 6 7 8

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

MEMORY AND REGISTERS

RESETS AND INTERRUPTS

TIMERS

M-BUS SERIAL INTERFACE

PULSE ACCUMULATOR

PULSE WIDTH MODULATOR

9 10 11 12 13 14 15

ON-SCREEN DISPLAY

ANALOG TO DIGITAL CONVERTER

CPU CORE AND INSTRUCTION SET

LOW POWER MODES

OPERATING MODES

ELECTRICAL SPECIFICATIONS

MECHANICAL SPECIFICATIONS

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Page 5

MC68HC05T16

MC68HC705T16

High-density complementary

metal oxide semiconductor

(HCMOS) microcontroller unit

All Trade Marks recognized. This document contains information on new products. Speciﬁcations and information herein are subject to change without notice.

All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available on request.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.



MOTOROLA LTD., 1996

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Conventions

Register and bit mnemonics are deﬁned in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET Unless otherwise stated, blank cells in a register diagram indicate that the bit is

either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; ‘u’ is used to indicate an undeﬁned state (on reset).

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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05T16D/H)

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SECTION 1 GENERAL DESCRIPTION

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SECTION 2 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS SECTION 3 MEMORY AND REGISTERS SECTION 4 RESETS AND INTERRUPTS SECTION 5 TIMERS SECTION 6 M-BUS SERIAL INTERFACE SECTION 7 PULSE ACCUMULATIOR SECTION 8 PULSE WIDTH MODULATION SECTION 9 ON-SCREEN DISPLAY SECTION 10 ANALOG TO DIGITAL CONVERTER SECTION 11 CPU CORE AND INSTRUCTION SET SECTION 12 LOW POWER MODES SECTION 13 OPERATING MODES SECTION 14 ELECTRICAL SPECIFICATIONS SECTION 15 MECHANICAL SPECIFICATIONS

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!MOTOROLA

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Paragraph Number

GENERAL DESCRIPTION

1.1 Features.................................................................................................................1-1

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

2.1 PIN DESCRIPTIONS.............................................................................................2-1

2.1.1 Pin Assignments..............................................................................................2-3

2.2 INPUT/OUTPUT PORTS.......................................................................................2-4

2.2.1 Input/Output Programming...............................................................................2-4

2.2.2 Port E and F Conﬁguration Registers..............................................................2-4

MEMORY AND REGISTERS

3.1 Memory Map..........................................................................................................3-1

3.2 Input/Output Section..............................................................................................3-1

3.3 RAM.......................................................................................................................3-1

Page

NumberTITLE

RESETS AND INTERRUPTS

4.1 RESETS ................................................................................................................4-1

4.1.1 Power-On Reset (POR)....................................................................................4-1

4.1.2 RESET

4.1.3 Computer Operating Properly (COP) Reset ....................................................4-2

4.2 INTERRUPTS........................................................................................................4-4

4.2.1 Hardware Controlled Sequences.....................................................................4-5

4.2.2 Software Interrupt (SWI)..................................................................................4-6

4.2.3 External Interrupt (IRQ

4.2.4 Programmable Timer Interrupt.........................................................................4-8

MC68HC05T16 MOTOROLA

Pin.......................................................................................................4-1

) ...................................................................................4-6

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Paragraph Number

4.2.5 M-Bus Interrupts..............................................................................................4-8

4.2.6 PAC Interrupt....................................................................................................4-10

4.2.7 OSD Interrupts.................................................................................................4-10

4.2.8 Multi-Function Timer Interrupts........................................................................4-11

TIMERS

5.1 PROGRAMMABLE TIMER....................................................................................5-1

5.1.1 Counter............................................................................................................5-3

5.1.2 Output Compare Registers..............................................................................5-3

5.1.3 Input Capture Registers...................................................................................5-4

5.1.4 Timer Control Register (TCR)..........................................................................5-5

5.1.5 Timer Status Register (TSR) ...........................................................................5-6

5.1.6 Programmable Timer Timing Diagrams ...........................................................5-7

5.2 MUL TI-FUNCTION TIMER....................................................................................5-10

5.2.1 COP Watchdog Reset......................................................................................5-11

M-BUS SERIAL INTERFACE

6.1 M-Bus Interface Features......................................................................................6-1

6.2 M-Bus Protocol......................................................................................................6-2

6.2.1 START Signal...................................................................................................6-3

6.2.2 Slave Address Transmission............................................................................6-3

6.2.3 Data T r ansfer....................................................................................................6-4

6.2.4 Repeated START Signal..................................................................................6-4

6.2.5 STOP Signal....................................................................................................6-4

6.2.6 Arbitration Procedure.......................................................................................6-4

6.2.7 Clock Synchronization.....................................................................................6-5

6.2.8 Handshaking....................................................................................................6-5

6.3 M-Bus Registers....................................................................................................6-5

6.3.1 M-Bus Address Register (MADR)....................................................................6-6

6.3.2 M-Bus Clock Register (MCKR)........................................................................6-6

6.3.3 M-Bus Control Register (MCR)........................................................................6-7

6.3.4 M-Bus Status Register (MSR) .........................................................................6-8

6.3.5 M-Bus Data I/O Register (MDR)......................................................................6-9

Page

NumberTITLE

PULSE ACCUMULATOR

7.1 Pulse Accumulator Registers ................................................................................7-1

7.1.1 PAC Control and Status Register (PACTL) ......................................................7-1

MOTOROLA ii

MC68HC05T16

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Paragraph Number

7.1.2 PAC Counter Register......................................................................................7-2

PULSE WIDTH MODULATOR

8.1 7-Bit PWM Channels .............................................................................................8-1

8.2 14-BIT PWM Channel............................................................................................8-2

ON-SCREEN DISPLAY

9.1 Introduction............................................................................................................9-1

9.2 Features.................................................................................................................9-2

9.3 Characters.............................................................................................................9-3

9.3.1 Character RAM................................................................................................9-3

9.3.2 Character ROM/EPROM..................................................................................9-3

9.3.3 Character Registers.........................................................................................9-5

9.3.4 Color Palette Registers....................................................................................9-6

9.4 Row........................................................................................................................9-7

9.4.1 Row Attribute Register.....................................................................................9-7

9.4.2 Row Vertical Position Registers .......................................................................9-8

9.4.3 Row Horizontal Position Register.....................................................................9-12

9.4.4 Row Control Register 1....................................................................................9-12

9.4.5 Row Control Register 2....................................................................................9-13

9.5 Frame ....................................................................................................................9-13

9.5.1 Frame Control 1 and Row Count Register.......................................................9-14

9.5.2 Frame Control Register 2.................................................................................9-15

9.5.3 Frame Control 3 and Status Register...............................................................9-17

Page

NumberTITLE

ANALOG TO DIGITAL CONVERTER

10.1 ADC Inputs ..........................................................................................................10-2

10.1.1 PF4/ADCIN1..................................................................................................10-2

10.1.2 ADCIN0..........................................................................................................10-2

10.2 Program Example................................................................................................10-2

10.3 ADC Control and Status Register........................................................................10-3

CPU CORE AND INSTRUCTION SET

11.1 Registers .............................................................................................................11-1

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MC68HC05T16 MOTOROLA

iii

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Paragraph Number

11.1.1 Accumulator (A).............................................................................................11-1

11.1.2 Index register (X)...........................................................................................11-2

11.1.3 Program counter (PC)....................................................................................11-2

11.1.4 Stack pointer (SP)..........................................................................................11-2

11.1.5 Condition code register (CCR).......................................................................11-2

11.2 Instruction set......................................................................................................11-3

11.2.1 Register/memory Instructions........................................................................11-4

11.2.2 Branch instructions........................................................................................11-4

11.2.3 Bit manipulation instructions..........................................................................11-4

11.2.4 Read/modify/write instructions.......................................................................11-4

11.2.5 Control instructions........................................................................................11-4

11.2.6 Tables.............................................................................................................11-4

11.3 Addressing modes...............................................................................................11-11

11.3.1 Inherent..........................................................................................................11-11

11.3.2 Immediate......................................................................................................11-11

11.3.3 Direct .............................................................................................................11-11

11.3.4 Extended........................................................................................................11-12

11.3.5 Indexed, no offset..........................................................................................11-12

11.3.6 Indexed, 8-bit offset.......................................................................................11-12

11.3.7 Indexed, 16-bit offset.....................................................................................11-12

11.3.8 Relative..........................................................................................................11-13

11.3.9 Bit set/clear....................................................................................................11-13

11.3.10 Bit test and branch.........................................................................................11-13

Page

NumberTITLE

LOW POWER MODES

12.1 Stop Mode...........................................................................................................12-1

12.1.1 Timer during Stop Mode................................................................................12-1

12.1.2 M-Bus during Stop Mode...............................................................................12-2

12.1.3 Pulse Accumulator during Stop Mode ...........................................................12-2

12.1.4 PWM during Stop Mode.................................................................................12-2

12.1.5 OSD during Stop Mode..................................................................................12-2

12.1.6 ADC during Stop Mode..................................................................................12-2

12.1.7 COP during Stop Mode..................................................................................12-2

12.2 Wait Mode ...........................................................................................................12-3

OPERATING MODES

13.1 User Mode (Normal Operation)...........................................................................13-2

13.2 Self-Check Mode.................................................................................................13-2

13.3 Bootstrap Mode...................................................................................................13-4

13.3.1 EPROM Programming...................................................................................13-4

MOTOROLA iv

MC68HC05T16

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Page 13

Paragraph Number

13.3.2 Program Control Register (PCR)...................................................................13-4

13.3.3 EPROM Programming Sequence..................................................................13-5

ELECTRICAL SPECIFICATIONS

14.1 Maximum Ratings................................................................................................14-1

14.2 Thermal Characteristics.......................................................................................14-1

14.3 DC Electrical Characteristics...............................................................................14-2

14.4 Open Drain Electrical Speciﬁcation .....................................................................14-3

14.5 On-Screen Display Timing...................................................................................14-3

14.6 M-Bus Interface Timing .................................................................................14-4

14.7 Control Timing .....................................................................................................14-5

MECHANICAL SPECIFICATIONS

15.1 56-pin SDIP Package...........................................................................................15-1

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MC68HC05T16 MOTOROLA

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MOTOROLA vi

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MC68HC05T16

Page 15

LIST OF FIGURES

Figure Number

1-1 MC68HC05T16/MC68HC705T16 Block Diagram..................................................1-2

2-1 Pin Assignments for 56-pin SDIP package.............................................................2-3

2-2 Parallel Port I/O Circuitry........................................................................................2-5

3-1 MC68HC05T16/MC68HC705T16 Memory Map ....................................................3-2

4-1 Power-On Reset and RESET

4-2 Interrupt Stacking Order.........................................................................................4-4

4-3 External Interrupt Circuit and Timing......................................................................4-7

5-1 Programmable Timer Block Diagram......................................................................5-2

5-2 Timer State Timing Diagram for Reset ...................................................................5-8

5-3 Timer State Timing Diagram for Input Capture.......................................................5-8

5-4 Timer State Timing Diagram for Output Compare ..................................................5-9

5-5 Timer State Diagram for Timer Overﬂow ................................................................5-9

6-1 M-Bus Interface Block Diagram..............................................................................6-2

6-2 M-Bus Transmission Signal Diagram......................................................................6-3

6-3 Clock Synchronization............................................................................................6-5

8-1 7-Bit PWM Output Waveform..................................................................................8-2

8-2 14-Bit PWM Output Waveform................................................................................8-3

9-1 OSD Character and Row Structure........................................................................9-4

9-2 Reserved Character ROM Codes...........................................................................9-5

9-3 Color Palette Organization......................................................................................9-6

9-4 Output Signal Timing Diagram - Without Background ............................................9-10

9-5 Output Signal Timing Diagram - With Background .................................................9-11

9-6 Resolution of Overlap among Rows.......................................................................9-11

9-7 Fading Out Sequence.............................................................................................9-16

10-1 ADC Block Diagram..............................................................................................10-1

11-1 Programming model.............................................................................................11-1

11-2 Stacking order ......................................................................................................11-2

13-1 Flowchart of Mode Entering .................................................................................13-1

13-2 Self-Check Mode Timing......................................................................................13-2

13-3 MC68HC05T16 Self-Test Circuit ..........................................................................13-3

14-1 M-Bus Timing Diagram.........................................................................................14-4

15-1 56-pin SDIP Mechanical Dimensions...................................................................15-1

Timing......................................................................4-3

NumberTITLE

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MC68HC05T16 MOTOROLA

vii

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MOTOROLA viii

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MC68HC05T16

Page 17

LIST OF TABLES

Table Number

2-1 I/O Pin Functions....................................................................................................2-4

3-1 MC68HC05T16/MC68HC705T16 Registers ..........................................................3-3

4-1 Reset Action on Internal Circuit..............................................................................4-2

4-2 Reset/Interrupt Vector Addresses..........................................................................4-5

5-1 COP Reset and RTI Rates.....................................................................................5-11

6-1 M-Bus Prescaler.....................................................................................................6-6

9-1 RGB Color Map......................................................................................................9-7

9-2 Number of Visible Characters Per Row..................................................................9-14

11-1 MUL instruction.....................................................................................................11-5

11-2 Register/memory instructions...............................................................................11-5

11-3 Branch instructions...............................................................................................11-6

11-4 Bit manipulation instructions.................................................................................11-6

11-5 Read/modify/write instructions .............................................................................11-7

11-6 Control instructions...............................................................................................11-7

11-7 Instruction set.......................................................................................................11-8

11-8 M68HC05 opcode map.........................................................................................11-10

13-1 Mode Selection.....................................................................................................13-2

13-2 Self-Check Report................................................................................................13-4

14-1 DC Electrical Characteristics for 5V Operation.....................................................14-2

14-2 Open Drain Parameters........................................................................................14-3

14-3 On-Screen Display Timings..................................................................................14-3

14-4 M-Bus Interface Input Signal Timing.....................................................................14-4

14-5 M-Bus Interface Output Signal Timing..................................................................14-4

14-6 Control Timing for 5V Operation...........................................................................14-5

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MC68HC05T16 MOTOROLA

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MC68HC05T16

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GENERAL DESCRIPTION

The MC68HC05T16 HCMOS microcontroller is a member of the M68HC05 Family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, OSD, M-Bus, PWM, PAC, Timer, A/D converter, I/O and Watchdog Timer.

The MC68HC705T16 is an EPROM version of the MC68HC05T16; it is av ailable in windo wed and OTP 56-pin SDIP packages. All references to the MC68HC05T16 apply equally to the MC68HC705T16, unless otherwise stated.

italicized in the text.

1.1 Features

• 8-bit architecture

References speciﬁc to the MC68HC705T16 are

• Power saving Stop, Wait modes

• 320 bytes of on-chip RAM (64 bytes for stack)

• 24064 bytes of on-chip ROM/

• PLL-based, 4-row-buffer On Screen Display (OSD)

• 128-character (4K bytes) OSD ROM/

• 16-character (512 bytes) dual ported OSD RAM; both readable and writable by CPU

• 40 bidirectional I/O lines: 24 dedicated and 16 multiplexed I/O lines; 12 of the 24 dedicated I/Os and 10 of the 16 multiplexed I/Os are of +12V open-drain type

• Multi-master M-Bus (I

• Timer with TCAP input pin and 2 output compare functions

• Pulse Accumulator (PAC)

• 9 channel 7-bit PWM, and single channel 14-bit PWM

• 2 channel 5-bit Analog to Digital Converter

• COP watchdog system

• Available in 56-pin SDIP package

† I

C-bus is a proprietary Philips interface bus

MC68HC05T16 MOTOROLA

EPROM

C†) interface system

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GENERAL DESCRIPTION

1-1

Page 20

IRQ

RESET

EXTAL

XTAL

VDD

VSS

VCO

HFLBK

FBKG

VFLBK

USER ROM/

SELF-CHECK/

M68HC05

CPU

15 4

OSC

÷ 2

POWER

OSD

PLL

BOOTSTRAP

RAM - 320 BYTES

000

EPROM

- 23.5K BYTES

ROM - 496 BYTES

0000011

PROGRAM COUNTER

CONDITION CODE REGISTER

COP

SYSTEM

OSD

CHAR.

ROM

ACCUMULATOR

INDEX REGISTER

STACK POINTER

HINZC

MULTI

FUNCTION

TIMER

OSD

CHAR.

RAM

OSD

7-BIT PWM

5-BIT

A/D

MBUS

PAC

16-BIT TIMER

DDR A

PORT A

DDR B

PORT B

DDR C

PORT C

DDR E

PORT E

DDR F

PORT F

*12V open-drain

TCAP

PA0 - PA7

PB0* - PB7*

PC0 - PC3

PC4* - PC7*

PE0/ PWM0* PE1/PWM1* PE2/ PWM2* PE3/ PWM3* PE4/ PWM4* PE5/ PWM5* PE6/ PWM6* PE7/ PWM7*

ADCIN0

PF0/ PWM8*

PF1/PWM9*

PF2/I

PF3/ HTONE

PF4/ ADCIN1

PF5/SDA

PF6/ SCL

PF7/ PACIN

MOTOROLA 1-2

Figure 1-1 MC68HC05T16/

MC68HC705T16

Block Diagram

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MC68HC05T16GENERAL DESCRIPTION

Page 21

PIN DESCRIPTIONS AND

INPUT/OUTPUT PORTS

This section provides a description of the functional pins and I/O programming of the MC68HC05T16/

2.1 PIN DESCRIPTIONS

MC68HC705T16

microcontroller.

PIN NAME

VDD, VSS 41, 44

IRQ/VPP 38

RESET 53

TCAP 15

EXTAL, XTAL 51, 52

PA0-PA7 31-24

PB0-PB7 16-23

56-pin SDIP

PIN No.

DESCRIPTION

Power is supplied to the MCU using these two pins. VDD is power and VSS is ground.

In the user mode this pin is an external hardware interrupt IRQ. It is software programmable to provide two choices of interrupt triggering sensitivity. These options are:

1) negative edge-sensitive triggering only, or

2) both negative edge-sensitive and level sensitive triggering.

In the bootstrap mode on the MC68HC705T16, this is the EPROM programming voltage input pin.

The active low RESET input is not required for start-up, but can be used to reset the MCU internal state and provide an orderly software start-up procedure.

The TCAP input controls the input capture feature for the on-chip programmable free-running timer.

These pins provide connections to the on-chip oscillator. The maximum crystal frequency is 4.2 MHz. EXTAL may be driven by an external oscillator if an external crystal circuit is not used.

These eight I/O lines comprise port A. The state of any pin is software programmable. All port A lines are conﬁgured as input during power on or external reset.

These eight I/O lines comprise port B. The state of any pin is software programmable. All port B lines are conﬁgured as input during power on or external reset. These pins are +12V open-drain pins.

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MC68HC05T16 MOTOROLA

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

2-1

Page 22

PIN NAME

PC0-PC7 40, 39, 37-32

PE0/PWM0 to PE7/PWM7

PF0-PF7 6-13

PWM8, PWM9 6, 7

I, TONE 8. 9

ADCIN0, ADCIN1 14, 10

SDA, SCL 11, 12

PACIN 13

R, G, B 50, 49, 48 These are the output pins for OSD R, G, and B videos.

FBKG 47

HFBLK, VFBLK 45, 46

VCO 43

RP 42 This is an input pin for biasing the internal OSD VCO.

56-pin SDIP

PIN No.

54, 55,56, 1

2, 3, 4, 5

DESCRIPTION

These eight I/O lines comprise port C. The state of any pin is software programmable. All port C lines are conﬁgured as input during power on or external reset. PC0-3 are push-pull type pins, and PC4-7 are +12V open-drain pins.

These eight I/O lines comprise port E. The state of any pin is software programmable. All port E lines are conﬁgured as input during power on or external reset. These pins become PWM outputs by setting the appropriate bits in the port E Conﬁguration register ($0C). See Section 2.2.2.

These eight I/O lines comprise port F. The state of any pin is software programmable. All port F lines are conﬁgured as input during power on or external reset. Other functions are also shared with these pins, and is selected by setting the appropriate bits in the port F Conﬁguration register ($0D). See Section 2.2.2.

PWM channels. These pins are shared with port pins PF0 and PF1, and are selected by setting port F Conﬁguration register ($0D) bits 0 and 1 respectively.

The I pin of the OSD module expands the color selection range by providing an intensity bit. The HTONE pin is mainly used for creating transparent background effect when the background of a character window overlaps the original TV picture display. These pins are shared with port pins PF2 and PF3.Selection is by the port F Conﬁguration register ($0D) bits 2 and 3 respectively.

These are the two input channels to the analog to digital converter. ADCIN1 pin is shared with port PF4, and is selected by setting the port F Conﬁguration register ($0D) bit 4.

These two pins are the M-Bus interface pins. SDA is the data line, and SCL is the clock line. These pins are shared with port pins PF5 and PF6 respectively. Selection is by the port F Conﬁguration register ($0D) bits 5 and 6.

This is the clock/control input to the pulse accumulator. This pin is shared with port pin PF7. Selection is by the port F Conﬁguration register ($0D) bit 7.

This is the OSD output pin for blanking out the original TV picture display so that OSD data can be displayed on the TV screen.

These are the OSD input pins for horizontal and vertical ﬂyback signals from the TV set chassis. They are used for synchronizing OSD signals with TV display.

This OSD pin is the phase detector output pin. With a low-pass ﬁlter this pin controls the frequency of the internal OSD VCO.

MOTOROLA 2-2

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MC68HC05T16PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

Page 23

2.1.1 Pin Assignments

PE3/PWM3 PE4/PWM4 PE5/PWM5 PE6/PWM6 PE7/PWM7

PF0/PWM8 PF1/PWM9

PF3/HTONE PF4/ADCIN1

PF5/SDA

PF6/SCL

PF7/PACIN

ADCIN0

Figure 2-1 Pin Assignments for 56-pin SDIP package

PF2/I

TCAP

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA 7 PA 6 PA 5 PA 4 PA 3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

PE2/PWM2 PE1/PWM1 PE0/PWM0 RESET XTAL EXTAL R G B FBKG VFLBK HFLBK VSS VCO RP VDD PC0 PC1 IRQ

VPP

PC2 PC3 PC4 PC5 PC6 PC7 PA 0 PA 1 PA 2

TPG

MC68HC05T16 MOTOROLA

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

2-3

Page 24

2.2 INPUT/OUTPUT PORTS

2.2.1 Input/Output Programming

Port A, B, C, E, and F may be programmed as an input or an output under software control. The direction of the pins is determined by the state of corresponding bit in the port data direction register (DDR). Each 8-bit port has an associated 8-bit data direction register. Any port A, B, C, E, or F pin is conﬁgured as an output if its corresponding DDR bit is set to a logic one. A pin is conﬁgured as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or reset, all DDRs are cleared, which conﬁgure all port A, B, C, E and F pins as inputs. The data direction registers are capable of being written to or read by the processor. Refer to Figure 2-2 and T ab le 2-1. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin.

Table 2-1 I/O Pin Functions

R/W DDR I/O Pin Function

0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is in an output mode. The output data latch is read.

2.2.2 Port E and F Conﬁguration Registers

Port E and F are shared with PWM, PAC, OSD, MBUS, and ADC. The conﬁguration registers, at $0C and $0D, are used to conﬁgure these I/O pins . The default state after a reset or POR is zero. Setting the corresponding bits will enable the corresponding functions. For example, setting the SDA and SCL bits will conﬁgure PF5 and PF6 as MBUS interf ace pins, regardless of the settings in the port F Data Direction register.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Port E Conﬁguration Register $0C PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 0000 0000

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Port F Conﬁguration Register $0D PAC SCL SDA ADC1 HTONE I PWM9 PWM8 0000 0000

MOTOROLA 2-4

State

on reset

State

on reset

MC68HC05T16PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

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Page 25

DATA DIRECTION

INTERNAL

MC68HC05

CONNECTIONS

TYPICAL PORT

DATA DIRECTION REGISTER

TYPICAL PORT REGISTER

I/ O PORT LINES

PORT DATA

PORT DDR

LATCHED OUTPUT

DATA BIT

INPUT

BIT

INPUT I/ O

OUTPUT

(a)

234567

DDR 7 DDR 6 DDR 5 DDR 4 DDR 3 DDR 2 DDR 1 DDR 0

Px7 Px6 Px5 Px4

Px3 Px2

(b)

NOTE:

(1) IP = INPUT PROTECTION (2) LATCH-UP PROTECTION NOT SHOWN

PAD

I/ O PIN

Px1 Px0

INTERNAL LOGIC

(c)

Figure 2-2 Parallel Port I/O Circuitry

TPG

MC68HC05T16 MOTOROLA

PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

2-5

Page 26

THIS PAGE LEFT BLANK INTENTIONALLY

MOTOROLA 2-6

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MC68HC05T16PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS

Page 27

MEMORY AND REGISTERS

This section describes the organization of the on-chip memory.

3.1 Memory Map

The CPU can address 64K-bytes of memory space. The ROM portion of memory holds the program instructions, ﬁxed data, user-deﬁned vectors, and interrupt service routines. The RAM portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 3-1 shows the Memory Map for the MC68HC05T16/

3.2 Input/Output Section

The ﬁrst 64 addresses of memory space, $0000-$003F, are the I/O section. These are the addresses of the I/O control registers, status registers, and data registers. Tab le 3-1 shows these registers and their respective bits.

MC68HC705T16

3.3 RAM

The 320 addresses from $0050-$018F are RAM locations. The CPU uses the 64 RAM addresses, $00C0-$00FF, as the stack. Before processing an interrupt, the CPU uses ﬁve bytes of the stack to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.

Note:

MC68HC05T16 MOTOROLA

Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Once the stack pointer passes $00C0, it wraps round back to $00FF.

TPG

MEMORY AND REGISTERS

3-1

Page 28

$0000

$003F

$0050

$00C0

$00FF $018F

$0200 $02FF

$0400

$05FF

$8000

$8FFF

$A000

$FDFF

$FE00

$FFDF

$FFE0

$FFEF $FFF0

$FFFF

I/O

64 Bytes

Reserved

RAM

320 Bytes

Stack

Reserved

OSD RAM 256 Bytes

Reserved

OSD Character RAM

512 Bytes

Reserved

OSD Character

EPROM

ROM/

4096 Bytes

Reserved

User ROM/

EPROM

23.5K Bytes

Self-Check/

Bootstrap

Program

496 Bytes

Self-Check/

Bootstrap

Vectors

16 Bytes

User Vectors

16 Bytes

$FFF0 $FFF2 $FFF4 $FFF6 $FFF8 $FFFA $FFFC $FFFE

Por ts

14 Bytes

PAC

2 Bytes

Timer

12 Bytes

MFT

1 Byte

OSD

15 Bytes

PWM

11 Bytes

M-BUS 5 Bytes

ADC

1 Byte

EPROM PCR

1 Byte

RESERVED

2 Bytes

MFT

PAC M-BUS TIMER

IRQ

OSD

SWI RESET

Port A Data Register Port B Data Register

Port C Data Register

Reserved Port E Data Register Port F Data Register

Port A Direction Register Port B Direction Register Port C Direction Register

Reserved

Port E Direction Register

Port F Direction Register Port E Conﬁguration Register Port F Conﬁguration Register

PAC Control and Status Register

PAC Data Register

Timer Control Register

Timer Status Register Timer Input Capture High Register Timer Input Capture Low Register

Timer Output Compare 0 High Register Timer Output Compare 0 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register

Timer Counter High Register Timer Counter Low Register

Timer Alternative Counter High Register

Timer Alternative Counter Low Register

MFT Control and Status Register

OSD Frame Control 1 and Row Count Register

OSD Frame Control 2 Register

OSD Color Palette 1 Register OSD Color Palette 2 Register OSD Color Palette 3 Register OSD Color Palette 4 Register

OSD Row Attribute Register OSD Row 0 Vertical Position Register OSD Row 1 Vertical Position Register OSD Row 2 Vertical Position Register OSD Row 3 Vertical Position Register

OSD Row Horizontal Position Register

OSD Row Control 1 Register OSD Row Control 2 Register

OSD Frame Control 3 and Status Register

PWM0 Register PWM1 Register PWM2 Register PWM3 Register PWM4 Register PWM5 Register PWM6 Register PWM7 Register

PWM8 Register PWM9L Register PWM9H Register

M-Bus Address Register

M-Bus Clock Register

M-Bus Control Register

M-Bus Status Register

M-Bus Data Register

ADC Control and Status Register

ERPOM Programming Control Register

Reserved Reserved

$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D

$1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B

$2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D

$3E $3F

MOTOROLA 3-2

Figure 3-1 MC68HC05T16/

MC68HC705T16

Memory Map

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MC68HC05T16MEMORY AND REGISTERS

Page 29

Table 3-1 MC68HC05T16/

Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00 Port A data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01 Part B data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02 Port C data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $03 Reserved $04 Port E data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $05 Port F data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $06 Port A data direction DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 $07 Port B data direction DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 $08 Port C data direction DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 $09 Reserved $0A Port E data direction DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 $0B Port F data direction DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 $0C Port E conﬁguration PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 $0D Port F conﬁguration PAC SCL SDA ADC1 HTONE I PWM9 PWM8 $0E PAC control and status PAOF PAEN PAMOD PAIE $0F PAC data PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 $10 Timer control ICIE OC0IE OC1IE TOVFIE IEDG $11 Timer status ICF OC0F OC1F TOF TCAPS $12 Timer input capture high CAP7H CAP6H CAP5H CAP4H CAP3H CAP2H CAP1H CAP0H $13 Timer input capture low CAP7L CAP6L CAP5L CAP4L CAP3L CAP2L CAP1L CAP0L $14 Timer output compare 0 high $15 Timer output compare 0 low $16 Timer output compare 1 high $17 Timer output compare 1 low $18 Timer counter high CNT7H CNT6H CNT5H CNT4H CNT3H CNT2H CNT1H CNT0H $19 Timer counter low CNT7L CNT6L CNT5L CNT4L CNT3L CNT2L CNT1L CNT0L $1A Timer alternate counter high $1B Timer alternate counter low $1C MFT control and status TOF RTIF TOFIE RTIE IRQN WDOG RT1 RT0 $1D OSD frame control 1 and row count PLLEN DSCAN FADE ON/OFF CDRC3 CDRC2 CDRC1 CDRC0 $1E OSD frame control 2 BR1 BR0 VFPOL HFPOL HTPOL FBPOL $1F OSD color palette 1 I1 R1 G1 B1 I0 R0 G0 B0

0CMP7H 0CMP6H 0CMP5H 0CMP4H 0CMP3H 0CMP2H 0CMP1H 0CMP0H 0CMP7L 0CMP6L 0CMP5L 0CMP4L 0CMP3L 0CMP2L 0CMP1L 0CMP0L 1CMP7H 1CMP6H 1CMP5H 1CMP4H 1CMP3H 1CMP2H 1CMP1H 1CMP0H 1CMP7L 1CMP6L 1CMP5L 1CMP4L 1CMP3L 1CMP2L 1CMP1L 1CMP0L

ACNT7H ACNT6H ACNT5H ACNT4H ACNT3H ACNT2H ACNT1H ACNT0H

ACNT7L ACNT6L ACNT5L ACNT4L ACNT3L ACNT2L ACNT1L ACNT0L

MC68HC705T16

Registers

RGBPOL

IPOL

TPG

MC68HC05T16 MOTOROLA

MEMORY AND REGISTERS

3-3

Page 30

Table 3-1 MC68HC05T16/

Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$20 OSD color palette 2 I3 R3 G3 B3 I2 R2 G2 B2 $21 OSD color palette 3 I5 R5 G5 B5 I4 R4 G4 B4 $22 OSD color palette 4 I7 R7 G7 B7 I6 R6 G6 B6 $23 OSD row attribute MTRX3 MTRX2 MTRX1 MTRX0 R3BE R2BE R1BE R0BE $24 OSD row 0 vertical position $25 OSD row 1 vertical position $26 OSD row 2 vertical position FBKGC2 R2VP6 R2VP5 R2VP4 R2VP3 R2VP2 R2VP1 R2VP0 $27 OSD row 3 vertical position FBKGC3 R3VP6 R3VP5 R3VP4 R3VP3 R3VP2 R3VP1 R3VP0 $28 OSD row horizontal position SHDW HP6 HP5 HP4 HP3 HP2 HP1 HP0 $29 OSD row control 1 R3INTE R2INTE R1INTE R0INTE R3EN R2EN R1EN R0EN $2A OSD row control 2 $2B OSD frame control 3 and status VFINTE MUTE1 MUTE0 VFLB R3CF R2CF R1CF R0CF $2C PWM0 0PWM6 0PWM5 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 $2D PWM1 1PWM6 1PWM5 1PWM4 1PWM3 1PWM2 1PWM1 1PWM0 $2E PWM2 2PWM6 2PWM5 2PWM4 2PWM3 2PWM2 2PWM1 2PWM0 $2F PWM3 3PWM6 3PWM5 3PWM4 3PWM3 3PWM2 3PWM1 3PWM0 $30 PWM4 4PWM6 4PWM5 4PWM4 4PWM3 4PWM2 4PWM1 4PWM0 $31 PWM5 5PWM6 5PWM5 5PWM4 5PWM3 5PWM2 5PWM1 5PWM0 $32 PWM6 6PWM6 6PWM5 6PWM4 6PWM3 6PWM2 6PWM1 6PWM0 $33 PWM7 7PWM6 7PWM5 7PWM4 7PWM3 7PWM2 7PWM1 7PWM0 $34 PWM8 8PWM6 8PWM5 8PWM4 8PWM3 8PWM2 8PWM1 8PWM0 $35 PWM9L 9PWM5 9PWM4 9PWM3 9PWM2 9PWM1 9PWM0 $36 PWM9H $37 MB address ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 $38 MB clock MBC4 MBC3 MBC2 MBC1 MBC0 $39 MB control MEM MIEM MSTR XMT ACKEB $3A MB status MCF SELTED BBSY ALOST SRW MIF $3B MB data MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 $3C ADC control and status RESULT CHNL AD4 AD3 AD2 AD1 AD0 $3D $3E Reserved $3F Reserved

EPROM programming control

FBKGC0 FBKGC1

R3CHS1 R3CHS0 R2CHS1 R2CHS0 R1CHS1 R1CHS0 R0CHS1 R0CHS0

9PWM13 9PWM12 9PWM11 9PWM10

MC68HC705T16

R0VP6 R0VP5 R0VP4 R0VP3 R0VP2 R0VP1 R0VP0 R1VP6 R1VP5 R1VP4 R1VP3 R1VP2 R1VP1 R1VP0

Registers

9PWM9 9PWM8 9PWM7 9PWM6

RXACKB

ELAT PGM

MOTOROLA 3-4

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MC68HC05T16MEMORY AND REGISTERS

Page 31

RESETS AND INTERRUPTS

4.1 RESETS

The MC68HC05T16 can be reset in three ways: b y the initial power-on reset function, b y an active low input to the RESET will cause the program to go to its starting address, speciﬁed by the contents of memory locations $FFFE and $FFFF, and cause the interrupt mask of the Condition Code register to be set.

4.1.1 Power-On Reset (POR)

The power-on reset occurs when a positive transition is detected on the supply voltage, VDD. The power-on reset is used strictly for power-up conditions , and should not be used to detect any drops in the power supply voltage. There is no provision for a power-down reset. The power-on circuitry provides for a 4064 tcyc delay from the time that the oscillator becomes active. If the external RESET

pin is low at the end of the 4064 tcyc time out, the processor remains in the reset condition until RESET operate properly prior to the time the 4064 POR cycles have elapsed. If there is doubt, the external RESET speciﬁed.

goes high. The user must ensure that VDD has risen to a point where the MCU can

pin should remain low until such time that VDD has risen to the minimum operating voltage

pin, and by a COP watchdog timer reset (if enabled). Any of these resets

4.1.2 RESET Pin

The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure. When using the external reset, the RESET RESET

pin contains an internal Schmitt Trigger as part of its input to improve noise immunity.

MC68HC05T16 MOTOROLA

RESETS AND INTERRUPTS

pin must stay low for a minimum of 1.5tcyc. The

TPG

4-1

Page 32

4.1.3 Computer Operating Properly (COP) Reset

The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a speciﬁc amount of time by a program reset sequence.

Note:

COP time-out is prevented by periodically writing a ‘0’ to bit 0 of address $FFF0.

If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Because the internal reset signal is used, the MCU comes out of a COP reset in the same operating mode it was in when the COP time-out was generated.

The watchdog timer is initially disabled after a reset, it is enabled by setting the WDOG bit in the Multi-Function Timer register (writing a ‘1’ to bit 2 of address $1C); see Section 5.2 for more details. Once enabled, it cannot be disabled by software.

Table 4-1 shows the internal circuit actions on reset, but not necessary in order of occurrence.

Table 4-1 Reset Action on Internal Circuit

DEFAULT CONDITIONS AFTER RESET

1 Timer prescaler reset to zero state 2 Timer counter conﬁgures to $FFFC 3 All timer interrupt enable bits cleared (ICIE, OC0IE, OC1IE, and TOVFIE) to disable timer interrupt 4 All data direction registers cleared to zero (default to inputs) 5 Port E and port F conﬁgured as general purpose I/O ports 6 Conﬁgure stack pointer to $00FF 7 Force internal address bus to the address of reset vector ($FFFE) 8 Set interrupt mask bit (I bit) in condition code register to logic one

9 Clear Stop latch 10 Clear Wait latch 11 Clear all interrupt enable bits 12 COP watchdog timer reset 13 COP watchdog disabled 14 Initialize M-Bus registers 15 Initialize PWM registers 16 Initialize PAC registers 17 OSD disabled, all registers initialized to default values

Listed numbers do not represent order of occurrence.

MOTOROLA 4-2

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MC68HC05T16RESETS AND INTERRUPTS

Page 33

VDDR

VDD

EXTAL PIN

INTERNAL

CLOCK

INTERNAL ADDRESS

BUS

INTERNAL

DATA

BUS

RESET

NOTES:

1. EXTAL is not meant to represent frequency. It is only used to represent time.

2. Internal clock, internal address bus, and internal data bus signals are not available externally.

3. Next rising edge of internal clock after rising edge of RESET

VDD THRESHOLD (TYPICALLY 1-2V)

oxov

FFFE FFFF NEW PC FFFE FFFE FFFF

cyc

NEW

PCL

initiates reset sequence.

NEW

PCH

4064 t

CODE

tRL=1.5t

cyc

CYC

PCH

PCL

NEW PC

CODE

Figure 4-1 Power-On Reset and RESET Timing

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MC68HC05T16 MOTOROLA

RESETS AND INTERRUPTS

4-3

Page 34

4.2 INTERRUPTS

The MC68HC05T16 is capable of handling eight types of interrupt, seven hardware and one software. The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts except the software interrupt, SWI. Interrupts such as Timer, M-Bus, OSD, and MFT have several ﬂags which will cause the interrupt. Interrupt ﬂags are found in “read only” status registers, while their enables are in associated control registers. They are never mix ed in the same register. If the enable bit is “0”, it masks the interrupt from occurring but does not inhibit the ﬂag from being set. A reset clears all enable bits. The general sequence for clearing an interrupt is a software sequence of reading the status register while the ﬂag is set followed by a read or write of an associated register. When any of these interrupts occur, and if enabled, normal processing is suspended at the end of the current instruction execution. The state of the machine is pushed onto the stack (see Figure 4-2 for stacking order) and the appropriate vector points to the starting address of the interrupt service routine (see T able 4-2). Also , the interrupt mask bit in the condition code register is set. This masks fur ther interrupts. At the completion of the service routine, the software normally contains an RTI instruction which, when executed, restores the machine state and continues executing the interrupted program. Interrupt priority is based on interrupt vector addresses. The higher the vector addresses, the higher the priority. For example, OSD interrupts have a higher priority than IRQ SWI and RESET

, TIMER, M-BUS, PAC, and MFT interrupts; but lower priority than

Note:

The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored on the stack is zero.

$00C0 (BOTTOM OF STACK) $00C1

UNSTACKING

5 4 3 2 1

STACKING

ORDER

1 2 3 4 5

•

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER

PROGRAM COUNTER (HIGH BYTE)

PROGRAM COUNTER (LOW BYTE)

•

$00C2

•

• $00FD $00FE $00FF (TOP OF STACK)

Figure 4-2 Interrupt Stacking Order

MOTOROLA 4-4

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MC68HC05T16RESETS AND INTERRUPTS

Page 35

Table 4-2 Reset/Interrupt Vector Addresses

– – Reset RESET $FFFE-$FFFF – – Software SWI $FFFC-$FFFD

VFLB Vertical Flyback

OSD Status

– – External Interrupt IRQ $FFF8-$FFF9

Timer Status

M-Bus Status

PAC Control PAOF Pulse Accumulator Overﬂow PAC $FFF2-$FFF3

Multi-Function

Timer

R3CF/R2CF/ R1CF/R0CF

ICF Input Capture

TOF Timer Overﬂow

ALOST Arbitration Loss

MCF Transfer Complete

RTIF Real Time Interrupt

TOF Timer Overﬂow

OSD Row Completion

OSD $FFFA-$FFFB

TIMER $FFF6-$FFF7OC0F/OC1F Output Compare

M-BUS $FFF4-$FFF5SELTED Addressed as Slave

MFT $FFF0-$FFF1

4.2.1 Hardware Controlled Sequences

The following three functions are not strictly interrupts, however, they are tied very closely to the interrupts. These functions are RESET

, STOP, WAIT.

1) RESET The RESET input pin causes the program to go to its starting address. This address is speciﬁed by the contents of memory locations $FFFE and $FFFF. The interrupt mask of the condition code register is also set. Most parts of the MCU is conﬁgured to some known state as described in Table 4-1.

2) STOP The STOP instruction causes the oscillator to be turned off and the processor “sleeps” until an e xternal interrupt (IRQ

) or RESET

occurs. See section 12 on Low Power Modes.

3) WAIT The WAIT instruction causes all processor clocks to stop, but leaves the Timer and PAC clocks running. This “rest” state of the processor can be exited by RESET

, an external interrupt (IRQ), or any of the interrupts described above. There are no special wait vectors for these individual interrupts. See section 12 on Low Power Modes.

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MC68HC05T16 MOTOROLA

RESETS AND INTERRUPTS

4-5

Page 36

4.2.2 Software Interrupt (SWI)

The software interrupt is an executable instruction. The action of the SWI instruction is similar to the hardware interrupts. The SWI is executed regardless of the state of the interr upt mask in the condition code register. The service routine address is speciﬁed by the contents of memory location $FFFC and $FFFD.

4.2.3 External Interrupt (IRQ)

The external interrupt IRQ can be software conﬁgured for “negative-edge” or “negative-edge and level” sensitive triggering by the IRQN bit in the Multi-Function Timer register.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Multi-Function Timer Register $1C TOF RTIF TOFIE RTIE IRQN WDOG RT1 RT0 0000 0011

IRQN

1 (set) – Negative edge triggering for IRQ 0 (clear) – Level and negative edge triggering for IRQ.

When the signal of the external interrupt pin, IRQ, satisﬁes the condition selected, an external interrupt occurs. The actual processor interrupt is generated only if the interr upt mask bit of the condition code register is also cleared. When the interr upt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the condition code register is set. This masks further interrupts until the present one is ser viced. The service routine address is speciﬁed by the contents of $FFF8 & $FFF9.

The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. Figure 4-3 shows both a block diagram and timing for the interrupt line (IRQ spaced far enough apart to be serviced. The minim um time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second conﬁguration shows several interrupt lines wired-OR to perform the interrupt at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized.

) to the processor. The ﬁrst method is used if pulses on the interrupt line are

only.

State

on reset

Note:

MOTOROLA 4-6

The internal interrupt latch is cleared in the ﬁrst par t of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t as soon as the I bit is cleared.

and serviced

ILIL

MC68HC05T16RESETS AND INTERRUPTS

TPG

Page 37

LEVEL SENSITIVE TRIGGER

IRQ

INTERRUPT PIN

IRQ

(a) Interrupt Function Diagram

ILIH

ILIL

I BIT (CC)

POWER-ON RESET

EXTERNAL RESET EXTERNAL INTERRUPT

BEING SERVICED

EDGE SENSITIVE TRIGGER CONDITION

The minimum pulse width t 125ns (V The period t the number of tcyc cycles it takes to execute the interrupt service routine plus 21 tcyc cycles.

EXTERNAL INTERRUPT REQUEST

is either

=5V) or 250ns (VDD=3V).

should not be less than

ILIL

ILIH

LEVEL SENSITIVE TRIGGER

Wired ORed

Interrupt signals

IRQ

CONDITION

if after servicing an interrupt the external interrupt pins remain low, then the next interrupt is recognized. Normally used with wired OR connection.

(b) Interrupt Mode Diagram

Figure 4-3 External Interrupt Circuit and Timing

TPG

MC68HC05T16 MOTOROLA

RESETS AND INTERRUPTS

4-7

Page 38

4.2.4 Programmable Timer Interrupt

Four timer interrupt ﬂags are found in the top nibb le of the Timer Status register (TSR) at location $11. All four interrupts will vector to the same address at location $FFF6-$FFF7.

Each ﬂag bit is deﬁned as follows:

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Timer Status Register $11 ICF OC0F OC1F TOF TCAPS 0 0 0 0000 u000

TOF - Timer Overﬂow Flag

TOF is set during the counter transition of $FFFF to $0000. It is cleared by reading the TSR (with TOF set) followed by reading the counter least signiﬁcant byte ($19).

OC0F, OC1F - Output Compare Flag 1 and Output Compare 2

The appropriate OCF is set when the corresponding Output Compare register matches the Counter register. It is cleared by reading the TSR (with OCF set) and then accessing the corresponding Output Compare register least signiﬁcant byte ($15 or $17).

ICF - Input Capture Flag

ICF is set when a proper edge has been sensed by the input capture edge detector. It is cleared by an CPU read of the TSR (with ICF set) followed by accessing the Input Capture register least signiﬁcant byte ($13).

All four timer interrupt ﬂags have corresponding enable bits (ICIE, OC0IE, OC1IE, and TOIE) found in the Timer Control register (TCR) at location $10. Reset clears all enable bits preventing an interrupt from occurring. The actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the interrupt mask bit in the condition code register is set. This masks further interrupts until the present one is serviced. The service routine address is speciﬁed by the contents of $FFF6 and $FFF7.

State

on reset

Refer to section 5.1 for detailed description of Programmable Timer.

4.2.5 M-Bus Interrupts

M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit, MIEN of M-Bus Control register is set, provided the interrupt mask bit of the condition code register is cleared. There are three causes of M-Bus interrupt:

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1) An arbitration lost which is signiﬁed by the Arbitration Lost ﬂag, ALOST of M-Bus Status Register.

2) Addressed as slave which is indicated by the master addressed as slave ﬂag, SELTED of M-Bus Status Register.

3) Completed transmission or reception of one byte of data. It depends on the original mode of the M-Bus interface which is determined by the Transmit/Receive ﬂag, XMT of M-Bus Control Register.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

M-Bus Status Register $3A MCF SELTED BBSY ALOST SRW MIF

MCF - Data Transfer Complete Flag

1 (set) – A byte transfer has been completed. 0 (clear) – A byte is being transfer.

SELTED - Addressed as Slave

1 (set) – Currently addressed as a slave. 0 (clear) – Currently not addressed.

When its own speciﬁc address (M-Bus Address register) matches the calling address, this bit is set. An interrupt is generated if the MIEN bit is set. Then CPU needs to check the SRW bit and set its XMT bit accordingly. Writing to the M-Bus Control register clears this bit.

ALOST - Arbitration Lost

This arbitration lost bit is set by hardware when the M-bus master loses arbitr ation during a master transmission mode. This bit must be cleared by software.

On entering the interrupt service routine, the M-Bus interrupt ﬂag, MIF of M-Bus Status Register must be cleared by software.

The interrupt service routine address is speciﬁed by the contents of memory location $FFF4 and $FFF5. Reset disables the whole M-Bus block by clearing the M-Bus Control Register.

RXACKB

State

on reset

1000 0001

Refer to Section 6 for detailed description of M-Bus.

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4.2.6 PAC Interrupt

Pulse Accumulator interrupt is enabled when the enable bit, PAIE of PAC Control register is set. The interrupt service routine address for PAC is speciﬁed by the contents of memory location $FFF2 and $FFF3.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PACTL $0E PAOF PAEN PAMOD PAIE 0000 0000

PAOF - PAC Overﬂow Interrupt Flag Bit.

1 (set) – A PAC overﬂow from $FF to $00 has occurred. 0 (clear) – No PAC overﬂow has occurred.

It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set.

PAIE - PAC Interrupt Enable Bit

1 (set) – PAC overﬂow Interrupt enabled. 0 (clear) – PAC overﬂow Interrupt disabled.

Refer to section 7 for detailed description of Pulse Accumulator.

State

on reset

4.2.7 OSD Interrupts

There are ﬁve OSD interrupt sources, VFLBK bit and R0/1/2/3CF bits of OSD Status register, in the OSD module. VFLB bit will be set whenever the leading edge of ver tical ﬂyback pin, VFLBK, has been detected. An interrupt will occur if the corresponding interrupt enable bit, VFINTE, is set. Whenever each row terminates its display, RiCF bit will be set and an interrupt will be generated provided that the corresponding interrupt enable bit, RiINTE is set. The interrupt service routine address is speciﬁed by the contents of memory location $FFFA and $FFFB.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Frame Control 3 and Status $2B VFINTE MUTE1 MUTE0 VFLB R3CF R2CF R1CF R0CF 0000 0000

VFINTE - VFLBK interrupt enable

1 (set) – Vertical ﬂyback interrupt enabled. 0 (clear) – Vertical ﬂyback interrupt disabled.

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State

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VFLB - VFLBK status

1 (set) – Vertical ﬂyback (leading edge) signal detected. 0 (clear) – No Vertical ﬂyback signal detected.

RiCF - Row i display status

1 (set) – Row i display has been terminated. 0 (clear) – Row i display has been not terminated.

Whenever a row display has been terminated, the corresponding RiCF ﬂag will be set along with update of CDRC3-CDRC0 ﬁeld.

Refer to section 9 for detailed description of On-Screen Display.

4.2.8 Multi-Function Timer Interrupts

There are two different interrupting sources, TOF and RTIF bits of Multi-Function Timer Register, in this module. The interrupt service routine address is speciﬁed by the contents of memory location $FFF0 and $FFF1.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Multi-Function Timer $1C TOF RTIF TOFIE RTIE IRQN WDOG RT1 RT0 0000 0011

TOF - Timer Overﬂow

1 (set) – 8-bit ripple timer overﬂow has occurred. 0 (clear) – No 8-bit ripple timer overﬂow has occurred.

This bit is set when the 8-bit ripple counter overﬂows from $FF to $00; a timer overﬂow interrupt will occur, if TOFIE (bit 5) is set. TOF is cleared by writing a ‘0’ to the bit.

RTIF - Real Time Interrupt Flag

1 (set) – A real time interrupt has occurred. 0 (clear) – A real time interrupt has not occurred.

A RTIF indicates when the output of the RTI circuit goes active. The clock frequency that drives the RTI circuit is E/16384 giving a maximum interrupt period of 3.9ms at a bus rate of 4.2MHz. A CPU interrupt request will be generated if RTIE is set. RTIE is cleared by writing a ‘0’ to the bit.

State

on reset

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TOFIE - Timer Overﬂow Interrupt Enable

1 (set) – TOF interrupt is enabled. 0 (clear) – TOF interrupt is disabled.

RTIE - Real Time Interrupt Enable

1 (set) – Real time interrupt circuit is active. 0 (clear) – Real time interrupt circuit is inactive.

Refer to section 5.2 for detailed description of Multi-Function Timer.

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TIMERS

5.1 PR OGRAMMABLE TIMER

The timer consists of a 16-bit free-running counter driven by a ﬁxed divide-by-four prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output wav eform. Pulse widths can v ary from sev eral microseconds to many seconds. Figure 5-1 shows a block diagram for the Programmable Timer.

Because the timer has a 16-bit architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers (high byte and low byte). Generally, assessing the low byte of a speciﬁc timer function allows full control of that function. However, an access of the high byte inhibits that speciﬁc timer function until the low byte is also accessed.

Note:

Twelve 8-bit registers are associated with the programmable timer.

The I bit in the condition code register should be set while manipulating both the high and low byte register of a speciﬁc timer function to ensure that an interrupt does not occur.

– Timer Control Register (TCR) $10 – Timer Status Register (TSR) $11 – Input Capture Register High byte - $12, Low byte - $13 – Output Compare 0 Register High byte - $14, Low byte - $15 – Output Compare 1 Register High byte - $16, Low byte - $17 – Counter Register High byte - $18, Low byte - $19 – Alternate Counter Register High byte - $1A, Low byte - $1B

A description of each register is provided in the following paragraphs.

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MC68HC05T16 INTERNAL BUS

OUTPUT

COMPARE

OUTPUT COMPARE CIRCUIT 1

OUTPUT

COMPARE

OUTPUT

COMPARE

CIRCUIT 2

INTERNAL PROCESSOR CLOCK

÷ 4

8 BIT

BUFFER

16 BIT FREE

RUNNING COUNTER

COUNTER

ALTERNATE

OVERFLOW

DETECT

CRCUIT

INPUT

CAPTURE

EDGE DETECT CIRCUIT

ICF OC0F OC1F TOF

INTERRUPT CIRCUIT

MOTOROLA 5-2

TCAPS

TIMER STATUS REGISTER

TIMER CONTROL REGISTER

ICIE OC0IE OC1IE TOVFIE IEDG

Figure 5-1 Programmable Timer Block Diagram

EDGE

INPUT

(TCAP)

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5.1.1 Counter

– Counter Register location High byte - $18, Low byte - $19 – Alternate Counter Register High byte - $1A, Low byte - $1B

The key element in the programmable timer is a 16-bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 0.95µs if the internal bus clock is 4.2MHz. The counter is incremented during the low portion of the internal bus clock. Software can read the counter at any time without affecting its value.

The double-byte, free-running counter can be read from either of two locations, $18 and $19 (counter register) or $1A and $1B (counter alternate register). Reading only the least signiﬁcant byte (LSB) of the free-running counter ($19 or $1B) receives the count value at the time of the read. If the most signiﬁcant byte (MSB) ($18 or $1A) is read ﬁrst, the LSB ($19 or $1B) is transferred to a buffer. This buffer v alue remains ﬁxed after the ﬁrst MSB read, even if the MSB is read several times. This buffer is accessed when the LSB ($19 or $1B) is read, and thus, completes a read sequence of the complete counter value.

Reading the Timer Counter register low byte after reading the timer Status Register clears the timer overﬂow ﬂag (TOF), but reading the Counter Alternate register does not affect TOF. Therefore, the counter alternate register can be read any time without risk of missing timer overﬂow interrupts due to a cleared TOF.

The free-running counter is preset to $FFFC during reset and is always a read-only register. During a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator start-up delay. The value in the free-running counter repeats every 262144 internal bus clock cycles. TOF is set when the counter overﬂows (from $FFFF to $0000); this will cause an interrupt if TOVFIE (bit 4 of Timer Control register) is set.

In some timing control applications it may be desirable to reset the counter under softw are control. When the low byte of the counter ($19 or $1B) is written to, the counter is set to its reset value of $FFFC. The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of the ﬂags and enable bits remain unaltered by this operation. If access has previously been made to the high byte of the free-running counter ($18 or $1A), then the reset counter operation terminates the access sequence.

5.1.2 Output Compare Registers

There are two 16-bit Output Compare registers:

– Output Compare 0 Register High byte - $14, Low byte - $15 – Output Compare 1 Register High byte - $16, Low byte - $17

Each 16-bit Output Compare register is made up of two 8-bit registers. These Output Compare registers are used for sev eral purposes, such as indicating when a period of time has elapsed. All

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bits are readable and writable and are not affected b y the timer hardw are or reset. If the compare function is not needed, the Output Compare registers can be used as storage locations.

The contents of the Output Compare registers are continually compared with the contents of the free-running counter and, if a match is found, the corresponding output compare ﬂag (OC0F or OC1F) in the Timer Status register is set. The Output Compare registers’ v alue should be changed after each successful comparison to establish a new elapsed time-out. An interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (OC0IE or OC1IE) is set. (The free-running counter is updated every four internal bus clock cycles.)

After a processor write cycle to the Output Compare registers containing the MSB ($14 or $16), the output compare function is inhibited until the LSB ($15 or $17) is also written. The user must write both bytes (locations) if the MSB is written ﬁrst. A write made only to the LSB ($15 or $17) will not inhibit the compare function. The processor can write to either byte of an Output Compare register without affecting the other byte. The minimum time required to update the Output Compare registers is a function of the program rather than the internal hardware. Because the output compare ﬂags and Output Compare registers are not deﬁned at power on, and not affected by reset, care must be taken when initializing output compare functions with software. The following procedure is recommended:

1) write to Output Compare register 0 and/or 1 High-byte to inhibit further compares;

2) read the Timer Status register to initialize clearing of OC0F or/and OC1F;

3) write to Output Compare register 0 or/and 1 Low-byte to enable the output compare function.

5.1.3 Input Capture Registers

– Input Capture Register High byte - $12, Low byte - $13

‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to trigger a read of the free-running counter. In this way it is possib le to relate the timing of an external signal to the internal counter value, and hence to elapsed time.

The two 8-bit registers that make up the 16-bit input capture register , are read-only, and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a valid transition. The level transition that triggers the counter transfer is deﬁned by the corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture register.

The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running counter , which is four internal bus clock cycles.

The free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture ﬂag (ICF) is set or clear. The input capture register always

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contains the free-running counter value that corresponds to the most recent input capture.After a read of the input capture register MSB ($12), the counter transfer is inhibited until the LSB ($13) is also read. This characteristic causes the time used in the input capture software routine and its interaction with the main program to determine the minimum pulse period. A read of the input capture register LSB ($13) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock.

5.1.4 Timer Control Register (TCR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$10 ICIE OC0IE OC1IE TOVFIE IEDG 0000 0000

The TCR is a read/write register containing ﬁve control bits . F our bits control interrupts associated with each of the four ﬂag bits found in the Timer Status register. The other bit controls which edge is signiﬁcant to the input capture edge detector. The Timer Control register and the free-running counter are the only sections of the timer affected by reset.

Deﬁnition of each bit is as follows:

ICIE - Input Capture Interrupt Enable

1 (set) – Input Capture interrupt enabled. 0 (clear) – Input Capture interrupt disabled.

OC0IE - Output Compare Interrupt Enable

1 (set) – Output Compare 0 interrupt enabled. 0 (clear) – Output Compare 0 interrupt disabled.

OC1IE - Output Compare Interrupt Enable

1 (set) – Output Compare 1 interrupt enabled. 0 (clear) – Output Compare 1 interrupt disabled.

State

on reset

TOVFIE - Timer Overﬂow Interrupt Enable

1 (set) – Timer Overﬂow interrupt enabled. 0 (clear) – Timer Overﬂow interrupt disabled.

IEDG - Input Edge

1 (set) – TCAP is positive-going edge sensitive. 0 (clear) – TCAP is negative-going edge sensitive.

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When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running counter value to the input capture registers. When clear, a negative-going edge triggers the transfer.

5.1.5 Timer Status Register (TSR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$11 ICF OC0F OC1F TOF TCAPS 0000 u000

The Timer Status register contains the status bits for the above four interrupt conditions - ICF, OC0F, OC1F, TOF.

Accessing the timer status register satisﬁes the ﬁrst condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit.

ICF - Input Capture Flag

1 (set) – A valid input capture has occurred. 0 (clear) – No input capture has occurred.

This bit is set when the selected polarity of edge is detected by the input capture edge detector; an input capture interrupt will be generated, if ICIE is set, ICF is cleared by reading the TSR and then the Input Capture Low register ($13)

OC0F - Output Compare 0 Flag

1 (set) – A valid output compare has occurred on output compare 0 register. 0 (clear) – No output compare has occurred on output compare 0 register.

OC0F will be set when its output compare 0 register contents match that of the free-running counter; an output compare interrupt will be generated, if OC0IE is set. OC0F is cleared by reading the TSR and then the Output Compare 0 Low register ($15).

State

on reset

OC1F - Output Compare 1 Flag

1 (set) – A valid output compare has occurred on output compare 1 register. 0 (clear) – No output compare has occurred on output compare 1 register.

OC0F will be set when its output compare 1 register contents match that of the free-running counter; an output compare interrupt will be generated, if OC1IE is set. OC1F is cleared by reading the TSR and then the Output Compare 1 Low register ($17).

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TOF - Timer Overﬂow Flag

1 (set) – Timer Overﬂow has occurred. 0 (clear) – No timer overﬂow has occurred.

This bit is set when the free-running counter overﬂows from $FFFF to $0000; a timer overﬂow interrupt will occur, if TOIE (bit 5 in Timer Control register $10) is set. TOF is cleared by reading the TSR and the counter low register ($19).

When using the timer overﬂow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereb y the timer o v erﬂo w ﬂag is unintentionally cleared if:

1) the timer status register is read or written when the TOF is set, and

2) the LSB of the free-running counter is read, but not for the purpose of servicing the ﬂag.

Reading the alternate counter register instead of the counter register will avoid this potential problem.

TCAPS - Timer Capture State

1 (set) – TCAP pin is a logic high. 0 (clear) – TCAP pin is a logic low.

This bit reﬂects the logic level at the TCAP pin.

5.1.6 Programmable Timer Timing Diagrams

The relationships between the internal clock signals, the counter contents and the status of the ﬂag bits are shown in the following diagr ams. It should be noted that the signals labelled ‘internal’ (processor clock, timer clocks and Reset) are not available to the user.

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INTERNAL

PROCESSOR

CLOCK

INTERNAL

RESET

T00

INTERNAL

CLOCKS

(external or end of POR)

INTERNAL

T01

TIMER

T10

T11

COUNTER

(16 BIT)

RESET

Notes:

RESET affects only the Counter register and Timer Control register.

INTERNAL

PROCESSOR

CLOCK

T00

T01

TIMER

CLOCKS

T10

T11

COUNTER

(16 BIT)

$FFFC $FFFD $FFFE $FFFF

Figure 5-2 Timer State Timing Diagram for Reset

$F123 $F124 $F125 $F126 $F127

INPUT EDGE

(SEE NOTE)

INTERNAL CAPTURE

LATCH

INPUT

CAPTURE

INPUT

CAPTURE

FLAG

Note:

If the input edge occurs in the shaded area from one timer state T10 to the other timer state T10 the input capture ﬂag is set during the next state T11.

Figure 5-3 Timer State Timing Diagram for Input Capture

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$F125$????

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INTERNAL

PROCESSOR

CLOCK

T00

INTERNAL

CLOCKS

OUTPUT COMPARE

COMPARE REGISTER

OUTPUT COMPARE

Flag and TCMP1, 2

Note:

PROCESSOR

T01

TIMER

T10

T11

COUNTER

(16 BIT)

LATCH

1. The CPU write to the compare registers may take place at any time, but a compare only occurs at

the timer state T01. Thus a 4-cycle difference may exist between the write to the compare register and the actual compare.

2. The output compare ﬂag is set at the timer state T11 that follows the comparison match ($F547 in

this example).

INTERNAL

CLOCK

T00

$F455 $F456 $F457 $F458 $F459

Note 1

CPU writes $F457

Note 1

Note 2

$F457

Figure 5-4 Timer State Timing Diagram for Output Compare

INTERNAL

Note:

T01

TIMER

CLOCKS

T10

T11

COUNTER

(16 BIT)

TIMER

OVERFLOW

FLAG (TOF)

The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000).

It is cleared by a read of the timer status register during the internal processor clock high time followed by a read of the counter low register.

$FFFE $FFFF $0000 $0001 $0002

Figure 5-5 Timer State Diagram for Timer Overﬂow

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5.2 MUL TI-FUNCTION TIMER

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Multi-Function Timer Register $1C TOF RTIF TOFIE RTIE IRQN WDOG RT1 RT0 0000 0011

The MFT provides miscellaneous function to the MC68HC05T16 MCU. It includes a timer ov erﬂow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ also set by this Multi-Function Timer register.

The clock base for this module is derived from the b us clock divided by f our . For a 4.2MHz E (CPU) clock, the clock base is 1.05 MHz. This clock base is then divided by an 8-stage ripple counter to generate the timer overﬂow. Timer overﬂow rate is thus E/1024. The output of this 8-stage ripple counter then drives a 4-stage divider to generate real time interrupt. Hence , the clock base f or real time interrupt is E/16384. Real time interrupt rate is selected by R T0 and RT1 bits of Multi-Function Timer register. The interrupt rates are E/16384, (E/16384)/2, (E/16384)/4, and (E/16384)/8. The selected real time interrupt rate is then divided by 8 to generate COP reset.

TOF - Timer Overﬂow

1 (set) – 8-bit ripple timer overﬂow has occurred. 0 (clear) – No 8-bit ripple timer overﬂow has occurred.

This bit is set when the 8-bit ripple counter overﬂows from $FF to $00; a timer overﬂow interrupt will occur, if TOFIE (bit 5) is set. TOF is cleared by writing a ‘0’ to the bit.

) triggering option is

State

on reset

RTIF - Real Time Interrupt Flag

1 (set) – A real time interrupt has occurred. 0 (clear) – A real time interrupt has not occurred.

When RTIF is set, a CPU interrupt request is generated if RITE is set. The clock frequency that drives the RTI circuit is E/16384 giving a maximum interrupt period of 3.9ms at a bus rate of

4.2MHz. RTIF is cleared by writing a “0” to the bit.

TOFIE - Timer Overﬂow Interrupt Enable

1 (set) – TOF interrupt is enabled. 0 (clear) – TOF interrupt is disabled.

RTIE - Real Time Interrupt Enable

1 (set) – Real time interrupt is enabled. 0 (clear) – Real time interrupt is disabled.

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IRQN - IRQ Pin Trigger Option

1 (set) – Negative edge triggering for IRQ only. 0 (clear) – Level and negative edge triggering for IRQ.

WDOG - COP Watchdog Enable

1 (set) – COP watchdog circuit enabled. 0 (clear) – COP watchdog circuit disabled.

See Section 5.2.1 on COP watchdog reset.

RT1, RT0 - Rate Select for COP watchdog and RTI

See Section 5.2.1 on watchdog reset.

5.2.1 COP Watchdog Reset

The COP (Computer Operating Properly) watchdog timer function is implemented by using the output of the Multi-Function Timer counter. The minimum COP reset rates are controlled by RT0 and RT1 of Multi-Function Timer register. If the COP circuit times out, an internal reset is generated and the reset vector is fetched (at $FFFE & $FFFF). Preventing a COP time-out is achieved b y writing a ‘0’ to bit 0 of address $FFF0. The COP counter has to be cleared periodically by software with a period less than COP reset rate.

Watchdog timer function will stop counting in Wait and Stop modes. Counting continues when it wakes up from Wait mode, and a 4064 cycle delay after waking up from Stop mode.

The watchdog counter system is controlled by the WDOG bit in the Multi-Function Timer register (bit 2 of address $1C). After power-on or external reset the watchdog system is disabled. Writing a “1” to the WDOG bit will enable the watchdog system and the counter starts counting. Once enabled, the watchdog system cannot be disabled by software. Writing a “0” to bit 0 of address $FFF0 will reset watchdog counter to prevent a watchdog time-out.

Table 5-1 COP Reset and RTI Rates

RT1 RT0

0 0 27.3ms 3.9ms 0 1 54.6ms 7.8ms 1 0 109.27ms 15.6ms 1 1 218.4 ms 31.2ms

RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset.

MC68HC05T16 MOTOROLA

Minimum COP reset period

E clock = 4.2MHz

TIMERS

RTI period

E clock = 4.2MHz

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M-BUS SERIAL INTERFACE

M-Bus (Motorola Bus) is a two-wire, bidirectional serial bus which provides a simple, efﬁcient w a y for data exchange between devices. It is fully compatible with the I bus minimizes the interconnection between devices and eliminates the need for address decoders; resulting in less PCB traces and economic hardware structure. This bus is suitable for applications requiring communications in a short distance among a number of devices. The maximum data rate is 100Kbit/s. The maximum comm unication length and number of de vices that can be connected are limited by a maximum bus capacitance of 400pF.

The M-Bus system is a true multi-master bus, including arbitration to prevent data collision if two or more masters intend to control the bus simultaneously. It may be used for rapid testing and alignment of end products via external connections to an assembly-line computer.

C bus standard. This two-wire

6.1 M-Bus Interface Features

• Compatible with I2C bus standard

• Multi-master operation

• 32 software programmable serial clock frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost driven interrupt with automatic mode switching from master to slave

• Calling address identiﬁcation interrupt

• Generate/detect the start, stop and acknowledge signals

• Repeated START signal generation

• Bus busy detection

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Control register Status register

MEN MIEN MSTR XMT ACKEB MCF SELTED BBSY LOST SRW MIF RXACKB

Interrupt

M-Bus

interrupt

Internal bus

Frequency

divider

Address register

Address

comparator

M-Bus clock

START, STOP

detector and

arbitration

generator sync logic

START, STOP

generator and

timing sync

SCL

SDA

SCL

control

SDA

control

Figure 6-1 M-Bus Interface Block Diagram

6.2 M-Bus Protocol

Normally, a standard communication is composed of four parts,

1) START signal,

2) slave address transmission,

3) data transfer, and

4) STOP signal.

TX shift

control

RX shift register

control

They are described brieﬂy in the following sections and illustrated in Figure 6-2.

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MSB LSB MSB LSB

SCL

SDA

SCL

SDA

101 00011 1 01 00011

Acknowledge bit No acknowledge

START signal STOP signal

MSB LSB MSB LSB

101 00011 1 01 00011

Acknowledge bit No acknowledge

START signal STOP signal

repeated START signal

Figure 6-2 M-Bus Transmission Signal Diagram

6.2.1 START Signal

When the bus is free, i.e., no master device is occupying the bus (both SCL and SDA lines are at logic high), a master may initiate communication by sending a START signal. As shown in Figure 6-2, a START signal is deﬁned as a high to low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transf er ma y contain se v er al bytes of data) and wakes up all slaves.

6.2.2 Slave Address Transmission

The ﬁrst byte of data transfer immediately following the START signal is the slave address transmitted by the master . This is a seven bits long calling address followed b y a R/W bit dictates the slave of the desired direction of data transfer.

Only the slave with matched address will respond by sending back an acknowledge bit by pulling the SDA low at the 9th clock; see Figure 6-2.

bit. The R/W

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6.2.3 Data Transfer

Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction speciﬁed by the R/W

Each data byte is 8 bits long. Data can be changed only when SCL is low and m ust be held stable when SCL is high as shown in Figure 6-2. One clock pulse is for one bit of data transfer, MSB is transferred ﬁrst. Each data byte has to be followed by an acknowledge bit. Hence, one complete data byte transfer requires 9 clock pulses.

If the slave receiver does not acknowledge the master, the SDA line should be left high by the slave, the master can then generate a STOP signal to abor t the data transfer or a START signal (repeated START) to commence a new calling.

If the master receiver does not acknowledge the slave transmitter after one byte transmission, it means an “end of data” to the slave. The slave shall release the SDA line for the master to generate STOP or START signal.

bit sent by the calling master.

6.2.4 Repeated START Signal

As shown in Figure 6-2, a repeated START signal is to generate a START signal without ﬁrst generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.

6.2.5 STOP Signal

The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal ﬁrst. This is called repeat START. A STOP signal is deﬁned as a low to high transition of SDA while SCL is at a logical high; See Figure 6-2.

6.2.6 Arbitration Procedure

This interface circuit is a true multi-master system which allows more than one master to be connected. If two or more masters try to control the bus at the same time , a clock synchronization procedure determines the bus clock. The clock low period is equal to the longest clock low period among the masters; and the clock high period is the shortest among the masters. A data arbitration procedure determines the priority. A master will lose arbitration if it transmits a logic “1” while the others transmit logic “0”, the losing master will immediately switch over to slave receive mode and stops its data and clock outputs. The transition from master to slave mode will not generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of arbitration.

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6.2.7 Clock Synchronization

Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will aff ect the devices connected to the bus. The devices start counting their low period and once a device's clock has gone low, it will hold the SCL line low until the clock high state is reached. Howe v er, the change of low to high in this device clock may not change the state of the SCL line, if another device clock is still in its low period. Therefore synchronized clock SCL will be held low by the device which releases SCL to a logic high in the last place. Devices with shorter low periods enter a high wait state during this time (See Figure 6-3). When all devices concerned have counted off their low period, the synchronized clock SCL line will be released and go high. All of them will start counting their high periods. The ﬁrst device to complete its high period will again pull the SCL line low .

WAIT

SCL1

SCL2

SCL

Internal counter reset

Figure 6-3 Clock Synchronization

Start counting high period

6.2.8 Handshaking

The clock synchronization mechanism can be used as a handshake in data transf er. Slave device may hold the SCL low after completion of one byte transfer (9 bits). In such case, it will halt the bus clock and force the master clock in a wait state until the slave releases the SCL line.

6.3 M-Bus Registers

There are ﬁve registers used in the M-Bus interface, these are discussed in the following paragraphs.

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6.3.1 M-Bus Address Register (MADR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$37 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0000 0000

State

on reset

ADR1-ADR7 are the slave address bits of the M-Bus module.

6.3.2 M-Bus Clock Register (MCKR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$38 MBC4 MBC3 MBC2 MBC1 MBC0 0000 0000

MBC0-MBC4 are used for clock rate selection. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 6-1.

Table 6-1 M-Bus Prescaler

MBC4 MBC3 MBC2 MBC1 MBC0 DIVIDER MBC4 MBC3 MBC2 MBC1 MBC0 DIVIDER

0000022 10000352 0000124 10001384 0001028 10010448 0001134 10011544 0010044 10100704 0010148 10101768 0011056 10110896 0011168 101111088 0100088 110001408 0100196 110011536 0 1 0 1 0 112 1 1 0 1 0 1792 0 1 0 1 1 136 1 1 0 1 1 2176 0 1 1 0 0 176 1 1 1 0 0 2816 0 1 1 0 1 192 1 1 1 0 1 3072 0 1 1 1 0 224 1 1 1 1 0 3584 0 1 1 1 1 272 1 1 1 1 1 4352

State

on reset

For a 4.2MHz external crystal operation (2.1MHz internal operating frequency), the serial bit clock frequency of M-Bus ranges from 483Hz to 95,455Hz.

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6.3.3 M-Bus Control Register (MCR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$39 MEN MIEN MSTR XMT ACKEB 0000 0000

MEN - M-Bus Enable

1 (set) – M-Bus interface system enabled. 0 (clear) – M-Bus interface system disabled.

MIEN - M-Bus Interrupt Enable

1 (set) – M-Bus interrupt enabled. 0 (clear) – M-Bus interrupt disabled.

This bit enables the MIF (in MSR) for M-Bus interrupts.

MSTR - Master/Slave Select Bit

1 (set) – M-Bus is set for master mode operation. 0 (clear) – M-Bus is set for slave mode operation.

Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave. In master mode, a bit clear immediately followed b y a bit set of this bit generates a repeated START signal without generating a STOP signal.

State

on reset

XMT - Transmit/Receive Mode Select Bit

1 (set) – M-Bus is set for transmit mode. 0 (clear) – M-Bus is set for receive mode.

ACKEB - Acknowledge Enable Bit

1 (set) – Do not send acknowledge signal. 0 (clear) – Send acknowledge signal at 9th clock bit.

If cleared, an acknowledge signal will be sent out to the bus at the 9th cloc k bit after receiving one byte of data. If set, no acknowledge signal response. This is an active low control bit.

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6.3.4 M-Bus Status Register (MSR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$3A MCF SELTED BBSY ALOST SRW MIF RXACKB 1000 0001

The MIF and ALOST bits are software clearable; while the other bits are read only.

MCF - Data Transfer Complete Flag

1 (set) – A byte transfer has been completed. 0 (clear) – A byte is being transfer.

When MCF is set, the MIF (M-bus interrupt) bit is also set. An M-bus interrupt is generated if the MIEN bit is set.

SELTED - Addressed as Slave Bit

1 (set) – Currently addressed as a slave. 0 (clear) – Not currently addressed.

This SELTED bit is set when its own speciﬁc address (M-Bus Address register) matches the calling address. When SELTED is set, the MIF (M-bus interrupt) bit is also set. An interrupt is generated if the MIEN bit is set. Then CPU needs to check the SRW bit and set its XMT bit accordingly. Writing to the M-Bus Control register clears this bit.

BBSY - Bus Busy Bit

State

on reset

1 (set) – M-Bus busy. 0 (clear) – M-Bus idle.

This bit indicates the status of the bus. When a START signal is detected, BBSY is set. If a STOP signal is detected, it is cleared.

ALOST - Arbitration Lost Flag

1 (set) – Lost arbitration in master mode. 0 (clear) – No arbitration lost.

This arbitration lost ﬂag is set when the M-bus master loses arbitration during a master transmission mode. When ALOST is set, the MIF (M-bus interrupt) bit is also set. This bit must be cleared by software.

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SRW - Slave R/W Select

1 (set) – Read from slave, from calling master. 0 (clear) – Write to slave from calling master.

When SELTED is set, the R/W command bit of the calling address sent from the master is latched into this SRW bit. By checking this bit, the CPU can then select slave transmit/receive mode by conﬁguring XMT bit of the M-Bus Control register.

MIF - M-Bus Interrupt Flag

1 (set) – A M-Bus interrupt has occurred. 0 (clear) – A M-Bus interrupt has not occurred.

When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one of the following events occurs:

1) Completion of one byte of data transfer . It is set at the falling edge of the 9th clock - MCF set.

2) A match of the calling address with its own speciﬁc address in slave receive mode - SELTED set.

3) A loss of bus arbitration - ALOST set.

This bit must be cleared by software in the interrupt routine.

RXACKB - Receive Acknowledge Bit

1 (set) – No acknowledgment signal detected. 0 (clear) – Acknowledgment signal detected after 8 bits data transmitted.

If cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If set, no acknowledge signal has been detected at the 9th clock. This is an active low status ﬂag.

6.3.5 M-Bus Data I/O Register (MDR)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$3B MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 uuuu uuuu

In master transmit mode, data written into this register is sent to the bus automatically, with the most signiﬁcant bit out ﬁrst. In master receive mode, reading of this register initiates receiving of the next byte data. In slave mode, the same function applies after it has been addressed.

State

on reset

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PULSE ACCUMULATOR

The Pulse Accumulator is an 8-bit counter that can operate in either of two modes; e vent counting mode and the gated time accumulation mode. The operating mode is selected by a control bit in the Pulse Accumulator Control register.

In the event counting mode, the 8-bit counter is clocked by the signal on the PACIN pin. The maximum clocking rate for the external counting mode is E (CPU) clock divided by two.

In the gated time accumulation mode, the 8-bit counter is driven by E clock divided by 64. The counter will increment when PACIN pin is high and halt when PACIN is low.

7.1 Pulse Accumulator Registers

Two registers are associated with the Pulse Accumulator; they are described below.

7.1.1 PAC Control and Status Register (PACTL)

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$0E PAOF PAEN PAMOD PAIE 0000 0000

PAOF - PAC Overﬂow Interrupt Flag Bit.

1 (set) – A PAC overﬂow from $FF to $00 has occurred. 0 (clear) – No PAC overﬂow has occurred.

It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set.

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PAEN - PAC Enable Bit

1 (set) – Pulse Accumulator enabled. 0 (clear) – Pulse Accumulator disabled. PAC counter register is also cleared.

PAMOD - Pulse Accumulator Mode Bit

1 (set) – Gated time accumulation mode. 0 (clear) – External event counting mode.

PAIE - PAC Interrupt Enable Bit

1 (set) – PAC overﬂow Interrupt enabled. 0 (clear) – PAC overﬂow Interrupt disabled.

This PAIE bit enables interrupt caused by the PAOF bit.

7.1.2 PAC Counter Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$0F PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 0000 0000

When PAC is disabled (PAEN= 0), the counter will be cleared to zero. This ensures the Counter starts from zero every time it is disabled and enabled.

The Pulse Accumulator Counter is read only and resets to zero a write operation.

State

on reset

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PULSE WIDTH MODULATOR

The MC68HC05T16 has 10 PWM channels, with output pins shared with port E and port F pins. Nine 7-bit channels are driven by the Timer clock, the other single 14-bit channel is driven by the CPU clock. All PWM outputs are +12V open-drain type; therefore a pull-up resistor is required at each PWM pin.

8.1 7-Bit PWM Channels

The 7-bit PWM system works in conjunction with the 16-bit free running timer to implement nine channels of conversion. A PWM register is allocated for each PWM channel. Channels PWM0 to PWM8, located at $2C to $34 respectively. Each 7-bit PWM data register has the same bit structure as shown below:

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PWM0 $2C 0PWM6 0PWM5 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 0000 0000

PWM8 $34 8PWM6 8PWM5 8PWM4 8PWM3 8PWM2 8PWM1 8PWM0 0000 0000

The driving clock for the 7-bit PWM channels is the 16-bit free-running timer clock divide by 2. For a 2.1MHz CPU clock, PWM clock = 2.1MHz/4/2 = 262500Hz. The PWM pulse period is 128 x 1/262500Hz = 487.62µs, i.e. a repetition frequency of 2050.8Hz. The duty cycle is proportional to the value in the corresponding PWM data register. A value of $00 loaded into these registers results in a continuously low output on the corresponding PWM output pin with external pull-up resistor connected. A v alue of $40 results in a 50% duty cycle output. The maximum value of $7F results in a 127/128 duty cycle output.

Changes to the value in the PWM registers will only become effective after the end of the current PWM cycle. This prevents erroneous PWM output during value update.

In Stop mode, the oscillator is stopped asynchronously with PWM operation. As a consequence, the PWM output will remain at the state at the moment when the oscillator is stopped. The PWM output might be at its high or low state at that moment, and it remains at that state until Stop mode

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on reset

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PWM value

$00

$01

487.62µs

128T

127T

$40

$7F

T = PWM clock period = 2 Timer clock periods = 8 CPU clock periods =3.81µs if MCU runs at 2.1MHz

64T 64T

127T

Figure 8-1 7-Bit PWM Output Waveform

is exited. After Stop mode is e xited, the PWM output resumes its unﬁnished portion of the stopped cycle. In Wait mode, the oscillator is running even though the CPU clock is not present, the PWM outputs are not affected.

Note:

Since the 7-bit PWM module uses the 16-bit free-running timer counter, PWM outputs will be affected when the counter is being reset.

8.2 14-Bit PWM Channel

The output wavef orm of the 14-bit PWM channel is controlled by an 8-bit and a 6-bit register . Each register can be viewed as conﬁguring its own waveform; the ﬁnal PWM output waveform is a combination of the two wavefor ms (waveforms are ORed). The driving clock for the 14-bit PWM channels is CPU clock.

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

BRM $35 9PWM5 9PWM4 9PWM3 9PWM2 9PWM1 9PWM0 0000 0000 PWM $36 9PWM13 9PWM12 9PWM11 9PWM10 9PWM9 9PWM7 9PWM7 9PWM6 0000 0000

State

on reset

The 8-bit register works in the same way as the 7-bit PWMs. That is, the value set in this 8-bit register determines the basic duty cycle of the waveform. A value of $00 results in a continuously

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low cycle. A value of $7F results in a 50% duty cycle. The maximum value of $FF results in a 255/256 duty cycle. The 14-bit PWM period is 256x0.476µs=121.9µs for a CPU clock of 2.1MHz.

The 6-bit register acts as a binary rate multiplier (BRM). The v alue set in this register (powers of 2) equals the number of pulses (pulse width equals to the PWM driving clock cycle) equally distributed in a 64-PWM-cycle. A maxim um value of $2x will have 32 pulses equally distributed in 64 PWM cycles (64 cycles has a period of 64x121.9µs=7.8ms).

Combining the 8-bit PWM together with the 6-bit BRM, the total average duty cycle at the output will be (M+N/64)/256, where M is the content of the 8-bit high-order register, and N is the content of the 6-bit low-order register. Using this mechanism, a true 14-bit resolution PWM is achieved. Figure 8-2 shows the waveform for the 14-bit PWM channel. Note that the resulting waveform is periodic on every 64 PWM cycles.

256T

M= $00

M= $01

255T

M= $7F

M= $FF

T= 1 CPU clock period (0.476µs if CPU clock= 2.1MHz) M = value set in 8-bit PWM register (address $36) N = value set in 6-bit binary rate multiplier (address $35)

N PWM cycles where pulses are inserted in a 64-cycle frame

--xxxxx1 32 1

--xxxx1x 16, 48 2

--xxx1xx 8, 24, 40, 56 4

--xx1xxx 4, 12, 20, 28, 36, 44, 52, 60 8

--x1xxxx 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 16

--1xxxxx 1, 3, 5, 7, ......61, 63 32

128T

255T

Pulse inserted at end of PWM cycle depends on setting of N.

128T

Number of inserted pulses in a 64-cycle

Figure 8-2 14-Bit PWM Output Waveform

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In order to prevent transient noise at the output during MCU write to the 8-bit PWM and 6-bit BRM registers, double buffering is used. Programming of the 2 registers must follow the sequence as shown below:

LDA BRM_value STA $35 ;Data put in 6-bit BRM buffer LDA PWM_value STA $36 ;Load 6-bit BRM and 8-bit PWM register

The instruction STA $35 simply puts the 6-bit BRM data in a buffer. Output is not affected at this time. The instruction STA $36, then, puts the total 14-bit data to BRM and PWM register at the same time. Output wa vef orm will change accordingly starting from the beginning of the next PWM cycle.

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ON-SCREEN DISPLAY

9.1 Introduction

The PLL-based On-Screen Display module displays programmable number of rows of symbols, be them characters or graphic symbols, either in a 16x16 dot matrix or in a 12x16 dot matrix over a full TV screen. It supports double scan mode for TV broadcast systems which implement non-interlaced scan broadcast. In double scan mode, each horizontal line in the character dot matrix will be displayed twice. Users have to determine if the target TV system is an interlaced or non-interlaced TV system. Auto TV system detection is not implemented.

The essence of this OSD module consists of four row buff ers for displa ying screen characters; with each row buffer having its own vertical position registers. Row buffers are refreshed if more than four rows of displa y are required. The PLL enables the OSD to adapt to any shift or change in the incoming horizontal ﬂyback frequency. Frame display fade-in and fade-out features are supported for smooth display appearance and disappearance.

Besides the 128-character ROM/EPROM f or ﬁxed character patterns, there is a 16-character RAM for user deﬁned patterns. This character RAM can be written and read by the CPU, but read-only by the OSD hardware. Since the contents of this character RAM can be changed during run-time, the user can have a large number of character sets stored in internal ROM, or in external ROM/EPROM/EEPROMs and have them load in via the M-bus.

The character dot matrix can be programmed to be either 12x16 or 16x16. Mixture of character dot matrices is not permissible on a row. There is no space between adjacent character dot matrices. The 12 x16 dot matrix is mainly used for English-type characters; whereas the 16x16 dot matrix is mainly used for character sets requiring bigger dot matrix to create legible fonts, such as Korean, Chinese, and Kanji. Each row buffer can display 32 characters for a 12x16 conﬁguration, and 24 characters for a 16x16 conﬁguration.

Character blinking, black-edge (bordering or shadowing), and background color features are supported. Background and blinking features are on per character basis; whereas bordering feature is on per row basis. Users have to be careful while designing their character fonts so that bordering effect is not nulliﬁed between adjacent characters in the same row or in two consecutiv e rows.

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The video mute function, when enabled, blocks off all TV video signals; but OSD signals remain. This feature can be used when, for example, the selected channel does not have any valid broadcast signals. Rather than displaying snow ﬂakes on the screen, the OSD mute function can be activated to cover up the sno w ﬂak es and replace them b y one of three color selections: black, green or blue. Video mute can be synchronized with vertical ﬂyback signal so that muting always occurs on vertical ﬂyback boundary to avoid inconsistent display in the same display ﬁeld, be it even or odd. To facilitate this, OSD interrupt activated by the leading edge of vertical ﬂyback is implemented. Whenever the video mute function is activated, fast blanking signal will be constantly activated until video mute function is deactivated. As a result, half tone feature is disabled while video mute is activated.

Ten pins are used for the OSD module; HFLBK, VFLBK, VCO, RP, FBKG, R, G, B, I, and HTONE. The I and HTONE pins are shared with port PF2 and PF3 respectively. HTONE (half tone) is used to create transparent background effect on the screen.

OSD registers are divided into four groups; with characters register group deﬁning individual character features, frame register group deﬁning frame features, row register group deﬁning individual row features, and ﬁnally status register carrying the status of the whole OSD module.

9.2 Features

Frame/Row Features

• PLL-based clock source

• Four display row buffers

• Programmable R/G/B, I, fast b lanking, and half tone output polarity and H/V sync input polarity

• Programmable row V and frame H start positions

• 12x16 or 16x16 character dot matrix selection on per row basis

• 32 (12x16 dot matrix) or 24 (16x16 dot matrix) symbols per row

• 8 common color palettes for both symbol color and background color

• 16 color selections per palette

• Frame fade in and fade out feature for smooth display appearance and disappearance

• Four row character size selections: 1Hx1V, 2Hx2V, 3Hx3V, and 4Hx4V

• Row character black-edge features: bordering or shadowing

• Double scan mode support for non-interlaced scan TV system

• Half tone capability for creating transparent background effect

• Video mute. Three color selections for video mute: black, green, and blue

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• Interrupt on the leading edge of vertical ﬂyback signal

Character Features

• 128-character ROM/EPROM plus 16-character RAM. Character RAM is dual ported

• Character attribute is on per character basis

• Individually controllable character background

• Character blinking with four blinking rates

9.3 Characters

Characters are stored in a 128-character ROM and a 16-character RAM. The 128 pairs of character registers are equally allocated for the 4 row buffers, each have 32 pairs. Each pair of character registers consists of the Character Code register and the Character Attribute register. The Character Code register selects the particular character from the character ROM/EPROM/RAM. The Character Attribute register selects the color, background, and blinking features for that selected character.

9.3.1 Character RAM

OSD character RAM is a dual ported RAM, consisting of 16 x(16 x16)/8 =512 bytes of RAM; located from $0400 to $05FF. Upon reset, the content of character RAM is random. Every entr y of this 16-entry character RAM occupies 32 consecutive memory bytes, always starting at even addresses. Users can read and write any byte at any time . OSD can only read the char acter RAM. Figure 9-1 shows the memory map of one entry of the 16-entry OSD character RAM.

If 12x16 character dot matrix is selected, bit 3 to bit 0 of all low order bytes at the right-hand side of Figure 9-1 will not be used for display.

9.3.2 Character ROM/EPROM

The memory arrangement of OSD character ROM/EPROM is the same as that of character RAM. Character ROM/EPROM is not readable to the CPU in user mode . OSD char acter ROM is located from $8000 to $8FFF. Three characters in the Character ROM are ﬁxed, and cannot be changed. They are shown in Figure 9-2.

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even bytes odd bytes

$xxx $xxx+ $002

$xxx+ $01E $xxx+ $01F

High order bytes Low order bytes

7 07430

Bits not used when 12x 16 dot matrix is selected

indicates a character dot exist indicates a character dot does not exist

$xxx+ $001 $xxx+ $003

Single Character Map

Select character pointer for RAM or ROM/EPROM

$0400

$05FF

Character Pointer

Character RAM Character ROM/EPROM

Character 0 Character 1

32-bytes per

Character

Character 16

Character 0 Character 1

32-bytes per

Character

Character 128

$8000

$8FFF

$201

$200

$200 $201

$240 $241

$280 $281

$2C0 $2C1

MOTOROLA 9-4

ROM/RAM

BLNKG

CH6 CH5 CH4 CH3 CH2 CH1 CH0

BGEN BGCOL2 BGCOL1 BGCOL0 CCOL2 CCOL1 CCOL0

$230 $231

$270 $271

$2B0 $2B1

$2F0 $2F1

Last 8 character register pairs of a row buffer are not used when that row buffer is conﬁgured for displaying 16x16 dot characters

Figure 9-1 OSD Character and Row Structure

Character Code Register (even bytes)

Character Attribute Register (odd bytes)

$23E

ROW BUFFER 0

$23F

$27E

ROW BUFFER 1

$27F

$2BE

ROW BUFFER 2

$2BF

$2FE

ROW BUFFER 3

$2FF

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Code $00 Code $20 : Blank Code $7F : Full-Filled

Figure 9-2 Reserved Character ROM Codes

9.3.3 Character Registers

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Character Code reg. 1 $200

Character Attribute reg. 1 $201 BLNKG BGEN

Character Code reg. 128 $2FE

Character Attribute reg. 128 $2FF BLNKG BGEN

ROM/RAM

CH6 CH5 CH4 CH3 CH2 CH1 CH0 uuuu uuuu

BGCOL2 BGCOL1 BGCOL0

CH6 CH5 CH4 CH3 CH2 CH1 CH0 uuuu uuuu

BGCOL2 BGCOL1 BGCOL0

CCOL2 CCOL1 CCOL0 uuuu uuuu

: :

CCOL2 CCOL1 CCOL0 uuuu uuuu

There are a total of 128 character code registers, 32 characters per row for four rows.

Character Codes:

ROM/RAM - ROM/RAM mapping select

1 (set) – CH6-CH0 is mapped to the 16 RAM codes. 0 (clear) – CH6-CH0 is mapped to the 128 ROM/EPROM codes.

CH6-CH0

0 to 127 = ROM/EPROM codes. 0 to 15 = RAM codes. Codes 16 and higher are invalid.

State

on reset

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Character attributes:

BLNKG - Character blinking on/off

1 (set) – Character blinking enabled. 0 (clear) – Character blinking disabled.

The blinking speed is controlled by BR1 and BR0 in Frame Control register 2.

BGEN - Character background display on/off

1 (set) – Character background display enabled. 0 (clear) – Character background display disabled.

BGCOL2, BGCOL1, BGCOL0 - Character background color select

Selects a color from the color palette. See Section 9.3.4.

CCOL2, CCOL1, CCOL0 - Character color select

Selects a color from the color palette. See Section 9.3.4.

9.3.4 Color Palette Registers

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$1F I1 R1 G1 B1 I0 R0 G0 B0 0000 0000 $20 I3 R3 G3 B3 I2 R2 G2 B2 0000 0000 $21 I5 R5 G5 B5 I4 R4 G4 B4 0000 0000 $22 I7 R7 G7 B7 I6 R6 G6 B6 0000 0000

Ii, Ri, Gi, and Bi bits select the color for color palette i, where i=0, 1, 2,..., 7. I bit is the intensity bit. There are 8 color palettes; each color palette is one of 16 colors. Figure 9-3 shows the color palette organization and Table 9-1 shows the RGB color map.

Palette 0 Palette 1 Palette 2 Palette 3 Palette 4 Palette 5 Palette 6 Palette 7

Color selected using Ii, Ri, Gi, and Bi

16 available colors

Figure 9-3 Color Palette Organization

MOTOROLA 9-6

State

on reset

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9.4 Row

Table 9-1 RGB Color Map

Ii Ri Gi Bi Color

0000 Black 0001 Blue 0010 Green 0011 Cyan 0100 Red 0101 Magenta 0110 Yellow 0111 White 1000 Dark Grey 1001 Dark Blue 1010 Dark Green 1011 Dark Cyan 1100 Dark Red 1101 Dark Magenta 1110 Dark Yellow 1111 Light Grey

Bit deﬁnitions may be reversed, depending on the chroma unit in the TV

The OSD module has 4 row buffers for displaying on-screen characters; row 0, 1, 2 and 3. Each row buffer consists of 32 pairs of Char acter register pairs (See Section 9.3). There are 5 registers which affects the position and attributes of the display rows.

9.4.1 Row Attribute Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$23 MTRX3 MTRX2 MTRX1 MTRX0 R3BE R2BE R1BE R0BE 0000 0000

MTRXi - Character dot matrix select for row i

1 (set) – 12x16 character dot matrix selected for row i. 0 (clear) – 16x16 character dot matrix selected for row i.

If 12 x16 matr ix is selected, a maximum of 32 characters may be displayed for that row. Rows selected for 16x 16 matrix characters, the maximum is 24 characters per row; the remaining 8

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Character register pairs are not used. See Figure 9-1. Unused Character register pairs may be used as general purpose RAM.

RiBE - Black-edge for row i enable

1 (set) – Black-edge (bordering or shadowing) for row i enabled. 0 (clear) – Black-edge (bordering or shadowing) for row i disabled.

This bit is the enable bit for the shadowing and bordering option selected by the SHDW bit in the OSD Row Horizontal Position register (bit 7 of address $28).

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Horizontal Position Register $28 SHDW HP6 HP5 HP4 HP3 HP2 HP1 HP0 0000 0000

SHDW - Shadow/border select

1 (set) – Shadow feature is selected if RiBE is enabled. 0 (clear) – Border feature is selected if RiBE is enabled.

This bit does not have any effect if RiBE bit is disabled.

9.4.2 Row Vertical Position Registers

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Row 0 Vertical Position Register $24 Row 1 Vertical Position Register $25 Row 2 Vertical Position Register $26 Row 3 Vertical Position Register $27

FBKGCi - FBKG (Fast Blanking) pin active select

1 (set) – FBKG pin is active during row i character dots only.

FBKGC0

R0VP6 R0VP5 R0VP4 R0VP3 R0VP2 R0VP1 R0VP0 0000 0000

FBKGC1

R1VP6 R1VP5 R1VP4 R1VP3 R1VP2 R1VP1 R1VP0 0000 0000

FBKGC2

R2VP6 R2VP5 R2VP4 R2VP3 R2VP2 R2VP1 R2VP0 0000 0000

FBKGC3

R3VP6 R3VP5 R3VP4 R3VP3 R3VP2 R3VP1 R3VP0 0000 0000

State

on reset

State

on reset

0 (clear) – FBKG pin is active during both row i character and row i background

dots.

FBKGCi bit controls the FBKG output pin of the OSD during row i display . If FBKGCi is clear , FBKG output pin is active during both character dots and background dots of row i. If FBKGCi is set, FBKG output pin is active only where character dots exist in the character dot matrix (including bordering or shadowing dots). The FBKG and HTONE pins may be used to create transparent background effects for OSD displays.

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Figure 9-4 and Figure 9-5 illustrate the timing signals of R, G, B, I, FBKG, and HTONE as a function of control bits BGEN, RiBE, and FBKGCi, using the 5th line (line 4) of a 12x16 dot matrix as an example. All output signals assume positive polarity.

Figure 9-4 illustrates the timing of output signals for characters with and without bordering effect. Figure 9-5 illustrates the output signal timing for characters with background enabled, yet with opposite FBKGCi bit setting. Note that both RiBE and FBKGCi are row features. Hence, the two adjacent dot matrices in both ﬁgures are drawn for demonstration purposes only , the y do not imply that users can conﬁgure OSD display in such a manner that one character has FBKGCi bit set and the next character in the same row has FBKGCi bit cleared. Note that ‘HTONE’ has exactly the same wavef orm as ‘Bac kground R,G,B, or I’. Output signal timing diagram similar to Figure 9-5 for the case where character bordering is enabled can be derived in very similar fashion. The only difference is that ‘FBKG’ will be on and ‘HTONE’ will be off where a bordering dot exists. Other output signal timings remain the same.

RiVP6 to RiVP0 - Row i Vertical Position

For single scan mode: Vertical position = RiVPx setting x 4 For double scan mode: Vertical position = RiVPx setting x 4 x 2 Each RiVP6-RiVP0 step shifts the vertical position of row i by 4 horizontal display lines. For single

scan mode, the shift is (RiVP6-RiVP0)x 4 horizontal lines. For double scan mode, the shift is ((RiVP6-RiVP0) x 4) x 2 horizontal lines. The calculation of shift is a function of scan mode, not character size selection. Hence, care should be taken when choosing vertical position for a particular row that locates after a row which has character size other than the basic 12x 16 or 16x16 setting. For example , assuming single scan mode, if row X has 4Hx4V character size and vertical position of $40 while row Y has basic character size of 1Hx1V and vertical position of $48, then row X will be displayed from the 256th (64x4) line to the 287th line, which covers only the ﬁrst 32 lines of the supposed 64-line row X display, and row Y will be displayed from the 288th (72x4) line to 303th line without any missing lines.

The reference point of shift is the leading edge of vertical ﬂyback input signal, VFLBK. As a result of this vertical start position granularity, there are a total of 262.5/4 row positions in a full screen.

In Figure 9-6(a), row (i+1) and row i partially overlaps. Since the vertical position of row (i+1) is lower than row i, row (i+1) will be partially covered b y row i. New symbols may be generated when rows are partially overlapped.

In Figure 9-6(b), row (j+1) is completely covered by row j. As result, only row j is visible. Note that in cases where the character size of the blocked row is bigger than that of the blocking

row, once the blocked row has been blocked, it will never be displayed again even after the blocking row displa y has been terminated. For example, assume the character size of row (i+1) is 4H x4V and that of row i is 1H x1V, and the difference in vertical position between them is 4 horizontal lines only. After the ﬁrst four lines of row (i+1) have been displayed, row i display will commence and continue for the next sixteen lines, blocking off row (i+1) display for these sixteen lines. After row i display has been terminated, there are still (64-4-16)=44 lines of row (i+1) display

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Timing signals for 5th line (line 4)

Background R, G, B, or I

Char R, G, B, or I

R, G, B, or I

FBKG

HTONE

RiBE= 0, BGEN=0, FBKGCi= X RiBE =1, SHDW= 0, BGEN=0, FGKGCi=X

Figure 9-4 Output Signal Timing Diagram - Without Background

that could have been displayed, the OSD is so designed that these remaining lines will not be displayed. The same result applies to the complete overlap situation with different character sizes.

A row display is terminated if:

1) the part of the row display which is not overridden by other overlapping rows has been completed, or

2) it completely overlaps a row or rows with higher priority, or

3) the part of the row display which does not overlap vertical retrace period has been completed. (This applies to rows immediately before vertical retrace)

Note that the judgement of overlap is totally based on the vertical position of rows, it has nothing to do with character size of rows. RiCF bit of Frame Control 3 and Status register will also be set when a row display is terminated.

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Timing signals for 5th line (line 4)

Char R, G, B, or I

Background

R, G, B, or I

FBKG

HTONE

FBKGCi= 0, BGEN=1, RiBE= 0 FBKGCi=1, BGEN =1, RiBE= 1, SHDW=1

background dot character dot shadow dot

Figure 9-5 Output Signal Timing Diagram - With Background

Row (i+1)

Row (i+1) partially overlaps row i

Row i

Row (j+1)

Row j

(a)

Row (j+1) and row j completely overlaps, therefore

(b)

only row j is visible

Figure 9-6 Resolution of Overlap among Rows

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9.4.3 Row Horizontal Position Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$28 SHDW HP6 HP5 HP4 HP3 HP2 HP1 HP0 0000 0000

SHDW - Shadow/border select

1 (set) – Shadow feature is selected if RiBE is enabled. See Section 9.4.1. 0 (clear) – Border feature is selected if RiBE is disabled. See Section 9.4.1.

HP6 to HP0 - Horizontal Position

Each (HP6-HP0) step shifts the horizontal position of all four rows by 4 dots . The reference point of shift is the leading edge of horizontal ﬂyback signal. Note that there is only one Row Horizontal Position register for all 4 row buffers, therefore all rows will have the same horizontal start point.

If (HP6-HP0) is so programmed that part of the row display goes beyond the beginning of a horizontal ﬂyback signal, display wrap-around occurs . That is, all lines of the row display will ha ve all dots before the nth horizontal ﬂyback displa y ed on one line and all remaining dots after the nth horizontal ﬂyback, along with all dots of next line before the (n+1)th horizontal ﬂyback displayed on the next line.

State

on reset

9.4.4 Row Control Register 1

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$29 R3INTE R2INTE R1INTE R0INTE R3EN R2EN R1EN R0EN 0000 0000

State

on reset

RiINTE - Row interrupt

1 (set) – Row interrupt enabled. 0 (clear) – Row interrupt disabled.

Enable/disable interrupt of row i if one of the following conditions occur:

1) the part of the row i display which is not overridden by other overlapping rows has been completed, or

2) the part of the row i display which does not overlap vertical retrace period has been completed.

Note that for the case where row i is completely ov erlapped by other ro ws, ro w i displa y has ne v er really happened, that is, terminated upon its commencement, row i interrupt will never occur.

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RiEN - Row i display enable

1 (set) – Row i display enabled. 0 (clear) – Row i display disabled.

If RiEN bit is set while the horizontal line currently being displayed has already passed the v ertical start position of this recently enabled row, this recently enabled row will not be displayed in this frame. It will then be displayed in the next frame. That is, RiEN bit has to be set before current horizontal display line reaches ((RiVP6-RiVP0)x4) for single scan mode or ((RiVP6-RiVP0)x4)x2 for double scan mode to enable display of row i in current frame.

Note that clearing RiEN bit does not clear the corresponding RiCF bit. Hence, care must be tak en before enabling RiINTE and RiEN to avoid interrupt caused by uncleared RiCF before the setting of RiINTE and RiEN.

9.4.5 Row Control Register 2

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$2A R3CHS1 R3CHS0 R2CHS1 R2CHS0 R1CHS1 R1CHS0 R0CHS1 R0CHS0 0000 0000

RiCHS1, RiCHS0 - Row i character size

RiCHS1 RiCHS0 Character size of row i

0 0 basic - 1H x1V 0 1 Single expanded - 2Hx2V 1 0 Double expanded - 3Hx3V 1 1 Triple expanded - 4Hx4V

There are two predeﬁned numbers of total dots that can be displayed on a horizontal line. The number of dots per line is a function of character size selection and the size of character dot matrix. For the special case of 3H x3V and 12x16 dot matrix, the number of total dots per line is 396; whereas f or other combinations of char acter siz e and dot matrix, the number is 384 dots per line. Users can avoid ﬁlling the unused bytes in a row since these bytes will not be displayed. Table 9-2 lists the number of valid character bytes per row.

State

on reset

9.5 Frame

The following registers affect the frame of an OSD displays.

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Table 9-2 Number of Visible Characters Per Row

char size

1H x 1V 2H x 2V 3H x 3V 4H x 4V

dot matrix

16x16 12x16

24 12

8 6 8

32 16

9.5.1 Frame Control 1 and Row Count Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$1D PLLEN DSCAN FADE ON/OFF CDRC3 CDRC2 CDRC1 CDRC0 0000 0000

Bits 7 to 4 are control bits and, bits 3 to 0 are status bits.

PLLEN - PLL enable bit

1 (set) – PLL enabled for OSD clock source. 0 (clear) – PLL disabled.

DSCAN - Double/Single scan mode select

1 (set) – Double scan mode. 0 (clear) – Single scan mode.

State

on reset

DSCAN (double scan) bit is for the control of OSD logic so that the OSD can accommodate non-interlaced scan TV system by adjusting dot matrix scan output. Users hav e to determine if the target TV broadcast system is a double scan system. If DSCAN is set, all horizontal lines in the character dot matrix will be displayed twice in the same frame. The other feature associated with horizontal lines that will also be doubled is the RiVP6-RiVP0 ﬁeld of Row Vertical Position Registers.

FADE - Display fade enable

1 (set) – Display fade function enabled. 0 (clear) – Display fade function disabled.

The FADE bit controls the sequence of frame display appearance and disappearance. When FADE bit is set, frame display will gradually appear (fade in) if ON/OFF is set, and gradually disappear (fade out) if ON/OFF is clear. If FADE bit is clear, OSD display will be turned on or off instantly.

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ON/OFF - OSD display on/off

1 (set) – OSD display on. 0 (clear) – OSD display off.

For the fading f eature, the whole screen is divided into se veral 16-horizontal-line segments . Notice that a row might not ﬁt into the 16-horizontal-line segments. It might cross two segments, depending on the vertical position of a row. The way that fade-in feature works is that one line in all 16-line segments will appear in the ﬁrst fading sequence; two lines, including the one line in the ﬁrst fading sequence, will appear in the second f ading sequence; four lines , including the two lines in the second fading sequence, will appear in the third f ading sequence; eight lines, including the four lines in the third fading sequence, will appear in the fourth fading sequence; and ﬁnally, all sixteen lines, including the eight lines in the fourth fading sequence, will appear in the ﬁfth fading sequence. Fade-out feature works in the opposite manner, that is, the number of display lines to be disappeared are 8 lines, 12 lines, 14 lines, 15 lines, and all 16 lines in each disappearance sequence, respectively. Fade out sequence for a character in a row ﬁtting right into the 16-horizontal-line segment is illustrated in Figure 9-7. Fading rate is ﬁxed at 32 frames per sequence. Therefore , it takes 160 fr ames to ex ecute the f ade function. At 60 Hz v ertical frequency , this will take ﬁve plus seconds. Note that when display disappears, all output pins are not tri-stated, rather they remain in their deserted states.

CDRC3 to CDRC0 - Terminated display rows

These status bits reﬂect the number of row displays that have been terminated. These bits are reset only by vertical ﬂyback and incremented by one every time a row display has been terminated.

9.5.2 Frame Control Register 2

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$1E BR1 BR0 VFPOL HFPOL HTPOL FBPOL RGBPOL IPOL 0000 0000

BR1, BR0 - Blink rate select

These bits control the blinking rate of all symbols on the TV screen. The on/off ratio of blinking is always 3/1.

VFPOL - VFLBK input polarity select

1 (set) – Vertical ﬂyback signal at VFLBK is active low. 0 (clear) – Vertical ﬂyback signal at VFLBK is active high.

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Before fading out 1st step: 8 lines off

2nd step: 12 lines off 3rd step: 14 lines off

Figure 9-7 Fading Out Sequence

MOTOROLA 9-16

Last step: all 16 lines off4th step: 15 lines off

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BR1 BR0

0 0 24 8 0 1 48 16 1 0 96 32 1 1 192 64

HFPOL - HFLBK input polarity select

1 (set) – Horizontal ﬂyback signal at HFLBK is active low. 0 (clear) – Horizontal ﬂyback signal at HFLBK is active high.

HTPOL - FBKG output polarity select

1 (set) – HTONE (half tone) output pin is active low. 0 (clear) – HTONE (half tone) output pin is active high.

The HTONE output pin is shared with port pin PF3. If HTONE is disabled, HTPOL will have no effect.

FBPOL - FBKG output polarity select

1 (set) – FBKG (fast blanking) output pin is active low. 0 (clear) – FBKG (fast blanking) output pin is active high.

On-Time (frames)

Off-Time (frames)

RGBPOL - RGB output polarity select

1 (set) – RBG output pins are active low. 0 (clear) – RGB output pins are active high.

IPOL - I output polarity select

1 (set) – I (intensity) output pin is active low. 0 (clear) – I (intensity) output pin is active high.

9.5.3 Frame Control 3 and Status Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$2B VFINTE MUTE1 MUTE0 VFLB R3CF R2CF R1CF R0CF 0000 0000

Bits 7 to 5 are control bits whereas bits 4 to 0 are status bits associated with interrupt. A status bit is cleared by writing a 0 to that bit. Care must be taken while clearing a status bit: make sure the

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status bit to be cleared is indeed one before writing a zero, and do not write a 0 to a status bit which is not 1. Otherwise, status bits which are becoming ones will be inadvertently cleared.

VFINTE - VFLBK interrupt enable

1 (set) – Vertical ﬂyback interrupt enabled. 0 (clear) – Vertical ﬂyback interrupt disabled.

MUTE1, MUTE0 - Video mute enable

MUTE1 MUTE0 Function

0 0 No video mute 0 1 Mute with black color 1 0 Mute with G color 1 1 Mute with B color

VFLB - VFLBK status

1 (set) – Vertical ﬂyback (leading edge) signal detected. 0 (clear) – No Vertical ﬂyback signal detected.

RiCF - Row i display status

1 (set) – Row i display has been terminated.

0 (clear) – Row i display has been not terminated.

Whenever a row display has been terminated, the corresponding RiCF ﬂag will be set along with update of CDRC3-CDRC0 ﬁeld.

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ANALOG TO DIGITAL CONVERTER

The Analog-to-Digital Converter (ADC) system consists of two analog input channels and a single 5-bit D/A Converter and Comparator, with continuous conversion. A result ﬂag indicates if the comparator output is above or below the analog Input. ADC is disabled by setting AD4 to AD0 bits of ADC Control/Status register to all 1’s. This disable function is mainly for low po wer applications .

Figure 10-1 shows a block diagram of the ADC module.

RESULT

– +

Figure 10-1 ADC Block Diagram

ADCIN0 or ADCIN1

AD4

AD3

AD2

AD1

AD0

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10.1 ADC Inputs

The ADC has two input channels: one dedicated input pin at ADCIN0 and one shared pin at PF4/ADCIN1.

10.1.1 PF4/ADCIN1

ADCIN1 multiplexes with PF4 at this pin. When the ADC1 bit of Port F Conﬁguration register is cleared, PF4/ADCIN1 is conﬁgured for PF4 and follows Port F DDR assignment. When ADC1 bit is set, PF4 is conﬁgured as ADCIN1 analog input, and Port F DDR has no effect on this pin. Reading PF4 when conﬁgured as an ADC input is zero.

10.1.2 ADCIN0

ADCIN0 is a dedicated analog input channel.

10.2 Program Example

The following example shows how to convert analog input channel 0 (ADCIN0). For ADCIN1 conversion, change #$00 to #$20. ADCSR is the ADC Control/Status register.

LDA #$00 STA ADCSR ;ADC Control and Status Register

DTA BRSET 7, ADCSR, ATD

INC ADCSR LDA ADCSR AND #$1F CMP #$1F

BLS DTA ;out of range ATD ... ;analog value in ADC.

;ANALOG IN = ([AD4:0] +1)*0.15625V at Vdd = 5V

MOTOROLA 10-2

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10.3 ADC Control and Status Register

Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

$3C RESULT CHNL AD4 AD3 AD2 AD1 AD0 u000 0000

This read/write register, located at address $3C, contains six control bits and one status bit.

RESULT - Comparator Status (Read Only)

1 (set) – AD4-0 value greater than analog in. 0 (clear) – AD4-0 value is less than analog in.

CHNL - Channel Select

1 (set) – ADCIN1 is selected for conversion. 0 (clear) – ADCIN0 is selected for conversion

AD4-0 - ADC Digital Result

These bits are written by the user to perform successive approximations in softw are. When a value causes the RESULT bit to change state from the value immediately before or after it, AD4-0 are considered to be the digital equivalent of the analog input. Note that when AD4-0 are all 1’s, ADC is virtually turned off to minimize power consumption.

State

on reset

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MOTOROLA 10-4

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CPU CORE AND INSTRUCTION SET

This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05L1.

11.1 Registers

The MCU contains ﬁve registers, as shown in the progr amming model of Figure 11-1. The interrupt stacking order is shown in Figure 11-2.

15 7 0

0 0 0 0 0 0 1 1

70 1

11HINZC

Figure 11-1 Programming model

Accumulator

Index register

Program counter

Stack pointer

Condition code register

Carry / borrow Zero Negative Interrupt mask Half carry

11.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.

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Stack

Interrupt

Decreasing

memory address

Increasing

memory

address

Unstack

Return

Condition code register

Accumulator

Index register

Program counter high

Program counter low

Figure 11-2 Stacking order

11.1.2 Index register (X)

The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area.

11.1.3 Program counter (PC)

The program counter is a 16-bit register, which contains the address of the ne xt byte to be f etched.

11.1.4 Stack pointer (SP)

The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack.

When accessing memory, the ten most signiﬁcant bits are permanently set to 0000000011. These ten bits are appended to the six least signiﬁcant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies tw o locations on the stack; an interrupt uses ﬁve locations.

11.1.5 Condition code register (CCR)

The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the ﬁfth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and speciﬁc actions can be taken as a result of their state. Each bit is explained in the following paragraphs.

Half carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

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Interrupt (I)

When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared.

Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative.

Zero (Z)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.

Carry/borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.

11.2 Instruction set

The MCU has a set of 62 basic instructions. They can be grouped into ﬁve different types as follows:

– Register/memory – Read/modify/write – Branch – Bit manipulation – Control

The following paragraphs brieﬂy explain each type. All the instructions within a given type are presented in individual tables.

This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 11-1.

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11.2.1 Register/memory Instructions

Most of these instructions use two operands. The ﬁrst operand is either the accumulator or the index register . The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 11-2 for a complete list of register/memory instructions.

11.2.2 Branch instructions

These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 11-3.

11.2.3 Bit manipulation instructions

The MCU can set or clear any writable bit that resides in the ﬁrst 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 11-4.

11.2.4 Read/modify/write instructions

These instructions read a memory location or a register, modify or test its contents, and write the modiﬁed value back to memory or to the register. The test for negative or z ero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 11-5 for a complete list of read/modify/write instructions.

11.2.5 Control instructions

These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 11-6 for a complete list of control instructions.

11.2.6 Tables

Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 11-8).

MOTOROLA 11-4

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Page 97

Table 11-1 MUL instruction

Operation X:A ← X*A

Multiplies the eight bits in the index register by the eight

Description

bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register.

H : Cleared

Condition

codes

I : Not affected N : Not affected Z : Not affected C : Cleared

Source MUL

Form

Addressing mode Cycles Bytes Opcode

Inherent 11 1 $42

Table 11-2 Register/memory instructions

Addressing modes

Immediate Direct Extended

Function

Mnemonic

Opcode

# Bytes

# Cycles

Opcode

# Bytes

# Cycles

Opcode

Load A from memory LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5 Load X from memory LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5 Store A in memory STA Store X in memory STX Add memory to A ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5 Add memory and carry to A ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5 Subtract memory SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5 Subtract memory from A

with borrow AND memory with A AND A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 5 OR memory with A ORA AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5 Exclusive OR memory with A EOR A8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 D8 3 5 Arithmetic compare A

with memory Arithmetic compare X

with memory Bit test memory with A

(logical compare) Jump unconditional JMP Jump to subroutine JSR

SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5

CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5

CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5

BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5

B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6 BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6

BC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4 BD 2 5 CD 3 6 FD 1 5 ED 2 6 DD 3 7

# Bytes

Indexed

(no

offset)

# Cycles

Opcode

# Bytes

Indexed

(8-bit

offset)

# Cycles

Opcode

# Bytes

Indexed

(16-bit offset)

# Cycles

Opcode

# Bytes

# Cycles

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MC68HC05L1 MOTOROLA

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11-5

Page 98

Table 11-3 Branch instructions

Relative addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Branch always BRA 20 2 3 Branch never BRN 21 2 3 Branch if higher BHI 22 2 3 Branch if lower or same BLS 23 2 3 Branch if carry clear BCC 24 2 3 (Branch if higher or same) (BHS) 24 2 3 Branch if carry set BCS 25 2 3 (Branch if lower) (BLO) 25 2 3 Branch if not equal BNE 26 2 3 Branch if equal BEQ 27 2 3 Branch if half carry clear BHCC 28 2 3 Branch if half carry set BHCS 29 2 3 Branch if plus BPL 2A 2 3 Branch if minus BMI 2B 2 3 Branch if interrupt mask bit is clear BMC 2C 2 3 Branch if interrupt mask bit is set BMS 2D 2 3 Branch if interrupt line is low BIL 2E 2 3 Branch if interrupt line is high BIH 2F 2 3 Branch to subroutine BSR AD 2 6

Table 11-4 Bit manipulation instructions

Addressing modes

Bit set/clear Bit test and branch

Function Mnemonic Opcode # Bytes # Cycles Opcode # Bytes # Cycles

Branch if bit n is set BRSET n (n=0–7) Branch if bit n is clear BRCLR n (n=0–7) 01+2•n 3 5 Set bit n BSET n (n=0–7) 10+2•n 2 5 Clear bit n BCLR n (n=0–7) 11+2•n 2 5

2•n 3 5

MOTOROLA 11-6

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MC68HC05L1CPU CORE AND INSTRUCTION SET

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Table 11-5 Read/modify/write instructions

Addressing modes

# Cycles

Indexed

(no

offset)

Opcode

# Bytes

Inherent

(A)

Function

Mnemonic

Opcode

# Bytes

Increment INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6 Decrement DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6 Clear CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6 Complement COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 Negate (two’s complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5 Multiply MUL 42 1 11

# Cycles

Inherent

(X)

Opcode

# Bytes

# Cycles

Direct

Opcode

# Bytes

# Cycles

Indexed

(8-bit

offset)

Opcode

# Bytes

Table 11-6 Control instructions

# Cycles

Inherent addressing mode

Function Mnemonic Opcode # Bytes # Cycles

Transfer A to X TAX 97 1 2 Transfer X to A TXA 9F 1 2 Set carry bit SEC 99 1 2 Clear carry bit CLC 98 1 2 Set interrupt mask bit SEI 9B 1 2 Clear interrupt mask bit CLI 9A 1 2 Software interrupt SWI 83 1 10 Return from subroutine RTS 81 1 6 Return from interrupt RTI 80 1 9 Reset stack pointer RSP 9C 1 2 No-operation NOP 9D 1 2 Stop STOP 8E 1 2 Wait WAIT 8F 1 2

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MC68HC05L1 MOTOROLA

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Table 11-7 Instruction set

Mnemonic

INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C

Addressing modes Condition codes

ADC ◊ • ◊◊◊ ADD ◊ • ◊◊◊ AND ••◊◊•

ASL ••◊◊◊

ASR ••◊◊◊ BCC •••••

BCLR •••••

BCS •••••

BEQ ••••• BHCC ••••• BHCS •••••

BHI •••••

BHS •••••

BIH ••••• BIL ••••• BIT ••◊◊•

BLO •••••

BLS •••••

BMC •••••

BMI ••••• BMS ••••• BNE

•••••

BPL ••••• BRA ••••• BRN •••••

BRCLR ••••◊ BRSET ••••◊

BSET •••••

BSR ••••• CLC ••••0

CLI •0•••

CLR ••01• CMP • • ◊◊◊

Address mode abbreviations

BSC Bit set/clear IMM Immediate BTB Bit test & branch IX Indexed (no offset) DIR Direct IX1 Indexed, 1 byte offset EXT Extended IX2 Indexed, 2 byte offset INH Inherent REL Relative

Not implemented

MOTOROLA 11-8

Condition code symbols

H Half carr y (from bit 3) ◊

I Interrupt mask • Not affected

N Negate (sign bit) ? Load CCR from stack

Z Zero 0 Cleared

C Carr y/borrow 1 Set

Tested and set if true, cleared otherwise

MC68HC05L1CPU CORE AND INSTRUCTION SET

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Motorola MC68HC05T16, MC68HC705T16 Technical Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

GENERAL DESCRIPTION

1.1 Features

2.1 PIN DESCRIPTIONS

2.2 INPUT/OUTPUT PORTS

2.2.1 Input/Output Programming

MEMORY AND REGISTERS

3.1 Memory Map

3.2 Input/Output Section

3.3 RAM

RESETS AND INTERRUPTS

4.1 RESETS

4.1.1 Power-On Reset (POR)

4.1.2 RESET Pin

4.1.3 Computer Operating Properly (COP) Reset

4.2 INTERRUPTS

4.2.1 Hardware Controlled Sequences

4.2.2 Software Interrupt (SWI)

4.2.3 External Interrupt (IRQ)

4.2.4 Programmable Timer Interrupt

4.2.5 M-Bus Interrupts

4.2.6 PAC Interrupt

4.2.7 OSD Interrupts

4.2.8 Multi-Function Timer Interrupts

TIMERS

5.1 PR OGRAMMABLE TIMER

5.1.1 Counter

5.1.2 Output Compare Registers

5.1.3 Input Capture Registers

5.1.4 Timer Control Register (TCR)

5.1.6 Programmable Timer Timing Diagrams

5.2 MUL TI-FUNCTION TIMER

5.2.1 COP Watchdog Reset

M-BUS SERIAL INTERFACE

6.1 M-Bus Interface Features

6.2 M-Bus Protocol

6.2.1 START Signal

6.2.2 Slave Address Transmission

6.2.3 Data Transfer

6.2.4 Repeated START Signal

6.2.5 STOP Signal

6.2.6 Arbitration Procedure

6.2.7 Clock Synchronization

6.2.8 Handshaking

6.3 M-Bus Registers

6.3.3 M-Bus Control Register (MCR)

6.3.4 M-Bus Status Register (MSR)

6.3.5 M-Bus Data I/O Register (MDR)

PULSE ACCUMULATOR

7.1 Pulse Accumulator Registers

7.1.2 PAC Counter Register

PULSE WIDTH MODULATOR

8.1 7-Bit PWM Channels

8.2 14-Bit PWM Channel

ON-SCREEN DISPLAY

9.1 Introduction

9.2 Features

9.3 Characters

9.3.1 Character RAM

9.3.2 Character ROM/EPROM

9.4 Row

9.4.1 Row Attribute Register

9.4.3 Row Horizontal Position Register

9.5 Frame

9.5.3 Frame Control 3 and Status Register

ANALOG TO DIGITAL CONVERTER

10.1 ADC Inputs

10.1.1 PF4/ADCIN1

10.1.2 ADCIN0

10.2 Program Example

10.3 ADC Control and Status Register

CPU CORE AND INSTRUCTION SET

11.1 Registers

11.1.1 Accumulator (A)