Motorola MC68HC05RC8, MC68HC05RC16 User Manual
HC05RC16GRS/D
REV. 3.0
MC68HC05RC8
MC68HC05RC16
General Release Specification
October 24, 1996
CSIC MCU Design Center
Austin, Texas
NON-DISCLOSURE AGREEMENT REQUIRED
General Release Specification
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
NON-DISCLOSURE AGREEMENT REQUIRED
© Motorola, Inc., 1996 MC68HC05RC16 — Rev. 3.0
2 MOTOROLA
General Release Specification — MC68HC05RC16
Section 1. General Description . . . . . . . . . . . . . . . . . . . 15
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Section 3. Central Processor Unit . . . . . . . . . . . . . . . . . 33
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
List of Sections
Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . 53
Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 57
Section 8. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Section 9. Carrier Modulator Transmitter (CMT) . . . . . . 67
Section 10. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 85
Section 11. Electrical Specifications . . . . . . . . . . . . . . 103
Section 12. Mechanical Specifications . . . . . . . . . . . 111
Section 13. Ordering Information . . . . . . . . . . . . . . . . 115
Appendix A. MC68HC05RC8 . . . . . . . . . . . . . . . . . . . . 119
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA List of Sections 3
List of Sections
General Release Specification MC68HC05RC16 — Rev. 3.0
4 List of Sections MOTOROLA
General Release Specification — MC68HC05RC16
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.1 V
1.5.2
1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.4
1.5.5
1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.7 PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.8 PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.9 PC0–PC3 (PC4–PC7). . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DD
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .23
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table of Contents
Section 2. Memory
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.2 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Table of Contents 5
Table of Contents
Section 3. Central Processor Unit
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.4 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.6 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.7 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Section 4. Interrupts
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.3 CPU Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.4 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.6 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.7 External Interrupt (
4.8 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.9 Carrier Modulator Transmitter Interrupt (CMT). . . . . . . . . . . . .42
4.10 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
IRQ/Port B Keyscan). . . . . . . . . . . . . . . . . .41
Section 5. Resets
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.3 External Reset (
5.4 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .48
RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
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Table of Contents
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.5.2 Computer Operating Properly Reset (COPR). . . . . . . . . . .49
5.5.2.1 Resetting the COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.5.2.4 COP Watchdog Timer Considerations. . . . . . . . . . . . . . .50
5.5.2.5 COP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.5.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 6. Low-Power Modes
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.4 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.6 Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Section 7. Parallel Input/Output (I/O)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7.6 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Table of Contents 7
Table of Contents
Section 8. Core Timer
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.3 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .63
8.4 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .65
8.5 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . .66
8.6 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Section 9. Carrier Modulator Transmitter (CMT)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
9.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.4.2 Carrier Generator Data Registers
(CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . .72
9.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
9.5.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
9.5.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.5.3 Extended Space Operation. . . . . . . . . . . . . . . . . . . . . . . . .78
9.5.3.1 End Of Cycle (EOC) Interrupt . . . . . . . . . . . . . . . . . . . . .79
9.5.3.2 Modulator Control and Status Register . . . . . . . . . . . . . .80
9.5.4 Modulator Period Data Registers
(MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .83
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8 Table of Contents MOTOROLA
Table of Contents
Section 10. Instruction Set
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.3.1 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.3.3 Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.3.4 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
10.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .90
10.4.2 Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . . .91
10.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .94
10.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Section 11. Electrical Specifications
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.6 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .106
11.7 DC Electrical Characteristics (2.2 Vdc). . . . . . . . . . . . . . . . . .107
11.8 Control Timing (5.0 Vdc and 2.2 V
) . . . . . . . . . . . . . . . . . . .109
dc
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Table of Contents 9
Table of Contents
Section 12. Mechanical Specifications
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.3 28-Pin Plastic Dual In-Line Package
(Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
12.4 28-Pin Small Outline Integrated Circuit Package
(Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
12.5 44-Pin Plastic Leaded Chip Carrier Package
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Section 13. Ordering Information
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .116
13.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .117
13.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .118
13.7 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Appendix A. MC68HC05RC8
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
A.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
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10 Table of Contents MOTOROLA
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Figure Title Page
1-1 MC68HC05RC16 Block Diagram. . . . . . . . . . . . . . . . . . . . .18
1-2 28-Pin DIP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1-3 28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1-4 44-Pin PLCC Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1-5 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2-1 MC68HC05RC16 Memory Map . . . . . . . . . . . . . . . . . . . . . .28
2-2 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3-1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3-2 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of Figures
4-1 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .40
4-2 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .41
5-1 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5-2 Reset and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . .47
5-3 COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .51
6-1 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .54
6-2 Stop/Wait Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7-1 Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7-2 I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8-1 Core Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .62
8-2 Core Timer Control and Status Register (CTCSR) . . . . . . .63
8-3 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .65
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA List of Figures 11
List of Figures
Figure Title Page
9-1 Carrier Modulator Transmitter Module Block Diagram. . . . .69
9-2 Carrier Generator Block Diagram. . . . . . . . . . . . . . . . . . . . .70
9-3 Carrier Generator Data Register CHR1 . . . . . . . . . . . . . . . .72
9-4 Carrier Generator Data Register CLR1 . . . . . . . . . . . . . . . .72
9-5 Carrier Generator Data Register CHR2 . . . . . . . . . . . . . . . .72
9-6 Carrier Generator Data Register CLR2 . . . . . . . . . . . . . . . .73
9-7 Modulator Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .75
9-8 CMT Operation in Time Mode . . . . . . . . . . . . . . . . . . . . . . .77
9-9 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .79
9-10 Modulator Control and Status Register (MCSR) . . . . . . . . .80
9-11 Modulator Period Data Register MDR1 . . . . . . . . . . . . . . . .83
9-12 Modulator Period Data Register MDR2 . . . . . . . . . . . . . . . .83
9-13 Modulator Period Data Register MDR3 . . . . . . . . . . . . . . . .83
11-1 Maximum Supply Current versus Internal
Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
A-1 MC68HC05RC8 Memory Map . . . . . . . . . . . . . . . . . . . . .120
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Table Title Page
4-1 Vector Address for Interrupts and Reset................................38
5-1 COP Watchdog Timer Recommendations .............................50
7-1 I/O Pin Functions....................................................................59
8-1 RTI and COP Rates at 4.096 MHz Oscillator.........................64
10-1 Register/Memory Instructions.................................................90
10-2 Read-Modify-Write Instructions..............................................91
10-3 Jump and Branch Instructions................................................93
10-4 Bit Manipulation Instructions...................................................94
10-5 Control Instructions.................................................................95
10-6 Instruction Set Summary........................................................96
10-7 Opcode Map.........................................................................102
List of Tables
13-1 MC Order Numbers..............................................................118
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA List of Tables 13
List of Tables
General Release Specification MC68HC05RC16 — Rev. 3.0
14 List of Tables MOTOROLA
General Release Specification — MC68HC05RC16
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.1 V
1.5.2
1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.4
1.5.5
1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.7 PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.8 PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.9 PC0–PC3 (PC4–PC7). . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DD
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .23
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 15
General Description
1.2 Introduction
The MC68HC05RC16 is a low-cost addition to the M68HC05 Family of
microcontrollers (MCUs) and is suitable for remote control applications.
This device contains the HC05 central processing unit (CPU) core,
including the 14-stage core timer with real-time interrupt (RTI) and
computer operating properly (COP) watchdog systems. On-chip
peripherals include a carrier modulator transmitter. The 16-kbyte
memory map has 15,936 bytes of user ROM and 352 bytes of RAM.
There are 20 input/output (I/O) lines (eight having keyscan
pullups/interrupts) and a low-power reset pin. This device is available in
28-pin small outline integrated circuit (SOIC), 28-pin dual in-line (DIP),
and 44-pin plastic leaded chip carrier (PLCC) packages. Four additional
I/O lines are available for bond out on the higher pin count package.
1.3 Features
Features for the MC68HC05RC16 include:
• Low Cost
• HC05 Core
• 28-Pin Plastic Dual In-Line (PDIP), Small Outline Integrated
Circuit (SOIC), or Plastic Leaded Chip Carrier (PLCC) Packages
• On-Chip Oscillator with Crystal/Ceramic Resonator
• 4-MHz Maximum Oscillator Frequency at 5 V and 2.2 V Supply
• Fully Static Operation
• 15,936 Bytes of User ROM
• 64 Bytes of Burn-In ROM
• 352 Bytes of On-Chip RAM
• 14-Stage Core Timer with Real-Time Interrupt (RTI) and
Computer Operating Properly (COP) Watchdog Circuits
• Carrier Modulator Transmitter Supporting Baseband, Pulse
Length Modulator (PLM), and Frequency Shift Keying (FSK)
Protocols
General Release Specification MC68HC05RC16 — Rev. 3.0
16 General Description MOTOROLA
General Description
Features
• Low-Power Reset Pin
• 20 Bidirectional I/O Lines (Four Additional I/O Lines Available for
Bond Out in 44-Lead PLCC Package)
• Mask Programmable Pullups and Interrupts on Eight Port Pins
(PB0–PB7)
• High-Current Infrared (IR) Drive Pin
• High-Current Port Pin (PC0)
• Power-Saving Stop and Wait Modes
• Mask Selectable Options:
– COP Watchdog Timer
– STOP Instruction Disable
– Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger
NOTE:
– Port B Pullups for Keyscan
• Illegal Address Reset
• ROM Security Feature
A line over a signal name indicates an active low signal. For example,
RESET is active low.
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 17
General Description
OSC2
OSC1
V
DD
V
SS
RESET
LPRST
IRQ
IRQEN
OSCILLATOR
COP
SYSTEM
CONTROL
CPU REGISTERS
0
0
CONDITION CODE REGISTER
CPU
0
SYSTEM
0
÷ 2
RTI
M68HC05 CPU
0
0
0
1
PROGRAM COUNTER
1
INTERNAL
PROCESSOR
CLOCK
CORE TIMER
SYSTEM
ALU
ACCUMULATOR
INDEX REGISTER
1
STACK POINTER
I
H
1
1
CARRIER
MODULATOR
IRQEN
Z
N
C
TRANSMITTER
PORT C
DATA DIRECTION REGISTER
PORT A
DATA DIRECTION REGISTER
IRO
PC0
PC1
PC2
PC3
PC4*
PC5*
PC6*
PC7*
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
SRAM — 352 BYTES
ROM — 15,936 BYTES
BURN-IN ROM — 64 BYTES
* Marked pins are available only 44-lead PLCC package.
PORT B
KEYSCAN PULLUPS
DATA DIRECTION REGISTER
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Figure 1-1. MC68HC05RC16 Block Diagram
General Release Specification MC68HC05RC16 — Rev. 3.0
18 General Description MOTOROLA
1.4 Mask Options
General Description
Mask Options
There are 11 total mask options on the MC68HC05RC16 including:
• Eight port B pullups
• IRQ sensitivity
• COP enable/disable
• STOP enable/disable
These are nonprogrammable options in that they are selected at the time
of code submission (when masks are made). These options are as
follows:
PB7PU — Port B7 Pullup/Interrupt
This bit enables or disables the pullup/interrupt on port B, bit 7.
1 = Enables the pullup/interrupt
0 = Disables the pullup/interrupt
PB6PU — Port B6 Pullup/Interrupt
This option enables or disables the pullup/interrupt on port B, bit 6.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
PB5PU — Port B5 Pullup/Interrupt
This option enables or disables the pullup/interrupt on port B, bit 5.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
PB4PU — Port B4 Pullup/Interrupt
This option enables or disables the pullup/interrupt on port B, bit 4.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
PB3PU — Port B3 Pullup/Interrupt
This option enables or disables the pullup/interrupt on port B, bit 3.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 19
General Description
PB2PU — Port B2 Pullup/Interrupt
PB1PU — Port B1 Pullup/Interrupt
PB0PU — Port B0 Pullup/Interrupt
COPEN — COP Enable
This option enables or disables the pullup/interrupt on port B, bit 2.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
This option enables or disables the pullup/interrupt on port B, bit 1.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
This option enables or disables the pullup/interrupt on port B, bit 0.
1 = Enables pullup/interrupt
0 = Disables pullup/interrupt
NOTE:
When the COP option is selected (COPEN = 1), the COP watchdog
timer is enabled.
When the COP option is deselected (COPEN = 0), the COP watchdog
timer is disabled.
STOPEN — STOP Instruction Enable
When the STOP option is selected (STOPEN = 1), the STOP
instruction is enabled.
When the STOP option is deselected (STOPEN = 0), the STOP
instruction is equivalent to a WAIT instruction.
IRQ — IRQ sensitivity
When the IRQ option is selected (IRQ = 1), edge- and level-sensitive
IRQ is enabled.
When the IRQ option is deselected (IRQ = 0), edge-only sensitive IRQ
is enabled.
The port B keyscan interrupt sensitivity will match that of the IRQ
sensitivity. (See 4.7 External Interrupt (IRQ/Port B Keyscan) for more
information.)
General Release Specification MC68HC05RC16 — Rev. 3.0
20 General Description MOTOROLA
1.5 Signal Description
The MC68HC05RC16 is available in
1. 28-pin dual-in-line package (DIP) see Figure 1-2
2. 28-pin small outline integrated circuit (SOIC) package
3. 44-pin plastic leaded chip carrier (PLCC) package seeFigure 1-4
The signals are described in the following subsections.
see Figure 1-3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
General Description
Signal Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
OSC1
27
OSC2
26
V
DD
25
IRQ
RESET
24
23
IRO
22
V
SS
21
LPRST
PC3
20
PC2
19
18
PC1
PC0
17
PA7
16
PA6
15
Figure 1-2. 28-Pin DIP Pinout
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 21
General Description
PB0 OSC1
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 1-3. 28-Pin SOIC Pinout
NC
PB0
2
22
OSC1
1
44
23
24
NC
PB4
PB5
PB6
PB7
NC
PC6
PC7
PA0
PA1
NC
NC
PB3
PB2
PB1
6
5
4
3
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OSC2
43
25
OSC2
V
DD
IRQ
RESET
IRO
V
SS
LPRST
PC3
PC2
PC1
PC0
PA7
PA6
VDDIRQ
42
41
26
27
NC
40
28
NC
39
RESET
38
IRO
37
V
36
SS
LPRST
35
NC
34
PC5
33
PC4
32
PC3
31
PC2
30
NC
29
NC
PA2
PA3
PA4
NOTE: NC = No Connect
All no connects should be tied to an appropriate logic
level (either VDD or VSS).
PA5NCPA6
PA7
PC0
PC1
NC
Figure 1-4. 44-Pin PLCC Pinout
General Release Specification MC68HC05RC16 — Rev. 3.0
22 General Description MOTOROLA
General Description
Signal Description
1.5.1 VDDand V
1.5.2
IRQ (Maskable Interrupt Request)
SS
Power is supplied to the microcontroller’s digital circuits using these two
pins. V
is the positive supply and VSS is ground.
DD
In addition to suppling the EPROM with the required programming
voltage, this pin has a mask option as specified by the user that provides
one of two different choices of interrupt triggering sensitivity. The options
are:
1. Negative edge-sensitive triggering only
2. Both negative edge-sensitive and level-sensitive triggering.
The MCU completes the current instruction before it responds to the
interrupt request. When
IRQ goes low for at least one t
(see 11.8
ILIH
Control Timing (5.0 Vdc and 2.2 Vdc)), a logic 1 is latched internally to
signify that an interrupt has been requested. When the MCU completes
its current instruction, the interrupt latch is tested. If the interrupt latch
contains a logic 1 and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU then begins the interrupt sequence.
If the option is selected to include level-sensitive triggering, the
requires an external resistor to V
IRQ pin contains an internal Schmitt trigger as part of its input to
The
for wired-OR operation.
DD
IRQ input
improve noise immunity.
Refer to Section 4. Interrupts for more detail.
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 23
General Description
1.5.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal, a ceramic resonator, or an external signal connects to these pins
to provide a system clock. The oscillator frequency is two times the
internal bus rate.
Figure 1-5 shows the recommended circuit when using a crystal. The
crystal and components should be mounted as close as possible to the
input pins to minimize output distortion and startup stabilization time.
A ceramic resonator may be used in place of the crystal in cost-sensitive
applications. Figure 1-5 (a) shows the recommended circuit for using a
ceramic resonator. The manufacturer of the particular ceramic resonator
being considered should be consulted for specific information.
An external clock should be applied to the OSC1 input with the OSC2 pin
not connected (see Figure 1-5 (b)). This setup can be used if the user
does not want to run the CPU with a crystal.
MCUMCU
OSC1 OSC2OSC1 OSC2
10 MΩ
30 pF
(a) Crystal/Ceramic Resonator (b) External Clock Source
Oscillator Connections Connections
30 pF
UNCONNECTED
<
EXTERNAL CLOCK
Figure 1-5. Oscillator Connections
General Release Specification MC68HC05RC16 — Rev. 3.0
24 General Description MOTOROLA
1.5.4 RESET
1.5.5 LPRST
1.5.6 IRO
General Description
Signal Description
This active-low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity. See Section 5. Resets.
LPRST pin is an active-low pin and is used to put the MCU into
The
low-power reset mode. In low-power reset mode the MCU is held in reset
with all processor clocks halted. See Section 5. Resets.
The IRO pin is the high-current source and sink output of the carrier
modulator transmitter subsystem which is suitable for driving infrared
(IR) LED biasing logic. See Section 9. Carrier Modulator Transmitter
(CMT).
1.5.7 PA0–PA7
1.5.8 PB0–PB7
These eight I/O lines comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset. For detailed information on I/O programming, see2.4
Input/Output Programming.
These eight I/O lines comprise port B. The state of any pin is software
programmable and all port B lines are configured as inputs during
power-on or reset. Each port B I/O line has a mask optionable
pullup/interrupt for keyscan. For detailed information on I/O
programming, see 2.4 Input/Output Programming.
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA General Description 25
General Description
1.5.9 PC0–PC3 (PC4–PC7)
These eight I/O lines comprise port C. PC0 is a high-current pin.
PC4–PC7 are available only in the 44-lead PLCC package. The state of
any pin is software programmable and all port C lines are configured as
input during power-on or reset. For detailed information on I/O
programming, see 2.4 Input/Output Programming.
NOTE:
NOTE:
Only four bits of port C are bonded out in 28-pin packages for the
MC68HC05RC16, although port C is truly an 8-bit port. Since pins
PC4–PC7 are unbonded, software should include the code to set their
respective data direction register locations to outputs to avoid floating
inputs.
Any unused inputs, I/O ports, and no connects should be tied to an
appropriate logic level (either V
or VSS). Although the I/O ports of the
DD
do not require termination, termination is recommended to reduce the
possibility of static damage.
General Release Specification MC68HC05RC16 — Rev. 3.0
26 General Description MOTOROLA
General Release Specification — MC68HC05RC16
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.2 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.2 Introduction
Section 2. Memory
2.3 Memory Map
This section describes the organization of the on-chip memory.
The MC68HC05RC16 has a 16-Kbyte memory map consisting of user
ROM, RAM, burn-in ROM, and input/output (I/O).
Figure 2-1 shows the MC68HC05RC16 memory map in user mode.
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Memory 27
Memory
$0000
$001F
$0020
$00BF
$00C0
$00FF
$0100
$017F
$0180
$3FAF
$3FB0
$3FEF
$3FF0
$3FFF
I/O
32 BYTES
RAM
160 BYTES
STACK
64 BYTES
RAM
128 BYTES
USER ROM
15,920 BYTES
BURN-IN ROM
& VECTORS
64 BYTES
USER VECTORS
16 BYTES
0000
0031
0032
0191
0192
0255
0256
0383
0384
16303
16304
16367
16368
16383
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
RESERVED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
RESERVED
CORE TIMER CONTROL & STATUS REG.
CORE TIMER COUNTER REGISTER
RESERVED
. . . . . . .
RESERVED
IR TIMER CHR1
IR TIMER CLR1
IR TIMER CHR2
IR TIMER CLR2
IR TIMER MCSR
IR TIMER MDR1
IR TIMER MDR2
IR TIMER MDR3
RESERVED
RESERVED
RESERVED
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
. . . . . . .
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$1E
$1F
UNUSED
$3FF0
... ..
UNUSED
CORE TIMER VECTOR (HIGH BYTE)
CORE TIMER VECTOR (LOW BYTE)
IR TIMER VECTOR (HIGH BYTE)
IR TIMER VECTOR (LOW BYTE)
IRQ/PTB KEYSCAN PULLUPS
VECTOR (HIGH BYTE)
IRQ/PTB KEYSCAN PULLUPS
VECTOR (LOW BYTE)
SWI VECTOR (HIGH BYTE)
SWI VECTOR (LOW BYTE)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$3FF5
$3FF6
$3FF7
$3FF8
$3FF9
$3FFA
$3FFB
$3FFC
$3FFD
$3FFE
$3FFF
Figure 2-1. MC68HC05RC16 Memory Map
General Release Specification MC68HC05RC16 — Rev. 3.0
28 Memory MOTOROLA
Memory
Memory Map
Addr. Register Bit 7 6 5 4 3 2 1 Bit 0
$0000 Port A Data Register
$0001 Port B Data Register
$0002 Port C Data Register
$0003 Reserved R RRRRRRR
$0004 Port A Data Direction Register
$0005 Port B Data Direction Register
$0006 Port C Data Direction Register
$0007 Reserved R RRRRRRR
$0008 Timer Control and Status Reg. CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0
$0009 Timer Counter Register
$000A Reserved R RRRRRRR
$000B Reserved R RRRRRRR
$000C Reserved R RRRRRRR
$000D Reserved R RRRRRRR
$000E Reserved R RRRRRRR
$000F Reserved R RRRRRRR
$0010 IR Timer CHR1 IROLN 0 PH5 PH4 PH3 PH2 PH1 PH0
$0011 IR Timer CLR1 IROLP 0 PL5 PL4 PL3 PL2 PL1 PL0
$0012 IR Timer CHR2 0 0 SH5 SH4 SH3 SH2 SH1 SH0
$0013 IR Timer CLR2 0 0 SL5 SL4 SL3 SL2 SL1 SL0
$0014 IR Timer MCSR EOC 0 EIMSK EXMRK BASE MODE EOCIE MCGEN
$0015 IR Timer MDR1 MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8
$0016 IR Timer MDR2 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0
$0017 IR Timer MDR3 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
$0018 Reserved R RRRRRRR
$0019 Reserved R RRRRRRR
R= Reserved
Figure 2-2. I/O Registers
MC68HC05RC16 — Rev. 3.0 General Release Specification
MOTOROLA Memory 29
Memory
Addr. Register Bit 7 6 5 4 3 2 1 Bit 0
$001A Reserved R RRRRRRR
$001B Reserved R RRRRRRR
$001C Reserved R RRRRRRR
$001D Reserved R RRRRRRR
$001E Reserved R RRRRRRR
$001F Reserved R RRRRRRR
R= Reserved
Figure 2-2. I/O Registers (Continued)
2.3.1 ROM
2.3.2 ROM Security
The user ROM consists of 15,920 bytes of ROM located from $0180 to
$3FAF and 16 bytes of user vectors located from $3FF0 to $3FFF.
The burn-in ROM is located from $3FB0 to $3FEF.
Ten of the user vectors, $3FF6–$3FFF, are dedicated to reset and
interrupt vectors. The six remaining locations — $3FF0, $3FF1, $3FF2,
$3FF3, $3FF4, and $3FF5 — are general-purpose user ROM locations.
Security has been incorporated into the MC68HC05RC16 to prevent
external viewing of the ROM contents. This feature ensures that
customer-developed software remains proprietary.
1
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
General Release Specification MC68HC05RC16 — Rev. 3.0
30 Memory MOTOROLA
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