MOTOROLA MC68306 User Guide

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MC68306

Integrated EC000 Processor

User’s Manual

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© MOTOROLA, 1993

PREFACE

The complete documentation package for the MC68306 consists of the MC68306UM/AD,

MC68306 EC000 Integrated Processor User’s Manual
Programmer’s Reference Manual,
Processor Product Brief

.

and the MC68306P/D,

, M68000PM/AD,

MC68306 EC000 Integrated

MC68000 Family

MC68306 EC000 Integrated Processor User’s Manual

The
capabilities, registers, and operation of the MC68306; the

Reference Manual
Integrated Processor Product Brief

capabilities.
This user’s manual is organized as follows:

Section 1 Introduction
Section 2 Signal Descriptions
Section 3 68000 Bus Operation Description
Section 4 EC000 Core Processor
Section 5 System Operation
Section 6 Serial Module
Section 7 IEEE 1149.1 Test Access Port
Section 8 Electrical Specifications
Section 9 Ordering Information and Mechanical Data

68K FAX-IT –

provides instruction details for the MC68306; and the

provides a brief description of the MC68306

Documentation Comments

describes the programming,

MC68000 Family Programmer’s

MC68306 EC000

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TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 MC68EC000 Core processor.................................................................................. 1-2

1.2 On-Chip Peripherals ............................................................................................... 1-3

1.2.1 Serial Module....................................................................................................... 1-3

1.2.2 DRAM Controller.................................................................................................. 1-4

1.2.3 Chip Selects......................................................................................................... 1-4

1.2.4 Parallel Ports........................................................................................................ 1-4

1.2.5 Interrupt Controller............................................................................................... 1-4

1.2.6 Clock.................................................................................................................... 1-5

1.2.7 Bus Timeout Monitor............................................................................................ 1-5

1.2.8 Mode Controller ................................................................................................... 1-5

1.2.9 IEEE 1149.1 Test................................................................................................. 1-5

Section 2

Signal Descriptions

2.1 Bus Signals............................................................................................................. 2-5

2.1.1 Address Bus (A23–A1) ........................................................................................ 2-5

2.1.2 Address Strobe (AS)............................................................................................ 2-5

2.1.3 Bus Error (BERR ) ................................................................................................ 2-5

2.1.4 Bus Request (BR) ................................................................................................ 2-5

2.1.5 Bus Grant (BG ) .................................................................................................... 2-6

2.1.6 Bus Grant Acknowledge (BGACK) ....................................................................... 2-6

2.1.7 Data Bus (D15–D0) ............................................................................................. 2-6

2.1.8 Data Transfer Acknowledge (DTACK) ................................................................. 2-6

2.1.9 DRAM Multiplexed Address Bus (DRAMA14 –DRAMA0) ..................................... 2-6

2.1.10 Processor Function Codes (FC2–FC0).............................................................. 2-6

2.1.11 Halt (HALT) ........................................................................................................ 2-7

2.1.12 Read/Write (R/W)............................................................................................... 2-7

2.1.13 Upper And Lower Data Strobes (UDS , LDS ) ..................................................... 2-7

2.1.14 Upper Byte Write (UW ) ...................................................................................... 2-8

2.1.15 Lower Byte Write (LW)....................................................................................... 2-8

2.1.16 Output Enable (OE) ........................................................................................... 2-8

2.1.17 Reset (RESET ) .................................................................................................. 2-8

2.2 Chip Select Signals................................................................................................. 2-9

MOTOROLA MC68306 USER'S MANUAL v

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

2.3 DRAM Controller Signals........................................................................................ 2-9

2.3.1 Column Address Strobe (CAS1–CAS0 )............................................................... 2-9

2.3.2 Row Address Strobe (RAS1–RAS0) .................................................................... 2-9

2.3.3 DRAM Write Signal (DRAMW)............................................................................. 2-9

2.4 Interrupt Control and Parallel Port Signals ............................................................. 2-9

2.4.1 Interrupt Request (IRQ7–IRQ1)........................................................................... 2-9

2.4.2 Interrupt Acknowledge (IACK7–IACK1)............................................................... 2-9

2.4.3 Port A Signals (PA7–PA0)................................................................................... 2-9

2.4.4 Port B (PB7–PB0)................................................................................................ 2-9

2.5 Clock and Mode Control Signals ............................................................................ 2-10

2.5.1 Crystal Oscillator (EXTAL, XTAL)........................................................................ 2-10

2.5.2 Clock Out (CLKOUT)........................................................................................... 2-10

2.5.3 Address Mode (AMODE)..................................................................................... 2-10

2.6 Serial Module Signals............................................................................................. 2-10

2.6.1 Channel A Receiver Serial-Data Input (RxDA).................................................... 2-10

2.6.2 Channel A Transmitter Serial-Data Output (TxDA) ............................................. 2-10

2.6.3 Channel B Receiver Serial-Data Input (RxDB).................................................... 2-10

2.6.4 Channel B Transmitter Serial-Data Output (TxDB) ............................................. 2-10

2.6.5 CTSA................................................................................................................... 2-11

2.6.6 RTSA................................................................................................................... 2-11

2.6.7 CTSB................................................................................................................... 2-11

2.6.8 RTSB................................................................................................................... 2-11

2.6.9 Crystal Oscillator (X1, X2) ................................................................................... 2-11

2.6.10 IP2 ..................................................................................................................... 2-11

2.6.11 OP3 ................................................................................................................... 2-11

2.7 JTAG Port Test Signals .......................................................................................... 2-11

2.7.1 Test Clock (TCK) ................................................................................................. 2-12

2.7.2 Test Mode Select (TMS)...................................................................................... 2-12

2.7.3 Test Data In (TDI)................................................................................................ 2-12

2.7.4 Test Data Out (TDO) ........................................................................................... 2-12

2.7.5 Test Reset (TRST) .............................................................................................. 2-12

Section 3

68000 Bus Operation Description

3.1 Data Transfer Operations ....................................................................................... 3-1

3.1.1 Read Cycle.......................................................................................................... 3-1

3.1.2 Write Cycle .......................................................................................................... 3-4

3.1.3 Read-Modify-Write Cycle..................................................................................... 3-7

3.1.4 CPU Space Cycle................................................................................................ 3-11

vi MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

3.2 Bus Arbitration ........................................................................................................ 3-12

3.2.1 Requesting the Bus ............................................................................................. 3-15

3.2.2 Receiving the Bus Grant...................................................................................... 3-16

3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)............................ 3-16

3.3 Bus Arbitration Control............................................................................................ 3-16

3.4 Bus Error and Halt Operation ................................................................................. 3-24

3.4.1 Bus Error Operation............................................................................................. 3-24

3.4.2 Retrying the Bus Cycle ........................................................................................ 3-25

3.4.3 Halt Operation...................................................................................................... 3-26

3.4.4 Double Bus Fault ................................................................................................. 3-27

3.5 Reset Operation...................................................................................................... 3-28

3.6 The Relationship of DTACK, BERR , and HALT ...................................................... 3-28

3.7 Asynchronous Operation ........................................................................................ 3-30

3.8 Synchronous Operation.......................................................................................... 3-33

Section 4

EC000 Core Processor

4.1 Features.................................................................................................................. 4-1

4.2 Processing States................................................................................................... 4-1

4.3 Programming Model ............................................................................................... 4-2

4.3.1 Data Format Summary......................................................................................... 4-3

4.3.2 Addressing Capabilities Summary....................................................................... 4-4

4.3.3 Notation Conventions .......................................................................................... 4-5

4.4 EC000 Core Instruction Set Overview .................................................................... 4-7

4.5 Exception Processing ............................................................................................. 4-12

4.5.1 Exception Vectors................................................................................................ 4-14

4.6 Processing of Specific Exceptions.......................................................................... 4-16

4.6.1 Reset Exception................................................................................................... 4-17

4.6.2 Interrupt Exceptions............................................................................................. 4-17

4.6.3 Uninitialized Interrupt Exception .......................................................................... 4-18

4.6.4 Spurious Interrupt Exception................................................................................ 4-18

4.6.5 Instruction Traps .................................................................................................. 4-18

4.6.6 Illegal and Unimplemented Instructions............................................................... 4-18

4.6.7 Privilege Violations............................................................................................... 4-19

4.6.8 Tracing................................................................................................................. 4-19

4.6.9 Bus Error.............................................................................................................. 4-20

4.6.10 Address Error..................................................................................................... 4-21

4.6.11 Multiple Exceptions............................................................................................ 4-21

MOTOROLA MC68306 USER'S MANUAL vii

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 5

System Operation

5.1 MC68306 Address Space....................................................................................... 5-1

5.2 Register Description ............................................................................................... 5-3

5.2.1 System Register .................................................................................................. 5-3

5.2.2 Timer Vector Register.......................................................................................... 5-4

5.2.3 Bus Timeout Period Register............................................................................... 5-4

5.2.4 Interrupt Registers ............................................................................................... 5-5

5.2.4.1 Interrupt Control Register ................................................................................. 5-5

5.2.4.2 Interrupt Status Register................................................................................... 5-6

5.2.5 I/O Port Registers ................................................................................................ 5-6

5.2.5.1 Port Pins Register............................................................................................. 5-7

5.2.5.2 Port Direction Register ..................................................................................... 5-7

5.2.5.3 Port Data Register ............................................................................................ 5-8

5.2.6 Chip Selects......................................................................................................... 5-8

5.2.6.1 Chip Select Configuration Registers (High Half) .............................................. 5-9

5.2.6.2 Chip Select Configuration Registers (Low Half) ............................................... 5-10

5.2.7 DRAM Control Registers ..................................................................................... 5-12

5.2.7.1 DRAM Refresh Register ................................................................................... 5-13

5.2.7.2 DRAM Bank Configuration Register (High Half)............................................... 5-14

5.2.7.3 DRAM Bank Configuration Register (Low Half)................................................ 5-14

5.2.8 Automatic DTACK Generation............................................................................. 5-16

5.3 Crystal Oscillator .................................................................................................... 5-16

Section 6

Serial Module

6.1 Module Overview.................................................................................................... 6-2

6.1.1 Serial Communication Channels A and B............................................................ 6-3

6.1.2 Baud Rate Generator Logic................................................................................. 6-3

6.1.3 Timer/Counter...................................................................................................... 6-3

6.1.4 Interrupt Control Logic ......................................................................................... 6-3

6.1.5 Comparison of Serial Module to MC68681.......................................................... 6-4

6.2 Serial Module Signal Definitions............................................................................. 6-4

6.2.3 Channel A Transmitter Serial Data Output (TxDA).............................................. 6-4

6.2.4 Channel A Receiver Serial Data Input (RxDA).................................................... 6-5

6.2.5 Channel B Transmitter Serial Data Output (TxDB).............................................. 6-5

6.2.6 Channel B Receiver Serial Data Input (RxDB).................................................... 6-6

6.2.7 Channel A Request-To-Send (RTSA/OP0) ......................................................... 6-6

6.2.7.1 RTSA................................................................................................................ 6-6

6.2.7.2 OP0 .................................................................................................................. 6-6

6.2.8 Channel B Request-To-Send (RTSB/OP1) ......................................................... 6-6

viii MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

6.2.8.1 RTSB ................................................................................................................ 6-6

6.2.8.2 OP1................................................................................................................... 6-6

6.2.9 Channel A Clear-To-Send (CTSA/IP0) ................................................................ 6-6

6.2.9.1 CTSA ................................................................................................................ 6-6

6.2.9.2 IP0 .................................................................................................................... 6-6

6.2.10 Channel B Clear-To-Send (CTSB/IP1) .............................................................. 6-6

6.2.10.1 CTSB .............................................................................................................. 6-6

6.2.10.2 IP1 .................................................................................................................. 6-6

6.3 Operation ................................................................................................................ 6-7

6.3.1 Baud Rate Generator........................................................................................... 6-7

6.3.2 Transmitter and Receiver Operating Modes........................................................ 6-7

6.3.2.1 Transmitter........................................................................................................ 6-9

6.3.2.2 Receiver............................................................................................................ 6-10

6.3.2.3 FIFO Stack........................................................................................................ 6-11

6.3.3 Looping Modes .................................................................................................... 6-13

6.3.3.1 Automatic Echo Mode....................................................................................... 6-13

6.3.3.2 Local Loopback Mode....................................................................................... 6-13

6.3.3.3 Remote Loopback Mode................................................................................... 6-13

6.3.4 Multidrop Mode .................................................................................................... 6-14

6.3.5 Counter/Timer...................................................................................................... 6-16

6.3.5.1 Counter Mode................................................................................................... 6-16

6.3.5.2 Timer Mode....................................................................................................... 6-16

6.3.6 Bus Operation...................................................................................................... 6-17

6.3.6.1 Read Cycles ..................................................................................................... 6-17

6.3.6.2 Write Cycles...................................................................................................... 6-17

6.3.6.3 Interrupt Acknowledge Cycles .......................................................................... 6-17

6.4 Register Description and Programming.................................................................. 6-17

6.4.1 Register Description ............................................................................................ 6-17

6.4.1.1 Mode Register 1 (DUMR1) ............................................................................... 6-18

6.4.1.2 Mode Register 2 (DUMR2) ............................................................................... 6-20

6.4.1.3 Status Register (DUSR).................................................................................... 6-22

6.4.1.4 Clock-Select Register (DUCSR) ....................................................................... 6-24

6.4.1.5 Command Register (DUCR) ............................................................................. 6-26

6.4.1.6 Receiver Buffer (DURB) ................................................................................... 6-29

6.4.1.7 Transmitter Buffer (DUTB) ................................................................................ 6-29

6.4.1.8 Input Port Change Register (DUIPCR) ............................................................. 6-29

6.4.1.9 Auxiliary Control Register (DUACR) ................................................................ 6-30

6.4.1.10 Interrupt Status Register (DUISR) .................................................................. 6-31

6.4.1.11 Interrupt MASK Register (DUIMR).................................................................. 6-33

6.4.1.12 Count Register Current MSB of Counter (DUCUR)........................................ 6-33

6.4.1.13 Count Register Current LSB of Counter (DUCLR) ......................................... 6-33

6.4.1.14 Counter/Timer Upper Preload Register (CTUR)............................................. 6-34

MOTOROLA MC68306 USER'S MANUAL ix

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

6.4.1.15 Counter/Timer Lower Pimer Register (CTLR) ................................................ 6-34

6.4.1.16 Interrupt Vector Register (DUIVR).................................................................. 6-34

6.4.1.17 Input Port Register.......................................................................................... 6-34

6.4.1.18 Output Port Control Register (DUOPCR) ....................................................... 6-35

6.4.1.19 Output Port Data Register (DUOP) ................................................................ 6-35

6.4.1.20 Start Counter Command Register .................................................................. 6-36

6.4.1.21 Stop Counter Command Register .................................................................. 6-36

6.4.2 Programming....................................................................................................... 6-36

6.4.2.1 Serial Module Initialization................................................................................ 6-36

6.4.2.2 I/O Driver Example ........................................................................................... 6-37

6.4.2.3 Interrupt Handling ............................................................................................. 6-37

6.5 Serial Module Initialization Sequence..................................................................... 6-43

Section 7

IEEE 1149.1 Test Access Port

7.1 Overview................................................................................................................. 7-1

7.2 TAP Controller ........................................................................................................ 7-3

7.3 Boundary Scan Register......................................................................................... 7-3

7.4 Instruction Register................................................................................................. 7-9

7.4.1 EXTEST (000) ..................................................................................................... 7-10

7.4.2 SAMPLE/PRELOAD (110) .................................................................................. 7-10

7.4.3 BYPASS (010, 101, 111)..................................................................................... 7-11

7.4.4 CLAMP (011)...................................................................................................... 7-11

7.5 MC68306 Restrictions ............................................................................................ 7-11

7.6 Non-IEEE 1149.1 Operation................................................................................... 7-12

Section 8

Electrical Specifications

8.1 Maximum Ratings................................................................................................... 8-1

8.2 Thermal Characteristics.......................................................................................... 8-1

8.3 Power Considerations............................................................................................. 8-2

8.4 AC Electrical Specification Definitions.................................................................... 8-2

8.5 DC Electrical Specifications.................................................................................... 8-4

8.6 AC Electrical Specifications—Clock Timing............................................................ 8-4

8.7 AC Electrical Specifications—Read and Write ....................................................... 8-5

8.8 AC Electrical Specifications—Chip Selects ............................................................ 8-9

8.9 AC Electrical Specifications—Bus Arbitration......................................................... 8-10

8.10 Bus Operation—DRAM Accesses AC Timing Specifications............................... 8-12

8.11Serial Module Electrical Characteristics ................................................................ 8-15

8.12 Serial Module AC Electrical Characteristics—Clock Timing................................. 8-16

8.13 AC Electrical Characteristics—Port Timing .......................................................... 8-16

8.14 AC Electrical Characteristics—Interrupt Reset..................................................... 8-16

x MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

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Number Title Number

8.14 AC Electrical Characteristics—Interrupt Reset ..................................................... 8-16

8.15 AC Electrical Characteristics—Transmitter Timing ............................................... 8-17

8.16 AC Electrical Characteristics—Receiver Timing................................................... 8-18

8.17 IEEE 1149.1 Electrical Characteristics ................................................................. 8-19

Section 9

Ordering Information and Mechanical Data

9.1 Standard Ordering Information ............................................................................... 9-1

9.2 Pin Assignments ..................................................................................................... 9-2

MOTOROLA MC68306 USER'S MANUAL xi

LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

Figure 1-1. MC68306 Simplified Block Diagram....................................................... 1-1

Figure 2-1. MC68306 Detailed Block Diagram......................................................... 2-2

Figure 3-1. Word Read Cycle Flowchart .................................................................. 3-2

Figure 3-2. Byte Read Cycle Flowchart.................................................................... 3-2

Figure 3-3. Read and Write Cycle Timing Diagram .................................................. 3-3

Figure 3-4. Word and Byte Read Cycle Timing Diagram ......................................... 3-3

Figure 3-5. Word Write Cycle Flowchart................................................................... 3-5

Figure 3-6. Byte Write Cycle Flowchart .................................................................... 3-6

Figure 3-7. Word and Byte Write Cycle Timing Diagram.......................................... 3-6

Figure 3-8. Read-Modify-Write Cycle Flowchart....................................................... 3-8

Figure 3-9. Read-Modify-Write Cycle Timing Diagram............................................. 3-9

Figure 3-10. Interrupt Acknowledge Cycle ............................................................... 3-11

Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram ..................................... 3-12

Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart ........................................ 3-13

Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart........................................... 3-14

Figure 3-14. Three-Wire Bus Arbitration Timing Diagram ........................................ 3-15

Figure 3-15. Two-Wire Bus Arbitration Timing Diagram........................................... 3-15

Figure 3-16. External Asynchronous Signal Synchronization................................... 3-17

Figure 3-17. Bus Arbitration Unit State Diagrams..................................................... 3-19

Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active.......... 3-20

Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive ................. 3-21

Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case ............... 3-22

Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active ............ 3-23

Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive.................... 3-24

Figure 3-23. Two-Wire Bus Arbitration Timing Diagram—Special Case .................. 3-25

Figure 3-24. Bus Error Timing Diagram.................................................................... 3-26

Figure 3-25. Retry Bus Cycle Timing Diagram ......................................................... 3-27

Figure 3-26. Halt Operation Timing Diagram............................................................ 3-28

Figure 3-27. Reset Operation Timing Diagram......................................................... 3-29

Figure 3-28 Fully Asynchronous Read Cycle ........................................................... 3-32

Figure 3-29. Fully Asynchronous Write Cycle........................................................... 3-32

Figure 3-30. Pseudo-Asynchronous Read Cycle ..................................................... 3-33

Figure 3-31. Pseudo-Asynchronous Write Cycle...................................................... 3-34

Figure 3-32. Synchronous Read Cycle..................................................................... 3-36

Figure 3-33. Synchronous Write Cycle..................................................................... 3-37

xii MC68306 USER'S MANUAL MOTOROLA

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

Figure 4-1. Programmer's Model .............................................................................. 4-2

Figure 4-2. Status Register....................................................................................... 4-3

Figure 4-3. General Exception Processing Flowchart .............................................. 4-13

Figure 4-4. General Form of Exception Stack Frame............................................... 4-14

Figure 4-5. Exception Vector Format........................................................................ 4-15

Figure 4-6. Address Translated from 8-Bit Vector Number ...................................... 4-15

Figure 4-7. Supervisor Stack Order for Bus or Address Error Exception ................. 4-21

Figure 5-1. Chip Select Expansion ........................................................................... 5-12

Figure 5-2. Oscillator Circuit Diagram....................................................................... 5-17

Figure 6-1. Simplified Block Diagram ....................................................................... 6-1

Figure 6-2. External and Internal Interface Signals .................................................. 6-5

Figure 6-3. Baud Rate Generator Block Diagram..................................................... 6-7

Figure 6-4. Transmitter and Receiver Functional Diagram....................................... 6-8

Figure 6-5. Transmitter Timing Diagram ................................................................... 6-9

Figure 6-6. Receiver Timing Diagram....................................................................... 6-11

Figure 6-7. Looping Modes Functional Diagram....................................................... 6-14

Figure 6-8. Multidrop Mode Timing Diagram ............................................................ 6-15

Figure 6-9. Serial Module Programming Model........................................................ 6-18

Figure 6-10. Serial Module Programming Flowchart ................................................ 6-38

Figure 7-1. Test Access Port Block Diagram............................................................ 7-2

Figure 7-2. TAP Controller State Machine................................................................ 7-3

Figure 7-3. Output Cell (O.Cell) ................................................................................ 7-7

Figure 7-4. Input Cell (I.Cell)..................................................................................... 7-7

Figure 7-5. Output Control Cell (En.Cell).................................................................. 7-8

Figure 7-6. Bidirectional Cell (IO.Cell) ...................................................................... 7-8

Figure 7-7. Bidirectional Cell (IOx0.Cell)................................................................... 7-9

Figure 7-8. General Arrangement for Bidirectional Pins ........................................... 7-9

Figure 7-9. Bypass Register ..................................................................................... 7-11

Figure 8-1. Drive Levels and Test Points for AC Specifications ............................... 8-3

Figure 8-2. Clock Output Timing............................................................................... 8-4

Figure 8-3. Read Cycle Timing Diagram................................................................... 8-7

Figure 8-4. Write Cycle Timing Diagram................................................................... 8-8

Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram....................... 8-9

Figure 8-6. Bus Arbitration Timing Diagram ............................................................. 8-10

Figure 8-7. Bus Arbitration Timing Diagram ............................................................. 8-11

Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh............................................. 8-13

Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh ............................................. 8-14

Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh................................................ 8-14

MOTOROLA MC68306 USER'S MANUAL xiii

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

Figure 8-11. DRAM Timing – 1-Wait, Test and Set .................................................. 8-15

Figure 8-12. Clock Timing......................................................................................... 8-16

Figure 8-13. Port Timing........................................................................................... 8-16

Figure 8-14. Interrupt Reset Timing.......................................................................... 8-17

Figure 8-15. Transmit Timing ................................................................................... 8-17

Figure 8-16. Receive Timing .................................................................................... 8-18

Figure 8-17. Test Clock Input Timing Diagram......................................................... 8-19

Figure 8-18. Boundary Scan Timing Diagram .......................................................... 8-20

Figure 8-19. Test Access Port Timing Diagram........................................................ 8-20

xiv MC68306 USER'S MANUAL MOTOROLA

LIST OF TABLES

Table Page

Number Title Number

Table 2-1. Bus Signal Summary ............................................................................... 2-3

Table 2-2. Chip Select Signal Summary................................................................... 2-3

Table 2-3. DRAM Controller Signal Summary .......................................................... 2-3

Table 2-4. Interrupt and Parallel Port Signal Summary ............................................ 2-4

Table 2-5. Clock and Mode Control Signal Summary............................................... 2-4

Table 2-6. Serial Module Signal Summary ............................................................... 2-4

Table 2-7. JTAG Signal Summary ............................................................................ 2-5

Table 2-8. Function Code Outputs............................................................................ 2-7

Table 2-9. Data Strobe Control of Data Bus ............................................................. 2-8

Table 3-1. DTACK, BERR, and HALT Assertion Results ......................................... 3-24

Table 3-2. BERR and HALT Negation Results ......................................................... 3-25

Table 4-1. Processor Data Formats.......................................................................... 4-3

Table 4-2. Effective Addressing Modes.................................................................... 4-4

Table 4-3. Notation Conventions .............................................................................. 4-5

Table 4-4. EC000 Core Instruction Set Summary .................................................... 4-8

Table 4-5. Exception Vector Assignments................................................................ 4-16

Table 4-6. Exception Grouping and Priority.............................................................. 4-22

Table 5-1. MC68306 Memory Map ........................................................................... 5-2

Table 5-2. Chip Select Match Bits ............................................................................ 5-11

Table 5-3. DRAM Address Multiplexer...................................................................... 5-13

Table 5-4. DRAM Bank Match Bits ........................................................................... 5-15

Table 6-1. PMx and PT Control Bits ......................................................................... 6-20

Table 6-2. B/Cx Control Bits ..................................................................................... 6-20

Table 6-3. CMx Control Bits...................................................................................... 6-21

Table 6-4. SBx Control Bits ...................................................................................... 6-22

Table 6-5. RCSx Control Bits.................................................................................... 6-25

Table 6-6. TCSx Control Bits .................................................................................... 6-26

Table 6-7. MISCx Control Bits .................................................................................. 6-27

Table 6-8. TCx Control Bits ...................................................................................... 6-28

Table 6-9. RCx Control Bits...................................................................................... 6-28

Table 6-10. Counter/Timer Mode and Source Select Bits ........................................ 6-30

MOTOROLA MC68306 USER'S MANUAL xv

LIST OF TABLES (Continued)

Table Page

Number Title Number

Table 7-1. Boundary Scan Control Bits .................................................................... 7-4

Table 7-2. Boundary Scan Bit Definitions................................................................. 7-5

Table 7-3. Instructions .............................................................................................. 7-10

xvi MC68306 USER'S MANUAL MOTOROLA

SECTION 1
INTRODUCTION

The MC68306 is an integrated processor containing an MC68EC000 processor and
elements common to many MC68000- and MC68EC000-based systems. Designers of
virtually any application requiring MC68000-class performance will find that the MC68306
reduces design time by providing valuable system elements integrated in one chip. The
combination of peripherals offered in the MC68306 can be found in a diverse range of
microprocessor-based systems, including embedded control and general computing.
Systems requiring serial communication and dynamic random access memory (DRAM)
can especially benefit from using the MC68306.

The MC68306's high level of functional integration results in significant reductions in
component count, power consumption, board space, and cost while yielding much higher
system reliability and shorter design time. Complete code compatibility with the MC68000
affords the designer access to a broad base of established real-time kernels, operating
systems, languages, applications, and development tools, many of which are oriented
towards embedded control. Figure 1-1 shows a simplified block diagram of the MC68306.

8

DRAM

CONTROLLER

8

CHIP

SELECTS

INTERRUPT

CONTROLLER

CLOCK

MODE

CONTROLLER

JTAG
PORT

PORT A

PORT B

8

16-BIT
TIMER

EC000
CORE

PROCESSOR

TWO-CHANNEL

SERIAL

I/O

24

16

Figure 1-1. MC68306 Simplified Block Diagram

MOTOROLA MC68306 USER'S MANUAL 1-1

The primary features of the MC68306 are as follows:

• Functional Integration on a Single Piece of Silicon

• EC000 Core—Identical to MC68EC000 Microprocessor
— Complete Code Compatibility with MC68000 and MC68EC000
— High Performance—2.4 MIPS
— Extended Internal Address Range – to 4 Gbyte

• Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)
— Baud Rate Generators
— Modem Control
— Compatible with MC68681/MC2681
— Integrated 16-Bit Timer/Counter

• DRAM Controller
— Supports up to 16 Mbytes using 4M x 1 DRAMs, 64 Mbytes using 16M x 1 DRAMs
— Provides Zero Wait State Interface to 80-ns DRAMs
— Programmable Refresh Timer Provides CAS-before-RAS Refresh

• Chip Selects
— Eight Programmable Chip Select Signals
— Provide Eight Separate 1-Mbyte Spaces or Four Separate 16-Mbyte Spaces
— Programmable Wait States

• Programmable Interrupt Controller

• Bus Timeout

• 24 Address Lines, 16 Data Lines

• 16.67 MHz, 5 Volt Operation

• 144-Pin Thin Quad Flat Pack (TQFP)or 132-Pin Plastic Quad Flat Pack (PQFP)

1.1 MC68EC000 CORE PROCESSOR

The MC68EC000 is a core implementation of the MC68000 32-bit microprocessor
architecture. The programmer can use any of the eight 32-bit data registers for fast
manipulation of data and any of the eight 32-bit address registers for indexing data in
memory. Flexible instructions support data movement, arithmetic functions, logical
operations, shifts and rotates, bit set and clear, conditional and unconditional program
branches, and overall system control.

The MC68EC000 core can operate on data types of single bits, binary-coded decimal
(BCD) digits, and 8, 16, and 32 bits. The integrated chip selects allow peripherals and
data in memory to reside anywhere in the 4-Gbyte linear address space. A supervisor
operating mode protects system-level resources from the more restricted user mode,
allowing a true virtual environment to be developed. Many addressing modes complement

1-2 MC68306 USER'S MANUAL MOTOROLA

these instructions, including predecrement and postincrement, which allow simple stack
and queue maintenance and scaled indexing for efficient table accesses. Data types and
addressing modes are supported orthogonally by all data operations and with all
appropriate addressing modes. Position-independent code is easily written.

Like all M68000 family processors, the MC68EC000 core recognizes interrupts of seven
different priority levels and allows either an automatic vector or a peripheral-supplied
vector to direct the processor to the desired service routine. Internal trap exceptions
ensure proper instruction execution with good addresses and data, allow operating system
intervention in special situations, and permit instruction tracing. Hardware signals can
either terminate or rerun bad memory accesses before instructions process data
incorrectly. The EC000 core provides 2.4 MIPS at 16.67 MHz.

1.2 ON-CHIP PERIPHERALS

To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules and
typical glue logic. The functions on the MC68306 include two serial channels, a
timer/counter, a DRAM controller, a parallel port, and system glue logic.

1.2.1 Serial Module

Most digital systems use serial I/O to communicate with host computers, operator
terminals, or remote devices. The MC68306 contains a two-channel, full-duplex UART
with an integrated timer. An on-chip baud rate generator provides standard baud rates up
the 38.4K baud to each channel's receiver and transmitter. The serial module is identical
to the MC68681/MC2681 DUART.

Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8
bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. Each channel provides
a wide variety of error detection and maskable interrupt capability. Full-duplex, autoecho
loopback, local loopback, and remote loopback modes can be selected. Multidrop
applications are also supported.

A 3.6864 MHz crystal drives the baud rate generators. Each transmit and receive channel
can be programmed for a different baud rate. Full modem support is provided with
separate request-to-send (RTS) and clear-to-send (CTS) signals for each channel.

The integrated 16-bit timer/counter can operate in a counter mode or a timer mode. The
timer/counter can function as a system stopwatch, a real-time single interrupt generator,
or a device watchdog when in counter mode. In timer mode, the timer/counter can be
used as a programmable clock source for channels A and B, a periodic interrupt
generator, or a variable duty cycle square-wave generator.

1.2.2 DRAM Controller

DRAM is used in many systems since it is the least expensive form of high-speed storage
available. However, considerable design effort is often spent designing the interface

MOTOROLA MC68306 USER'S MANUAL 1-3

between the processor and DRAM. The MC68306 contains a full DRAM controller, greatly
reducing design time and complexity.

The DRAM controller provides row address strobe ( RAS) and column address strobe
(CAS) signals for two separate banks of DRAMs. Each bank can include up to 16 devices;
up to 15 multiplexed address lines are also available. Thus, using 4M x 1 DRAMs, up to
16 Mbytes of DRAM are supported; with 16M x 1 DRAMs, up to 64 Mbytes of DRAM are
supported. A programmable refresh timer provides CAS-before-RAS refreshes at
designated intervals.

The DRAM controller has its own address registers that control the address range
selected by each RAS and CAS signal, leaving the eight integrated chip selects free for
other system peripherals. DRAM accesses are zero wait states using 80-ns DRAMs.

1.2.3 Chip Selects

The MC68306 provides up to eight programmable chip select outputs, in most cases
eliminating the need for external address decoding. All handshaking and timing signals
are provided, with up to 950-ns access times. Each chip select can access a 16 Mbyte
address space located anywhere in the 4-Gbyte address range. Internal registers allow
the base address, range, and cycle duration of each chip select to be independently
programmed. After reset, chip select (CS0) responds to all accesses until the chip selects
have been properly programmed. Four of the chip selects are multiplexed with the most
significant address bits (A23–A20). The address mode (AMODE) input determines the
functions of these outputs.

1.2.4 Parallel Ports

Two 8-bit parallel ports are provided. The port pins can be individually programmed to be
inputs or outputs. If the pins are programmed to be inputs, the value on those pins can be
read by accessing an on-board register. If the pins are programmed to be outputs, the
pins will reflect the value programmed into another on-board register. The port B pins are
multiplexed with four interrupt request and four interrupt acknowledge lines. The function
of these pins is controlled by the internal registers.

1.2.5 Interrupt Controller

Seven input signals are provided to trigger an external interrupt, one for each of the seven
priority levels supported. Each input can be programmed to be active high or active low.
Seven separate outputs indicate the priority level of the interrupt being serviced. Interrupts
at each priority level can be pre-programmed to go to the default service routine. For
maximum flexibility, interrupts can be vectored to the correct service routine by the
interrupting device.

1.2.6 Clock

To save on system costs, the MC68306 has an on-board oscillator that can be driven with
a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an

1-4 MC68306 USER'S MANUAL MOTOROLA

external 16.67-MHz oscillator can be used, with a tight skew between the input clock
signal and the bus clock on the CLKOUT pin.

1.2.7 Bus Timeout Monitor

A bus timeout monitor is provided to automatically terminate and report as erroneous any
bus cycle that is not normally terminated after a pre-programmed length of time. The user
can program this timeout period to be up to 4096 clocks.

1.2.8 IEEE 1149.1 Test

To aid in system diagnostics, the MC68306 includes dedicated user-accessible test logic
that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often
referred to as JTAG (Joint Test Action Group).

MOTOROLA MC68306 USER'S MANUAL 1-5

SECTION 2
SIGNAL DESCRIPTION

This section contains a brief description of the input and output signals, with reference (if
applicable) to other sections which give greater detail on its use. Figure 2-1 provides a
detailed diagram showing the integrated peripherals and signals, and Tables 2-1–2-7
provides a quick reference for determining a signal's name, mnemonic, its use as an input
or output, active state, and type identification.

NOTE

The terms assertion and negation will be used extensively.
This is done to avoid confusion when dealing with a mixture of
“active low” and “active high” signals. The term assert or
assertion is used to indicate that a signal is active or true,
independent of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.

MOTOROLA MC68306 USER'S MANUAL 2-1

CS0

CS1

CS2

CS3

CS4/A20

CS5/A21

CS6/A22

CS7/A23

DRAMW

RAS1
RAS0
CAS1
CAS0

DRAM

CONTROLLER

CHIP

SELECTS

A19–A16
A15/DRAMA14–A1/DRAMA0

D15–D0

EXTAL

XTAL

CLOCK

CLKOUT

AMODE

TCK

TMS

TDI

TDO

MODE

CONTROLLER

JTAG

PORT

EC000
CORE

PROCESSOR

TRST

IRQ7
IRQ4
IRQ1

IACK7

INTERRUPT

CONTROLLER

IACK4

FC2–FC0
RESET

BERR

HALT

AS
UDS
LDS

R/W

UW
LW
OE

DTACK

BR
BG
BGACK

IACK1

IRQ6/PB7
IRQ5/PB6
IRQ3/PB5

IRQ2/PB4
IACK6/PB3
IACK5/PB2
IACK3/PB1

PORT B

PORT A

16-BIT

TIMER/

COUNTER

TWO-

CHANNEL

SERIAL

I/O

X2

X1/CLK

RxDA
TxDA
RxDB
TxDB

IACK2/PB0

PA0

IP2

OP3

FLOW

CONTROL

RTSB/OP1
RTSA/OP0
CTSB/IP1

PA7

PA6

PA5

PA4

PA3

PA2

PA1

CTSA/IP0

Figure 2-1. MC68306 Detailed Block Diagram

2-2 MC68306 USER'S MANUAL MOTOROLA

Table 2-1. Bus Signal Summary

Input/

Signal Name Mnemonic

Address Signals A23–A1 Output Yes
Address Strobe AS Output Yes 4.7 K
Bus Error BERR I/O — 2.2 K
Bus Grant BG Output No
Bus Grant Acknowledge BGACK Input — (1)
Bus Request BR Input — (1)
Data Bus D15–D0 I/O Yes
Data Transfer Acknowledge DTACK I/O — 2.2 K
DRAM Multiplexed Address14–0 DRAMA14–DRAMA0 Output Yes
Function Codes FC2–FC0 Output Yes
Halt HALT I/O — 2.2 K
Lower Data Strobe LDS I/O Yes 4.7 K
Upper Data Strobe UDS I/O Yes 4.7 K
Lower-Byte Write Strobe LW Output No
Upper-Byte Write Strobe UW Output No
Output Enable OE Output No
Read/Write R/W Output Yes
Reset RESET I/O — 2.2 K

NOTES:

1. Pullup may be required, value depends on individual application. Must not be left floating.

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-2. Chip Select Signal Summary

Input/

Signal Name Mnemonic

Chip Select CS3–CS0 Output Yes 4.7 K
Chip Select 4–7/Address Port 23–20CS7–CS4/ A23–A20 Output Yes 4.7 K

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-3. DRAM Controller Signal Summary

Input/

Signal Name Mnemonic

Column Address Strobe CAS1–CAS0 Output Yes 4.7 K
Row Address Strobe RAS1–RAS0 Output Yes 4.7 K
DRAM Write Signal DRAMW Output Yes

Output

MOTOROLA MC68306 USER'S MANUAL 2-3

Three-State During

Bus Arbitration

Pullup Required

Table 2-4. Interrupt and Parallel Port Signal Summary

Input/

Signal Name Mnemonic

Interrupt Request Level 7, 4, 1 IRQ7, IRQ4, IRQ1 Input — (2)
Interrupt Request Level 6/Port B 7 IRQ6/PB7 I/O — (2)
Interrupt Request Level 5/Port B 6 IRQ5/PB6 I/O — (2)
Interrupt Request Level 3/Port B 5 IRQ3/PB5 I/O — (2)
Interrupt Request Level 2/Port B 4 IRQ2/PB4 I/O — (2)
Interrupt Acknowledge 7, 4, 1 IACK7, IACK4, IACK1 Output —
Interrupt Acknowledge 6/Port B 7 IACK6 /PB3 I/O — (2)
Interrupt Acknowledge 5/Port B 6 IACK5 /PB2 I/O — (2)
Interrupt Acknowledge 3/Port B 5 IACK3 /PB1 I/O — (2)
Interrupt Acknowledge 2/Port B 4 IACK2 /PB0 I/O — (2)
Port A PA7–PA0 I/O — (2)

NOTES:

2. Pullup or pulldown may be required, value depends on individual application.

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-5. Clock and Mode Control Signal Summary

Signal Name Mnemonic

Crystal Oscillator or External
Clock

Input/

Output

EXTAL Input —

Three-State During

Bus Arbitration

Pullup Required

Crystal Oscillator XTAL Output —
System Clock CLKOUT Output No
Address Mode AMODE Input —

2-4 MC68306 USER'S MANUAL MOTOROLA

Table 2-6. Serial Module Signal Summary

Input/

Signal Name Mnemonic

Channel A Receiver Serial Data RxDA Input —
Channel A Transmitter Serial

Data
Channel B Receiver Serial Data RxDB Input —
Channel B Transmitter Serial

Data
Channel A Clear-to-Send CTSA /IP0 Input — (1)
Channel A Request-to-Send RTSA /OP0 Output No
Channel B Clear-to-Send CTSB /IP1 Input — (1)
Channel B Request-to-Send RTSB /OP1 Output No
Crystal Output X2 Output No
Crystal Input or External Clock X1/CLK Input —
Parallel Input 2 IP2 Input — (1)
Parallel Output 3 OP3 Output No

NOTES:

1. Pullup may be required, value depends on individual application. Must not be left floating.

TxDA Output No

TxDB Output No

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-7. JTAG Signal Summary

Input/

Signal Name Mnemonic

Test Clock TCK Input —
Test Data Input TDI Input —
Test Data Output TDO Output —
Test Mode Select TMS Input —
Test Reset TRST Input — 4.7 K (3)

NOTES:

3. Pin has internal pullup, but external pulldown may be required for correct initialization.

Output

Three-State During

Bus Arbitration

Pulldown Required

2.1 BUS SIGNALS

The following signals are used for the MC68306 bus.

2.1.1 Address Bus (A23–A1)

This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3
provide the level number of the interrupt being acknowledged, and address lines A23–A4

MOTOROLA MC68306 USER'S MANUAL 2-5

are driven to logic high. A23–A20 are only available in address mode (AMODE=0). A15–

BERR

BG

BGACK

A1 are multiplexed with DRAM address.

2.1.2 Address Strobe (AS)

Assertion of this three-state signal indicates that the information on the address bus is a
valid address.

2.1.3 Bus Error (

)

Assertion of this bi-directional, open-drain signal indicates a problem in the current bus
cycle. The MC68306 can assert this signal to terminate a bus cycle when no external
response is received. An external source can assert BERR to indicate a problem such as:

1. No response from a device

2. No interrupt vector number returned

3. An illegal access request rejected by a memory management unit

4. Some other application-dependent error

Either the processor retries the bus cycle or performs exception processing, as
determined by interaction between the bus error signal and the halt signal.

2.1.4 Bus Request (BR)

This input can be wire-ORed with bus request signals from all other devices that could be
bus masters. Assertion of this signal indicates to the processor that some other device
needs to become the bus master. Bus requests can be issued at any time during a bus
cycle or between cycles.

2.1.5 Bus Grant (

)

This output signal indicates to all other potential bus master devices that the processor will
relinquish bus control at the end of the current bus cycle.

2.1.6 Bus Grant Acknowledge (

)

Assertion of this input indicates that some other device has become the bus master. This
signal should not be asserted until the following conditions are met:

1. A bus grant has been received.

2. Address strobe is inactive, which indicates that the microprocessor is not using the
bus.

3. Data transfer acknowledge is inactive, which indicates that neither memory nor
peripherals are using the bus.

4. Bus grant acknowledge is inactive, which indicates that no other device is claiming
bus mastership.

2-6 MC68306 USER'S MANUAL MOTOROLA

BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus

DTACK

HALT

arbitration system.

2.1.7 Data Bus (D15–D0)

This bi-directional, three-state bus is the general-purpose data path. It is 16 bits wide and
can transfer and accept data of either word or byte length. During an interrupt
acknowledge cycle, an external device can supply the interrupt vector number on data
lines D7–D0.

2.1.8 Data Transfer Acknowledge (

)

Assertion of this bi-directional, open-drain signal indicates the completion of the data
transfer. When the processor recognizes DTACK during a read cycle, data is latched, and
the bus cycle is terminated. When DTACK is recognized during a write cycle, the bus
cycle is terminated. The MC68306 generates DTACK for all internal cycles, DRAM cycles,
and autovector IACK cycles, and can be programmed to generate DTACK for any chip
select cycle. (Refer to 3.7 Asynchronous Operation and 3.8 Synchronous Operation.)

2.1.9 DRAM Multiplexed Address Bus (DRAMA14–DRAMA0)

These signals provide fifteen multiplexed address bits used during row address strobe.

2.1.10 Processor Function Codes (FC2–FC0)

These function code outputs indicate the mode (user or supervisor) and the address
space type currently being accessed, as shown in Table 2-8. The function code outputs
are valid whenever AS is asserted.

Table 2-8. Function Code Outputs

Function Code Output

FC2 FC1 FC0 Address Space Type

Low Low Low (Undefined, Reserved)
Low Low High User Data
Low High Low User Program

Low High High (Undefined, Reserved)
High Low Low (Undefined, Reserved)
High Low High Supervisor Data
High High Low Supervisor Program
High High High CPU Space

2.1.11 Halt (

)

External assertion of this bi-directional signal causes the processor to stop bus activity at
the completion of the bus cycle for which the input met set-up time requirements (i.e.,
current or next cycle). This operation places all control signals in the inactive state. For

MOTOROLA MC68306 USER'S MANUAL 2-7

additional information about the interaction between HALT and RESET , refer to 3.5 Reset

UDS, LDS

UDS LDS

W

OE UW LW

UW

Operation and for more information on HALT and BERR , refer to 3.4 Bus Error and Halt
Operation.

Processor assertion of HALT indicates a double bus fault condition. This condition is
unrecoverable; the MC68306 must be externally reset to resume operation.

2.1.12 Read/Write (R/W)

This three-state, bi-directional signal defines the data bus transfer as a read or write cycle.
The R/W signal relates to the data strobe signals described in the following paragraphs.

2.1.13 Upper And Lower Data Strobes (

)

These three-state, bi-directional signals and R/W control the flow of data on the data bus.
Table 2-9 lists the combinations of these signals, the corresponding data on the bus, and
the OE, LW, and UW signals. When the R/W line is high, the processor reads from the
data bus. When the R/W line is low, the processor drives the data bus. When another bus
master controls the bus, the UDS, LDS, and R/W pins become inputs and the OE, LW,
and UW signals are still decoded as shown in Table 2-9.

Table 2-9. Data Strobe Control of Data Bus

R/

High High — No Valid Data No Valid Data High High High

Low Low High Valid Data Bits

High Low High No Valid Data Valid Data Bits

Low High High Valid Data Bits

Low Low Low Valid Data Bits

D8–D15 D0–D7

Valid Data Bits

15–8

15–8

15–8

7–0

7–0

No Valid Data Low High High

Valid Data Bits

7–0

Low High High

Low High High

High Low Low

High Low Low Valid Data Bits

7–0*

Low High Low Valid Data Bits

15–8

*These conditions are a result of current implementation and may not appear
on future devices.

2.1.14 Upper-Byte Write (

)

Valid Data Bits

7–0

Valid Data Bits

15–8*

High High Low

High Low High

This signal is a combination of R/W low and UDS low for writing the upper-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the upper portion of the data bus on a write operation. UW is also decoded for external
bus masters.

2-8 MC68306 USER'S MANUAL MOTOROLA

2.1.15 Lower-Byte Write (

LW

RESET

CAS1–CAS0

RAS1–RAS0

DRAMW

)

This signal is a combination of R/W low and LDS low for writing the lower-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the lower portion of the data bus on a write operation. LW is also decoded for external
bus masters.

2.1.16 Output Enable (OE)

OE is a combination of R/ W high and an active data strobe ( UDS or LDS ). OE is also
decoded for external bus masters.

2.1.17 Reset (

)

The external assertion of this bi-directional, open-drain signal can start a system
initialization sequence by resetting the processor. The processor assertion of RESET
(from executing a RESET instruction) resets all external devices of a system without
affecting the internal state of the processor. The interaction of internal and external

RESET , and the HALT signal is described in paragraph 3.5 Reset Operation.

2.2 CHIP SELECT SIGNALS

These eight three-state signals provide address decodes with programmable base and
range. CS7 –CS4 are only available in chip select mode (AMODE bit =1). CS3–CS0 are
always available.

2.3 DRAM CONTROLLER SIGNALS

The following signals are used to control an external DRAM for the MC68306.

2.3.1 Column Address Strobe (

)

These three-state signals provide column address strobe timing for external DRAM. CAS0
controls data lines D15–D8 and CAS1 controls D7–D0.

2.3.2 Row Address Strobe (

)

These three-state signals provide row address strobe timing for external DRAM. Each
RAS controls a separate bank of DRAM.

2.3.3 DRAM Write Signal (

)

This signal provides write control for external DRAM.

2.4 INTERRUPT CONTROL AND PARALLEL PORT SIGNALS

The following signals are used for interrupt control on the MC68306.

MOTOROLA MC68306 USER'S MANUAL 2-9

2.4.1 Interrupt Request (IRQ7–IRQ1)

IACK7–IACK1

Three input signals (IRQ7, IRQ4, IRQ1) notify the core processor of an interrupt request.
Four additional interrupt request lines (IRQ6, IRQ5, IRQ3, and IRQ2) are shared with
parallel port B pins and may be individually programmed as interrupts.

2.4.2 Interrupt Acknowledge (

)

Three output signals (IACK7, IACK4, IACK1 ) indicate an interrupt acknowledge cycle.
Four additional interrupt acknowledge lines (IACK6, IACK5, IACK3, and IACK2) are
shared with parallel port B pins and may be individually programmed as interrupt
acknowledges.

2.4.3 Port A Signals (PA7–PA0)

These eight pins serve as port A parallel input/output signals.

2.4.4 Port B (PB7–PB0)

These eight pins are shared with IRQ6, IRQ5, IRQ3, IRQ2 and IACK6, IACK5, IACK3,
IACK2, and can be individually programmed to serve as port B parallel input/output

signals.

2.5 CLOCK AND MODE CONTROL SIGNALS

These four pins are used to connect an external crystal to the on-chip oscillator and define
the four multifunction pins.

2.5.1 Crystal Oscillator (EXTAL, XTAL)

These two pins are the connections for an external crystal to the internal oscillator circuit.
If an external oscillator is used, it should be connected to EXTAL, with XTAL left open,
and must drive CMOS levels. A crystal or clock input must be supplied at all times.

2.5.2 Clock Out (CLKOUT)

This output signal is the system clock output and is used as the bus timing reference by
external devices.

2.5.3 Address Mode (AMODE)

This input signal provides mode control for the multi-function chip select pins. When set to
zero, A23–A20 is selected and when set to one, CS7–CS4 is selected. The mode
selection is static: AMODE is latched at the end of any system reset.

2.6 SERIAL MODULE SIGNALS

The following paragraphs describe the signals used by the serial module on the MC68306.

2-10 MC68306 USER'S MANUAL MOTOROLA