MOTOROLA MC68306 User Guide

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MC68306

Integrated EC000 Processor

User’s Manual

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© MOTOROLA, 1993

PREFACE

The complete documentation package for the MC68306 consists of the MC68306UM/AD,

MC68306 EC000 Integrated Processor User’s Manual
Programmer’s Reference Manual,
Processor Product Brief

.

and the MC68306P/D,

, M68000PM/AD,

MC68306 EC000 Integrated

MC68000 Family

MC68306 EC000 Integrated Processor User’s Manual

The
capabilities, registers, and operation of the MC68306; the

Reference Manual
Integrated Processor Product Brief

capabilities.
This user’s manual is organized as follows:

Section 1 Introduction
Section 2 Signal Descriptions
Section 3 68000 Bus Operation Description
Section 4 EC000 Core Processor
Section 5 System Operation
Section 6 Serial Module
Section 7 IEEE 1149.1 Test Access Port
Section 8 Electrical Specifications
Section 9 Ordering Information and Mechanical Data

68K FAX-IT –

provides instruction details for the MC68306; and the

provides a brief description of the MC68306

Documentation Comments

describes the programming,

MC68000 Family Programmer’s

MC68306 EC000

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TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 MC68EC000 Core processor.................................................................................. 1-2

1.2 On-Chip Peripherals ............................................................................................... 1-3

1.2.1 Serial Module....................................................................................................... 1-3

1.2.2 DRAM Controller.................................................................................................. 1-4

1.2.3 Chip Selects......................................................................................................... 1-4

1.2.4 Parallel Ports........................................................................................................ 1-4

1.2.5 Interrupt Controller............................................................................................... 1-4

1.2.6 Clock.................................................................................................................... 1-5

1.2.7 Bus Timeout Monitor............................................................................................ 1-5

1.2.8 Mode Controller ................................................................................................... 1-5

1.2.9 IEEE 1149.1 Test................................................................................................. 1-5

Section 2

Signal Descriptions

2.1 Bus Signals............................................................................................................. 2-5

2.1.1 Address Bus (A23–A1) ........................................................................................ 2-5

2.1.2 Address Strobe (AS)............................................................................................ 2-5

2.1.3 Bus Error (BERR ) ................................................................................................ 2-5

2.1.4 Bus Request (BR) ................................................................................................ 2-5

2.1.5 Bus Grant (BG ) .................................................................................................... 2-6

2.1.6 Bus Grant Acknowledge (BGACK) ....................................................................... 2-6

2.1.7 Data Bus (D15–D0) ............................................................................................. 2-6

2.1.8 Data Transfer Acknowledge (DTACK) ................................................................. 2-6

2.1.9 DRAM Multiplexed Address Bus (DRAMA14 –DRAMA0) ..................................... 2-6

2.1.10 Processor Function Codes (FC2–FC0).............................................................. 2-6

2.1.11 Halt (HALT) ........................................................................................................ 2-7

2.1.12 Read/Write (R/W)............................................................................................... 2-7

2.1.13 Upper And Lower Data Strobes (UDS , LDS ) ..................................................... 2-7

2.1.14 Upper Byte Write (UW ) ...................................................................................... 2-8

2.1.15 Lower Byte Write (LW)....................................................................................... 2-8

2.1.16 Output Enable (OE) ........................................................................................... 2-8

2.1.17 Reset (RESET ) .................................................................................................. 2-8

2.2 Chip Select Signals................................................................................................. 2-9

MOTOROLA MC68306 USER'S MANUAL v

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

2.3 DRAM Controller Signals........................................................................................ 2-9

2.3.1 Column Address Strobe (CAS1–CAS0 )............................................................... 2-9

2.3.2 Row Address Strobe (RAS1–RAS0) .................................................................... 2-9

2.3.3 DRAM Write Signal (DRAMW)............................................................................. 2-9

2.4 Interrupt Control and Parallel Port Signals ............................................................. 2-9

2.4.1 Interrupt Request (IRQ7–IRQ1)........................................................................... 2-9

2.4.2 Interrupt Acknowledge (IACK7–IACK1)............................................................... 2-9

2.4.3 Port A Signals (PA7–PA0)................................................................................... 2-9

2.4.4 Port B (PB7–PB0)................................................................................................ 2-9

2.5 Clock and Mode Control Signals ............................................................................ 2-10

2.5.1 Crystal Oscillator (EXTAL, XTAL)........................................................................ 2-10

2.5.2 Clock Out (CLKOUT)........................................................................................... 2-10

2.5.3 Address Mode (AMODE)..................................................................................... 2-10

2.6 Serial Module Signals............................................................................................. 2-10

2.6.1 Channel A Receiver Serial-Data Input (RxDA).................................................... 2-10

2.6.2 Channel A Transmitter Serial-Data Output (TxDA) ............................................. 2-10

2.6.3 Channel B Receiver Serial-Data Input (RxDB).................................................... 2-10

2.6.4 Channel B Transmitter Serial-Data Output (TxDB) ............................................. 2-10

2.6.5 CTSA................................................................................................................... 2-11

2.6.6 RTSA................................................................................................................... 2-11

2.6.7 CTSB................................................................................................................... 2-11

2.6.8 RTSB................................................................................................................... 2-11

2.6.9 Crystal Oscillator (X1, X2) ................................................................................... 2-11

2.6.10 IP2 ..................................................................................................................... 2-11

2.6.11 OP3 ................................................................................................................... 2-11

2.7 JTAG Port Test Signals .......................................................................................... 2-11

2.7.1 Test Clock (TCK) ................................................................................................. 2-12

2.7.2 Test Mode Select (TMS)...................................................................................... 2-12

2.7.3 Test Data In (TDI)................................................................................................ 2-12

2.7.4 Test Data Out (TDO) ........................................................................................... 2-12

2.7.5 Test Reset (TRST) .............................................................................................. 2-12

Section 3

68000 Bus Operation Description

3.1 Data Transfer Operations ....................................................................................... 3-1

3.1.1 Read Cycle.......................................................................................................... 3-1

3.1.2 Write Cycle .......................................................................................................... 3-4

3.1.3 Read-Modify-Write Cycle..................................................................................... 3-7

3.1.4 CPU Space Cycle................................................................................................ 3-11

vi MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

3.2 Bus Arbitration ........................................................................................................ 3-12

3.2.1 Requesting the Bus ............................................................................................. 3-15

3.2.2 Receiving the Bus Grant...................................................................................... 3-16

3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)............................ 3-16

3.3 Bus Arbitration Control............................................................................................ 3-16

3.4 Bus Error and Halt Operation ................................................................................. 3-24

3.4.1 Bus Error Operation............................................................................................. 3-24

3.4.2 Retrying the Bus Cycle ........................................................................................ 3-25

3.4.3 Halt Operation...................................................................................................... 3-26

3.4.4 Double Bus Fault ................................................................................................. 3-27

3.5 Reset Operation...................................................................................................... 3-28

3.6 The Relationship of DTACK, BERR , and HALT ...................................................... 3-28

3.7 Asynchronous Operation ........................................................................................ 3-30

3.8 Synchronous Operation.......................................................................................... 3-33

Section 4

EC000 Core Processor

4.1 Features.................................................................................................................. 4-1

4.2 Processing States................................................................................................... 4-1

4.3 Programming Model ............................................................................................... 4-2

4.3.1 Data Format Summary......................................................................................... 4-3

4.3.2 Addressing Capabilities Summary....................................................................... 4-4

4.3.3 Notation Conventions .......................................................................................... 4-5

4.4 EC000 Core Instruction Set Overview .................................................................... 4-7

4.5 Exception Processing ............................................................................................. 4-12

4.5.1 Exception Vectors................................................................................................ 4-14

4.6 Processing of Specific Exceptions.......................................................................... 4-16

4.6.1 Reset Exception................................................................................................... 4-17

4.6.2 Interrupt Exceptions............................................................................................. 4-17

4.6.3 Uninitialized Interrupt Exception .......................................................................... 4-18

4.6.4 Spurious Interrupt Exception................................................................................ 4-18

4.6.5 Instruction Traps .................................................................................................. 4-18

4.6.6 Illegal and Unimplemented Instructions............................................................... 4-18

4.6.7 Privilege Violations............................................................................................... 4-19

4.6.8 Tracing................................................................................................................. 4-19

4.6.9 Bus Error.............................................................................................................. 4-20

4.6.10 Address Error..................................................................................................... 4-21

4.6.11 Multiple Exceptions............................................................................................ 4-21

MOTOROLA MC68306 USER'S MANUAL vii

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

Section 5

System Operation

5.1 MC68306 Address Space....................................................................................... 5-1

5.2 Register Description ............................................................................................... 5-3

5.2.1 System Register .................................................................................................. 5-3

5.2.2 Timer Vector Register.......................................................................................... 5-4

5.2.3 Bus Timeout Period Register............................................................................... 5-4

5.2.4 Interrupt Registers ............................................................................................... 5-5

5.2.4.1 Interrupt Control Register ................................................................................. 5-5

5.2.4.2 Interrupt Status Register................................................................................... 5-6

5.2.5 I/O Port Registers ................................................................................................ 5-6

5.2.5.1 Port Pins Register............................................................................................. 5-7

5.2.5.2 Port Direction Register ..................................................................................... 5-7

5.2.5.3 Port Data Register ............................................................................................ 5-8

5.2.6 Chip Selects......................................................................................................... 5-8

5.2.6.1 Chip Select Configuration Registers (High Half) .............................................. 5-9

5.2.6.2 Chip Select Configuration Registers (Low Half) ............................................... 5-10

5.2.7 DRAM Control Registers ..................................................................................... 5-12

5.2.7.1 DRAM Refresh Register ................................................................................... 5-13

5.2.7.2 DRAM Bank Configuration Register (High Half)............................................... 5-14

5.2.7.3 DRAM Bank Configuration Register (Low Half)................................................ 5-14

5.2.8 Automatic DTACK Generation............................................................................. 5-16

5.3 Crystal Oscillator .................................................................................................... 5-16

Section 6

Serial Module

6.1 Module Overview.................................................................................................... 6-2

6.1.1 Serial Communication Channels A and B............................................................ 6-3

6.1.2 Baud Rate Generator Logic................................................................................. 6-3

6.1.3 Timer/Counter...................................................................................................... 6-3

6.1.4 Interrupt Control Logic ......................................................................................... 6-3

6.1.5 Comparison of Serial Module to MC68681.......................................................... 6-4

6.2 Serial Module Signal Definitions............................................................................. 6-4

6.2.3 Channel A Transmitter Serial Data Output (TxDA).............................................. 6-4

6.2.4 Channel A Receiver Serial Data Input (RxDA).................................................... 6-5

6.2.5 Channel B Transmitter Serial Data Output (TxDB).............................................. 6-5

6.2.6 Channel B Receiver Serial Data Input (RxDB).................................................... 6-6

6.2.7 Channel A Request-To-Send (RTSA/OP0) ......................................................... 6-6

6.2.7.1 RTSA................................................................................................................ 6-6

6.2.7.2 OP0 .................................................................................................................. 6-6

6.2.8 Channel B Request-To-Send (RTSB/OP1) ......................................................... 6-6

viii MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

6.2.8.1 RTSB ................................................................................................................ 6-6

6.2.8.2 OP1................................................................................................................... 6-6

6.2.9 Channel A Clear-To-Send (CTSA/IP0) ................................................................ 6-6

6.2.9.1 CTSA ................................................................................................................ 6-6

6.2.9.2 IP0 .................................................................................................................... 6-6

6.2.10 Channel B Clear-To-Send (CTSB/IP1) .............................................................. 6-6

6.2.10.1 CTSB .............................................................................................................. 6-6

6.2.10.2 IP1 .................................................................................................................. 6-6

6.3 Operation ................................................................................................................ 6-7

6.3.1 Baud Rate Generator........................................................................................... 6-7

6.3.2 Transmitter and Receiver Operating Modes........................................................ 6-7

6.3.2.1 Transmitter........................................................................................................ 6-9

6.3.2.2 Receiver............................................................................................................ 6-10

6.3.2.3 FIFO Stack........................................................................................................ 6-11

6.3.3 Looping Modes .................................................................................................... 6-13

6.3.3.1 Automatic Echo Mode....................................................................................... 6-13

6.3.3.2 Local Loopback Mode....................................................................................... 6-13

6.3.3.3 Remote Loopback Mode................................................................................... 6-13

6.3.4 Multidrop Mode .................................................................................................... 6-14

6.3.5 Counter/Timer...................................................................................................... 6-16

6.3.5.1 Counter Mode................................................................................................... 6-16

6.3.5.2 Timer Mode....................................................................................................... 6-16

6.3.6 Bus Operation...................................................................................................... 6-17

6.3.6.1 Read Cycles ..................................................................................................... 6-17

6.3.6.2 Write Cycles...................................................................................................... 6-17

6.3.6.3 Interrupt Acknowledge Cycles .......................................................................... 6-17

6.4 Register Description and Programming.................................................................. 6-17

6.4.1 Register Description ............................................................................................ 6-17

6.4.1.1 Mode Register 1 (DUMR1) ............................................................................... 6-18

6.4.1.2 Mode Register 2 (DUMR2) ............................................................................... 6-20

6.4.1.3 Status Register (DUSR).................................................................................... 6-22

6.4.1.4 Clock-Select Register (DUCSR) ....................................................................... 6-24

6.4.1.5 Command Register (DUCR) ............................................................................. 6-26

6.4.1.6 Receiver Buffer (DURB) ................................................................................... 6-29

6.4.1.7 Transmitter Buffer (DUTB) ................................................................................ 6-29

6.4.1.8 Input Port Change Register (DUIPCR) ............................................................. 6-29

6.4.1.9 Auxiliary Control Register (DUACR) ................................................................ 6-30

6.4.1.10 Interrupt Status Register (DUISR) .................................................................. 6-31

6.4.1.11 Interrupt MASK Register (DUIMR).................................................................. 6-33

6.4.1.12 Count Register Current MSB of Counter (DUCUR)........................................ 6-33

6.4.1.13 Count Register Current LSB of Counter (DUCLR) ......................................... 6-33

6.4.1.14 Counter/Timer Upper Preload Register (CTUR)............................................. 6-34

MOTOROLA MC68306 USER'S MANUAL ix

TABLE OF CONTENTS (Continued)

Paragraph Page

Number Title Number

6.4.1.15 Counter/Timer Lower Pimer Register (CTLR) ................................................ 6-34

6.4.1.16 Interrupt Vector Register (DUIVR).................................................................. 6-34

6.4.1.17 Input Port Register.......................................................................................... 6-34

6.4.1.18 Output Port Control Register (DUOPCR) ....................................................... 6-35

6.4.1.19 Output Port Data Register (DUOP) ................................................................ 6-35

6.4.1.20 Start Counter Command Register .................................................................. 6-36

6.4.1.21 Stop Counter Command Register .................................................................. 6-36

6.4.2 Programming....................................................................................................... 6-36

6.4.2.1 Serial Module Initialization................................................................................ 6-36

6.4.2.2 I/O Driver Example ........................................................................................... 6-37

6.4.2.3 Interrupt Handling ............................................................................................. 6-37

6.5 Serial Module Initialization Sequence..................................................................... 6-43

Section 7

IEEE 1149.1 Test Access Port

7.1 Overview................................................................................................................. 7-1

7.2 TAP Controller ........................................................................................................ 7-3

7.3 Boundary Scan Register......................................................................................... 7-3

7.4 Instruction Register................................................................................................. 7-9

7.4.1 EXTEST (000) ..................................................................................................... 7-10

7.4.2 SAMPLE/PRELOAD (110) .................................................................................. 7-10

7.4.3 BYPASS (010, 101, 111)..................................................................................... 7-11

7.4.4 CLAMP (011)...................................................................................................... 7-11

7.5 MC68306 Restrictions ............................................................................................ 7-11

7.6 Non-IEEE 1149.1 Operation................................................................................... 7-12

Section 8

Electrical Specifications

8.1 Maximum Ratings................................................................................................... 8-1

8.2 Thermal Characteristics.......................................................................................... 8-1

8.3 Power Considerations............................................................................................. 8-2

8.4 AC Electrical Specification Definitions.................................................................... 8-2

8.5 DC Electrical Specifications.................................................................................... 8-4

8.6 AC Electrical Specifications—Clock Timing............................................................ 8-4

8.7 AC Electrical Specifications—Read and Write ....................................................... 8-5

8.8 AC Electrical Specifications—Chip Selects ............................................................ 8-9

8.9 AC Electrical Specifications—Bus Arbitration......................................................... 8-10

8.10 Bus Operation—DRAM Accesses AC Timing Specifications............................... 8-12

8.11Serial Module Electrical Characteristics ................................................................ 8-15

8.12 Serial Module AC Electrical Characteristics—Clock Timing................................. 8-16

8.13 AC Electrical Characteristics—Port Timing .......................................................... 8-16

8.14 AC Electrical Characteristics—Interrupt Reset..................................................... 8-16

x MC68306 USER'S MANUAL MOTOROLA

TABLE OF CONTENTS (Continued)

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Number Title Number

8.14 AC Electrical Characteristics—Interrupt Reset ..................................................... 8-16

8.15 AC Electrical Characteristics—Transmitter Timing ............................................... 8-17

8.16 AC Electrical Characteristics—Receiver Timing................................................... 8-18

8.17 IEEE 1149.1 Electrical Characteristics ................................................................. 8-19

Section 9

Ordering Information and Mechanical Data

9.1 Standard Ordering Information ............................................................................... 9-1

9.2 Pin Assignments ..................................................................................................... 9-2

MOTOROLA MC68306 USER'S MANUAL xi

LIST OF ILLUSTRATIONS

Figure Page

Number Title Number

Figure 1-1. MC68306 Simplified Block Diagram....................................................... 1-1

Figure 2-1. MC68306 Detailed Block Diagram......................................................... 2-2

Figure 3-1. Word Read Cycle Flowchart .................................................................. 3-2

Figure 3-2. Byte Read Cycle Flowchart.................................................................... 3-2

Figure 3-3. Read and Write Cycle Timing Diagram .................................................. 3-3

Figure 3-4. Word and Byte Read Cycle Timing Diagram ......................................... 3-3

Figure 3-5. Word Write Cycle Flowchart................................................................... 3-5

Figure 3-6. Byte Write Cycle Flowchart .................................................................... 3-6

Figure 3-7. Word and Byte Write Cycle Timing Diagram.......................................... 3-6

Figure 3-8. Read-Modify-Write Cycle Flowchart....................................................... 3-8

Figure 3-9. Read-Modify-Write Cycle Timing Diagram............................................. 3-9

Figure 3-10. Interrupt Acknowledge Cycle ............................................................... 3-11

Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram ..................................... 3-12

Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart ........................................ 3-13

Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart........................................... 3-14

Figure 3-14. Three-Wire Bus Arbitration Timing Diagram ........................................ 3-15

Figure 3-15. Two-Wire Bus Arbitration Timing Diagram........................................... 3-15

Figure 3-16. External Asynchronous Signal Synchronization................................... 3-17

Figure 3-17. Bus Arbitration Unit State Diagrams..................................................... 3-19

Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active.......... 3-20

Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive ................. 3-21

Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case ............... 3-22

Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active ............ 3-23

Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive.................... 3-24

Figure 3-23. Two-Wire Bus Arbitration Timing Diagram—Special Case .................. 3-25

Figure 3-24. Bus Error Timing Diagram.................................................................... 3-26

Figure 3-25. Retry Bus Cycle Timing Diagram ......................................................... 3-27

Figure 3-26. Halt Operation Timing Diagram............................................................ 3-28

Figure 3-27. Reset Operation Timing Diagram......................................................... 3-29

Figure 3-28 Fully Asynchronous Read Cycle ........................................................... 3-32

Figure 3-29. Fully Asynchronous Write Cycle........................................................... 3-32

Figure 3-30. Pseudo-Asynchronous Read Cycle ..................................................... 3-33

Figure 3-31. Pseudo-Asynchronous Write Cycle...................................................... 3-34

Figure 3-32. Synchronous Read Cycle..................................................................... 3-36

Figure 3-33. Synchronous Write Cycle..................................................................... 3-37

xii MC68306 USER'S MANUAL MOTOROLA

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

Figure 4-1. Programmer's Model .............................................................................. 4-2

Figure 4-2. Status Register....................................................................................... 4-3

Figure 4-3. General Exception Processing Flowchart .............................................. 4-13

Figure 4-4. General Form of Exception Stack Frame............................................... 4-14

Figure 4-5. Exception Vector Format........................................................................ 4-15

Figure 4-6. Address Translated from 8-Bit Vector Number ...................................... 4-15

Figure 4-7. Supervisor Stack Order for Bus or Address Error Exception ................. 4-21

Figure 5-1. Chip Select Expansion ........................................................................... 5-12

Figure 5-2. Oscillator Circuit Diagram....................................................................... 5-17

Figure 6-1. Simplified Block Diagram ....................................................................... 6-1

Figure 6-2. External and Internal Interface Signals .................................................. 6-5

Figure 6-3. Baud Rate Generator Block Diagram..................................................... 6-7

Figure 6-4. Transmitter and Receiver Functional Diagram....................................... 6-8

Figure 6-5. Transmitter Timing Diagram ................................................................... 6-9

Figure 6-6. Receiver Timing Diagram....................................................................... 6-11

Figure 6-7. Looping Modes Functional Diagram....................................................... 6-14

Figure 6-8. Multidrop Mode Timing Diagram ............................................................ 6-15

Figure 6-9. Serial Module Programming Model........................................................ 6-18

Figure 6-10. Serial Module Programming Flowchart ................................................ 6-38

Figure 7-1. Test Access Port Block Diagram............................................................ 7-2

Figure 7-2. TAP Controller State Machine................................................................ 7-3

Figure 7-3. Output Cell (O.Cell) ................................................................................ 7-7

Figure 7-4. Input Cell (I.Cell)..................................................................................... 7-7

Figure 7-5. Output Control Cell (En.Cell).................................................................. 7-8

Figure 7-6. Bidirectional Cell (IO.Cell) ...................................................................... 7-8

Figure 7-7. Bidirectional Cell (IOx0.Cell)................................................................... 7-9

Figure 7-8. General Arrangement for Bidirectional Pins ........................................... 7-9

Figure 7-9. Bypass Register ..................................................................................... 7-11

Figure 8-1. Drive Levels and Test Points for AC Specifications ............................... 8-3

Figure 8-2. Clock Output Timing............................................................................... 8-4

Figure 8-3. Read Cycle Timing Diagram................................................................... 8-7

Figure 8-4. Write Cycle Timing Diagram................................................................... 8-8

Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram....................... 8-9

Figure 8-6. Bus Arbitration Timing Diagram ............................................................. 8-10

Figure 8-7. Bus Arbitration Timing Diagram ............................................................. 8-11

Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh............................................. 8-13

Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh ............................................. 8-14

Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh................................................ 8-14

MOTOROLA MC68306 USER'S MANUAL xiii

LIST OF ILLUSTRATIONS (Continued)

Figure Page

Number Title Number

Figure 8-11. DRAM Timing – 1-Wait, Test and Set .................................................. 8-15

Figure 8-12. Clock Timing......................................................................................... 8-16

Figure 8-13. Port Timing........................................................................................... 8-16

Figure 8-14. Interrupt Reset Timing.......................................................................... 8-17

Figure 8-15. Transmit Timing ................................................................................... 8-17

Figure 8-16. Receive Timing .................................................................................... 8-18

Figure 8-17. Test Clock Input Timing Diagram......................................................... 8-19

Figure 8-18. Boundary Scan Timing Diagram .......................................................... 8-20

Figure 8-19. Test Access Port Timing Diagram........................................................ 8-20

xiv MC68306 USER'S MANUAL MOTOROLA

LIST OF TABLES

Table Page

Number Title Number

Table 2-1. Bus Signal Summary ............................................................................... 2-3

Table 2-2. Chip Select Signal Summary................................................................... 2-3

Table 2-3. DRAM Controller Signal Summary .......................................................... 2-3

Table 2-4. Interrupt and Parallel Port Signal Summary ............................................ 2-4

Table 2-5. Clock and Mode Control Signal Summary............................................... 2-4

Table 2-6. Serial Module Signal Summary ............................................................... 2-4

Table 2-7. JTAG Signal Summary ............................................................................ 2-5

Table 2-8. Function Code Outputs............................................................................ 2-7

Table 2-9. Data Strobe Control of Data Bus ............................................................. 2-8

Table 3-1. DTACK, BERR, and HALT Assertion Results ......................................... 3-24

Table 3-2. BERR and HALT Negation Results ......................................................... 3-25

Table 4-1. Processor Data Formats.......................................................................... 4-3

Table 4-2. Effective Addressing Modes.................................................................... 4-4

Table 4-3. Notation Conventions .............................................................................. 4-5

Table 4-4. EC000 Core Instruction Set Summary .................................................... 4-8

Table 4-5. Exception Vector Assignments................................................................ 4-16

Table 4-6. Exception Grouping and Priority.............................................................. 4-22

Table 5-1. MC68306 Memory Map ........................................................................... 5-2

Table 5-2. Chip Select Match Bits ............................................................................ 5-11

Table 5-3. DRAM Address Multiplexer...................................................................... 5-13

Table 5-4. DRAM Bank Match Bits ........................................................................... 5-15

Table 6-1. PMx and PT Control Bits ......................................................................... 6-20

Table 6-2. B/Cx Control Bits ..................................................................................... 6-20

Table 6-3. CMx Control Bits...................................................................................... 6-21

Table 6-4. SBx Control Bits ...................................................................................... 6-22

Table 6-5. RCSx Control Bits.................................................................................... 6-25

Table 6-6. TCSx Control Bits .................................................................................... 6-26

Table 6-7. MISCx Control Bits .................................................................................. 6-27

Table 6-8. TCx Control Bits ...................................................................................... 6-28

Table 6-9. RCx Control Bits...................................................................................... 6-28

Table 6-10. Counter/Timer Mode and Source Select Bits ........................................ 6-30

MOTOROLA MC68306 USER'S MANUAL xv

LIST OF TABLES (Continued)

Table Page

Number Title Number

Table 7-1. Boundary Scan Control Bits .................................................................... 7-4

Table 7-2. Boundary Scan Bit Definitions................................................................. 7-5

Table 7-3. Instructions .............................................................................................. 7-10

xvi MC68306 USER'S MANUAL MOTOROLA

SECTION 1
INTRODUCTION

The MC68306 is an integrated processor containing an MC68EC000 processor and
elements common to many MC68000- and MC68EC000-based systems. Designers of
virtually any application requiring MC68000-class performance will find that the MC68306
reduces design time by providing valuable system elements integrated in one chip. The
combination of peripherals offered in the MC68306 can be found in a diverse range of
microprocessor-based systems, including embedded control and general computing.
Systems requiring serial communication and dynamic random access memory (DRAM)
can especially benefit from using the MC68306.

The MC68306's high level of functional integration results in significant reductions in
component count, power consumption, board space, and cost while yielding much higher
system reliability and shorter design time. Complete code compatibility with the MC68000
affords the designer access to a broad base of established real-time kernels, operating
systems, languages, applications, and development tools, many of which are oriented
towards embedded control. Figure 1-1 shows a simplified block diagram of the MC68306.

8

DRAM

CONTROLLER

8

CHIP

SELECTS

INTERRUPT

CONTROLLER

CLOCK

MODE

CONTROLLER

JTAG
PORT

PORT A

PORT B

8

16-BIT
TIMER

EC000
CORE

PROCESSOR

TWO-CHANNEL

SERIAL

I/O

24

16

Figure 1-1. MC68306 Simplified Block Diagram

MOTOROLA MC68306 USER'S MANUAL 1-1

The primary features of the MC68306 are as follows:

• Functional Integration on a Single Piece of Silicon

• EC000 Core—Identical to MC68EC000 Microprocessor
— Complete Code Compatibility with MC68000 and MC68EC000
— High Performance—2.4 MIPS
— Extended Internal Address Range – to 4 Gbyte

• Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)
— Baud Rate Generators
— Modem Control
— Compatible with MC68681/MC2681
— Integrated 16-Bit Timer/Counter

• DRAM Controller
— Supports up to 16 Mbytes using 4M x 1 DRAMs, 64 Mbytes using 16M x 1 DRAMs
— Provides Zero Wait State Interface to 80-ns DRAMs
— Programmable Refresh Timer Provides CAS-before-RAS Refresh

• Chip Selects
— Eight Programmable Chip Select Signals
— Provide Eight Separate 1-Mbyte Spaces or Four Separate 16-Mbyte Spaces
— Programmable Wait States

• Programmable Interrupt Controller

• Bus Timeout

• 24 Address Lines, 16 Data Lines

• 16.67 MHz, 5 Volt Operation

• 144-Pin Thin Quad Flat Pack (TQFP)or 132-Pin Plastic Quad Flat Pack (PQFP)

1.1 MC68EC000 CORE PROCESSOR

The MC68EC000 is a core implementation of the MC68000 32-bit microprocessor
architecture. The programmer can use any of the eight 32-bit data registers for fast
manipulation of data and any of the eight 32-bit address registers for indexing data in
memory. Flexible instructions support data movement, arithmetic functions, logical
operations, shifts and rotates, bit set and clear, conditional and unconditional program
branches, and overall system control.

The MC68EC000 core can operate on data types of single bits, binary-coded decimal
(BCD) digits, and 8, 16, and 32 bits. The integrated chip selects allow peripherals and
data in memory to reside anywhere in the 4-Gbyte linear address space. A supervisor
operating mode protects system-level resources from the more restricted user mode,
allowing a true virtual environment to be developed. Many addressing modes complement

1-2 MC68306 USER'S MANUAL MOTOROLA

these instructions, including predecrement and postincrement, which allow simple stack
and queue maintenance and scaled indexing for efficient table accesses. Data types and
addressing modes are supported orthogonally by all data operations and with all
appropriate addressing modes. Position-independent code is easily written.

Like all M68000 family processors, the MC68EC000 core recognizes interrupts of seven
different priority levels and allows either an automatic vector or a peripheral-supplied
vector to direct the processor to the desired service routine. Internal trap exceptions
ensure proper instruction execution with good addresses and data, allow operating system
intervention in special situations, and permit instruction tracing. Hardware signals can
either terminate or rerun bad memory accesses before instructions process data
incorrectly. The EC000 core provides 2.4 MIPS at 16.67 MHz.

1.2 ON-CHIP PERIPHERALS

To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules and
typical glue logic. The functions on the MC68306 include two serial channels, a
timer/counter, a DRAM controller, a parallel port, and system glue logic.

1.2.1 Serial Module

Most digital systems use serial I/O to communicate with host computers, operator
terminals, or remote devices. The MC68306 contains a two-channel, full-duplex UART
with an integrated timer. An on-chip baud rate generator provides standard baud rates up
the 38.4K baud to each channel's receiver and transmitter. The serial module is identical
to the MC68681/MC2681 DUART.

Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8
bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. Each channel provides
a wide variety of error detection and maskable interrupt capability. Full-duplex, autoecho
loopback, local loopback, and remote loopback modes can be selected. Multidrop
applications are also supported.

A 3.6864 MHz crystal drives the baud rate generators. Each transmit and receive channel
can be programmed for a different baud rate. Full modem support is provided with
separate request-to-send (RTS) and clear-to-send (CTS) signals for each channel.

The integrated 16-bit timer/counter can operate in a counter mode or a timer mode. The
timer/counter can function as a system stopwatch, a real-time single interrupt generator,
or a device watchdog when in counter mode. In timer mode, the timer/counter can be
used as a programmable clock source for channels A and B, a periodic interrupt
generator, or a variable duty cycle square-wave generator.

1.2.2 DRAM Controller

DRAM is used in many systems since it is the least expensive form of high-speed storage
available. However, considerable design effort is often spent designing the interface

MOTOROLA MC68306 USER'S MANUAL 1-3

between the processor and DRAM. The MC68306 contains a full DRAM controller, greatly
reducing design time and complexity.

The DRAM controller provides row address strobe ( RAS) and column address strobe
(CAS) signals for two separate banks of DRAMs. Each bank can include up to 16 devices;
up to 15 multiplexed address lines are also available. Thus, using 4M x 1 DRAMs, up to
16 Mbytes of DRAM are supported; with 16M x 1 DRAMs, up to 64 Mbytes of DRAM are
supported. A programmable refresh timer provides CAS-before-RAS refreshes at
designated intervals.

The DRAM controller has its own address registers that control the address range
selected by each RAS and CAS signal, leaving the eight integrated chip selects free for
other system peripherals. DRAM accesses are zero wait states using 80-ns DRAMs.

1.2.3 Chip Selects

The MC68306 provides up to eight programmable chip select outputs, in most cases
eliminating the need for external address decoding. All handshaking and timing signals
are provided, with up to 950-ns access times. Each chip select can access a 16 Mbyte
address space located anywhere in the 4-Gbyte address range. Internal registers allow
the base address, range, and cycle duration of each chip select to be independently
programmed. After reset, chip select (CS0) responds to all accesses until the chip selects
have been properly programmed. Four of the chip selects are multiplexed with the most
significant address bits (A23–A20). The address mode (AMODE) input determines the
functions of these outputs.

1.2.4 Parallel Ports

Two 8-bit parallel ports are provided. The port pins can be individually programmed to be
inputs or outputs. If the pins are programmed to be inputs, the value on those pins can be
read by accessing an on-board register. If the pins are programmed to be outputs, the
pins will reflect the value programmed into another on-board register. The port B pins are
multiplexed with four interrupt request and four interrupt acknowledge lines. The function
of these pins is controlled by the internal registers.

1.2.5 Interrupt Controller

Seven input signals are provided to trigger an external interrupt, one for each of the seven
priority levels supported. Each input can be programmed to be active high or active low.
Seven separate outputs indicate the priority level of the interrupt being serviced. Interrupts
at each priority level can be pre-programmed to go to the default service routine. For
maximum flexibility, interrupts can be vectored to the correct service routine by the
interrupting device.

1.2.6 Clock

To save on system costs, the MC68306 has an on-board oscillator that can be driven with
a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an

1-4 MC68306 USER'S MANUAL MOTOROLA

external 16.67-MHz oscillator can be used, with a tight skew between the input clock
signal and the bus clock on the CLKOUT pin.

1.2.7 Bus Timeout Monitor

A bus timeout monitor is provided to automatically terminate and report as erroneous any
bus cycle that is not normally terminated after a pre-programmed length of time. The user
can program this timeout period to be up to 4096 clocks.

1.2.8 IEEE 1149.1 Test

To aid in system diagnostics, the MC68306 includes dedicated user-accessible test logic
that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often
referred to as JTAG (Joint Test Action Group).

MOTOROLA MC68306 USER'S MANUAL 1-5

SECTION 2
SIGNAL DESCRIPTION

This section contains a brief description of the input and output signals, with reference (if
applicable) to other sections which give greater detail on its use. Figure 2-1 provides a
detailed diagram showing the integrated peripherals and signals, and Tables 2-1–2-7
provides a quick reference for determining a signal's name, mnemonic, its use as an input
or output, active state, and type identification.

NOTE

The terms assertion and negation will be used extensively.
This is done to avoid confusion when dealing with a mixture of
“active low” and “active high” signals. The term assert or
assertion is used to indicate that a signal is active or true,
independent of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.

MOTOROLA MC68306 USER'S MANUAL 2-1

CS0

CS1

CS2

CS3

CS4/A20

CS5/A21

CS6/A22

CS7/A23

DRAMW

RAS1
RAS0
CAS1
CAS0

DRAM

CONTROLLER

CHIP

SELECTS

A19–A16
A15/DRAMA14–A1/DRAMA0

D15–D0

EXTAL

XTAL

CLOCK

CLKOUT

AMODE

TCK

TMS

TDI

TDO

MODE

CONTROLLER

JTAG

PORT

EC000
CORE

PROCESSOR

TRST

IRQ7
IRQ4
IRQ1

IACK7

INTERRUPT

CONTROLLER

IACK4

FC2–FC0
RESET

BERR

HALT

AS
UDS
LDS

R/W

UW
LW
OE

DTACK

BR
BG
BGACK

IACK1

IRQ6/PB7
IRQ5/PB6
IRQ3/PB5

IRQ2/PB4
IACK6/PB3
IACK5/PB2
IACK3/PB1

PORT B

PORT A

16-BIT

TIMER/

COUNTER

TWO-

CHANNEL

SERIAL

I/O

X2

X1/CLK

RxDA
TxDA
RxDB
TxDB

IACK2/PB0

PA0

IP2

OP3

FLOW

CONTROL

RTSB/OP1
RTSA/OP0
CTSB/IP1

PA7

PA6

PA5

PA4

PA3

PA2

PA1

CTSA/IP0

Figure 2-1. MC68306 Detailed Block Diagram

2-2 MC68306 USER'S MANUAL MOTOROLA

Table 2-1. Bus Signal Summary

Input/

Signal Name Mnemonic

Address Signals A23–A1 Output Yes
Address Strobe AS Output Yes 4.7 K
Bus Error BERR I/O — 2.2 K
Bus Grant BG Output No
Bus Grant Acknowledge BGACK Input — (1)
Bus Request BR Input — (1)
Data Bus D15–D0 I/O Yes
Data Transfer Acknowledge DTACK I/O — 2.2 K
DRAM Multiplexed Address14–0 DRAMA14–DRAMA0 Output Yes
Function Codes FC2–FC0 Output Yes
Halt HALT I/O — 2.2 K
Lower Data Strobe LDS I/O Yes 4.7 K
Upper Data Strobe UDS I/O Yes 4.7 K
Lower-Byte Write Strobe LW Output No
Upper-Byte Write Strobe UW Output No
Output Enable OE Output No
Read/Write R/W Output Yes
Reset RESET I/O — 2.2 K

NOTES:

1. Pullup may be required, value depends on individual application. Must not be left floating.

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-2. Chip Select Signal Summary

Input/

Signal Name Mnemonic

Chip Select CS3–CS0 Output Yes 4.7 K
Chip Select 4–7/Address Port 23–20CS7–CS4/ A23–A20 Output Yes 4.7 K

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-3. DRAM Controller Signal Summary

Input/

Signal Name Mnemonic

Column Address Strobe CAS1–CAS0 Output Yes 4.7 K
Row Address Strobe RAS1–RAS0 Output Yes 4.7 K
DRAM Write Signal DRAMW Output Yes

Output

MOTOROLA MC68306 USER'S MANUAL 2-3

Three-State During

Bus Arbitration

Pullup Required

Table 2-4. Interrupt and Parallel Port Signal Summary

Input/

Signal Name Mnemonic

Interrupt Request Level 7, 4, 1 IRQ7, IRQ4, IRQ1 Input — (2)
Interrupt Request Level 6/Port B 7 IRQ6/PB7 I/O — (2)
Interrupt Request Level 5/Port B 6 IRQ5/PB6 I/O — (2)
Interrupt Request Level 3/Port B 5 IRQ3/PB5 I/O — (2)
Interrupt Request Level 2/Port B 4 IRQ2/PB4 I/O — (2)
Interrupt Acknowledge 7, 4, 1 IACK7, IACK4, IACK1 Output —
Interrupt Acknowledge 6/Port B 7 IACK6 /PB3 I/O — (2)
Interrupt Acknowledge 5/Port B 6 IACK5 /PB2 I/O — (2)
Interrupt Acknowledge 3/Port B 5 IACK3 /PB1 I/O — (2)
Interrupt Acknowledge 2/Port B 4 IACK2 /PB0 I/O — (2)
Port A PA7–PA0 I/O — (2)

NOTES:

2. Pullup or pulldown may be required, value depends on individual application.

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-5. Clock and Mode Control Signal Summary

Signal Name Mnemonic

Crystal Oscillator or External
Clock

Input/

Output

EXTAL Input —

Three-State During

Bus Arbitration

Pullup Required

Crystal Oscillator XTAL Output —
System Clock CLKOUT Output No
Address Mode AMODE Input —

2-4 MC68306 USER'S MANUAL MOTOROLA

Table 2-6. Serial Module Signal Summary

Input/

Signal Name Mnemonic

Channel A Receiver Serial Data RxDA Input —
Channel A Transmitter Serial

Data
Channel B Receiver Serial Data RxDB Input —
Channel B Transmitter Serial

Data
Channel A Clear-to-Send CTSA /IP0 Input — (1)
Channel A Request-to-Send RTSA /OP0 Output No
Channel B Clear-to-Send CTSB /IP1 Input — (1)
Channel B Request-to-Send RTSB /OP1 Output No
Crystal Output X2 Output No
Crystal Input or External Clock X1/CLK Input —
Parallel Input 2 IP2 Input — (1)
Parallel Output 3 OP3 Output No

NOTES:

1. Pullup may be required, value depends on individual application. Must not be left floating.

TxDA Output No

TxDB Output No

Output

Three-State During

Bus Arbitration

Pullup Required

Table 2-7. JTAG Signal Summary

Input/

Signal Name Mnemonic

Test Clock TCK Input —
Test Data Input TDI Input —
Test Data Output TDO Output —
Test Mode Select TMS Input —
Test Reset TRST Input — 4.7 K (3)

NOTES:

3. Pin has internal pullup, but external pulldown may be required for correct initialization.

Output

Three-State During

Bus Arbitration

Pulldown Required

2.1 BUS SIGNALS

The following signals are used for the MC68306 bus.

2.1.1 Address Bus (A23–A1)

This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3
provide the level number of the interrupt being acknowledged, and address lines A23–A4

MOTOROLA MC68306 USER'S MANUAL 2-5

are driven to logic high. A23–A20 are only available in address mode (AMODE=0). A15–

BERR

BG

BGACK

A1 are multiplexed with DRAM address.

2.1.2 Address Strobe (AS)

Assertion of this three-state signal indicates that the information on the address bus is a
valid address.

2.1.3 Bus Error (

)

Assertion of this bi-directional, open-drain signal indicates a problem in the current bus
cycle. The MC68306 can assert this signal to terminate a bus cycle when no external
response is received. An external source can assert BERR to indicate a problem such as:

1. No response from a device

2. No interrupt vector number returned

3. An illegal access request rejected by a memory management unit

4. Some other application-dependent error

Either the processor retries the bus cycle or performs exception processing, as
determined by interaction between the bus error signal and the halt signal.

2.1.4 Bus Request (BR)

This input can be wire-ORed with bus request signals from all other devices that could be
bus masters. Assertion of this signal indicates to the processor that some other device
needs to become the bus master. Bus requests can be issued at any time during a bus
cycle or between cycles.

2.1.5 Bus Grant (

)

This output signal indicates to all other potential bus master devices that the processor will
relinquish bus control at the end of the current bus cycle.

2.1.6 Bus Grant Acknowledge (

)

Assertion of this input indicates that some other device has become the bus master. This
signal should not be asserted until the following conditions are met:

1. A bus grant has been received.

2. Address strobe is inactive, which indicates that the microprocessor is not using the
bus.

3. Data transfer acknowledge is inactive, which indicates that neither memory nor
peripherals are using the bus.

4. Bus grant acknowledge is inactive, which indicates that no other device is claiming
bus mastership.

2-6 MC68306 USER'S MANUAL MOTOROLA

BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus

DTACK

HALT

arbitration system.

2.1.7 Data Bus (D15–D0)

This bi-directional, three-state bus is the general-purpose data path. It is 16 bits wide and
can transfer and accept data of either word or byte length. During an interrupt
acknowledge cycle, an external device can supply the interrupt vector number on data
lines D7–D0.

2.1.8 Data Transfer Acknowledge (

)

Assertion of this bi-directional, open-drain signal indicates the completion of the data
transfer. When the processor recognizes DTACK during a read cycle, data is latched, and
the bus cycle is terminated. When DTACK is recognized during a write cycle, the bus
cycle is terminated. The MC68306 generates DTACK for all internal cycles, DRAM cycles,
and autovector IACK cycles, and can be programmed to generate DTACK for any chip
select cycle. (Refer to 3.7 Asynchronous Operation and 3.8 Synchronous Operation.)

2.1.9 DRAM Multiplexed Address Bus (DRAMA14–DRAMA0)

These signals provide fifteen multiplexed address bits used during row address strobe.

2.1.10 Processor Function Codes (FC2–FC0)

These function code outputs indicate the mode (user or supervisor) and the address
space type currently being accessed, as shown in Table 2-8. The function code outputs
are valid whenever AS is asserted.

Table 2-8. Function Code Outputs

Function Code Output

FC2 FC1 FC0 Address Space Type

Low Low Low (Undefined, Reserved)
Low Low High User Data
Low High Low User Program

Low High High (Undefined, Reserved)
High Low Low (Undefined, Reserved)
High Low High Supervisor Data
High High Low Supervisor Program
High High High CPU Space

2.1.11 Halt (

)

External assertion of this bi-directional signal causes the processor to stop bus activity at
the completion of the bus cycle for which the input met set-up time requirements (i.e.,
current or next cycle). This operation places all control signals in the inactive state. For

MOTOROLA MC68306 USER'S MANUAL 2-7

additional information about the interaction between HALT and RESET , refer to 3.5 Reset

UDS, LDS

UDS LDS

W

OE UW LW

UW

Operation and for more information on HALT and BERR , refer to 3.4 Bus Error and Halt
Operation.

Processor assertion of HALT indicates a double bus fault condition. This condition is
unrecoverable; the MC68306 must be externally reset to resume operation.

2.1.12 Read/Write (R/W)

This three-state, bi-directional signal defines the data bus transfer as a read or write cycle.
The R/W signal relates to the data strobe signals described in the following paragraphs.

2.1.13 Upper And Lower Data Strobes (

)

These three-state, bi-directional signals and R/W control the flow of data on the data bus.
Table 2-9 lists the combinations of these signals, the corresponding data on the bus, and
the OE, LW, and UW signals. When the R/W line is high, the processor reads from the
data bus. When the R/W line is low, the processor drives the data bus. When another bus
master controls the bus, the UDS, LDS, and R/W pins become inputs and the OE, LW,
and UW signals are still decoded as shown in Table 2-9.

Table 2-9. Data Strobe Control of Data Bus

R/

High High — No Valid Data No Valid Data High High High

Low Low High Valid Data Bits

High Low High No Valid Data Valid Data Bits

Low High High Valid Data Bits

Low Low Low Valid Data Bits

D8–D15 D0–D7

Valid Data Bits

15–8

15–8

15–8

7–0

7–0

No Valid Data Low High High

Valid Data Bits

7–0

Low High High

Low High High

High Low Low

High Low Low Valid Data Bits

7–0*

Low High Low Valid Data Bits

15–8

*These conditions are a result of current implementation and may not appear
on future devices.

2.1.14 Upper-Byte Write (

)

Valid Data Bits

7–0

Valid Data Bits

15–8*

High High Low

High Low High

This signal is a combination of R/W low and UDS low for writing the upper-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the upper portion of the data bus on a write operation. UW is also decoded for external
bus masters.

2-8 MC68306 USER'S MANUAL MOTOROLA

2.1.15 Lower-Byte Write (

LW

RESET

CAS1–CAS0

RAS1–RAS0

DRAMW

)

This signal is a combination of R/W low and LDS low for writing the lower-byte of a 16-bit
port. This signal simplifies memory system design by explicitly signalling that data is valid
on the lower portion of the data bus on a write operation. LW is also decoded for external
bus masters.

2.1.16 Output Enable (OE)

OE is a combination of R/ W high and an active data strobe ( UDS or LDS ). OE is also
decoded for external bus masters.

2.1.17 Reset (

)

The external assertion of this bi-directional, open-drain signal can start a system
initialization sequence by resetting the processor. The processor assertion of RESET
(from executing a RESET instruction) resets all external devices of a system without
affecting the internal state of the processor. The interaction of internal and external

RESET , and the HALT signal is described in paragraph 3.5 Reset Operation.

2.2 CHIP SELECT SIGNALS

These eight three-state signals provide address decodes with programmable base and
range. CS7 –CS4 are only available in chip select mode (AMODE bit =1). CS3–CS0 are
always available.

2.3 DRAM CONTROLLER SIGNALS

The following signals are used to control an external DRAM for the MC68306.

2.3.1 Column Address Strobe (

)

These three-state signals provide column address strobe timing for external DRAM. CAS0
controls data lines D15–D8 and CAS1 controls D7–D0.

2.3.2 Row Address Strobe (

)

These three-state signals provide row address strobe timing for external DRAM. Each
RAS controls a separate bank of DRAM.

2.3.3 DRAM Write Signal (

)

This signal provides write control for external DRAM.

2.4 INTERRUPT CONTROL AND PARALLEL PORT SIGNALS

The following signals are used for interrupt control on the MC68306.

MOTOROLA MC68306 USER'S MANUAL 2-9

2.4.1 Interrupt Request (IRQ7–IRQ1)

IACK7–IACK1

Three input signals (IRQ7, IRQ4, IRQ1) notify the core processor of an interrupt request.
Four additional interrupt request lines (IRQ6, IRQ5, IRQ3, and IRQ2) are shared with
parallel port B pins and may be individually programmed as interrupts.

2.4.2 Interrupt Acknowledge (

)

Three output signals (IACK7, IACK4, IACK1 ) indicate an interrupt acknowledge cycle.
Four additional interrupt acknowledge lines (IACK6, IACK5, IACK3, and IACK2) are
shared with parallel port B pins and may be individually programmed as interrupt
acknowledges.

2.4.3 Port A Signals (PA7–PA0)

These eight pins serve as port A parallel input/output signals.

2.4.4 Port B (PB7–PB0)

These eight pins are shared with IRQ6, IRQ5, IRQ3, IRQ2 and IACK6, IACK5, IACK3,
IACK2, and can be individually programmed to serve as port B parallel input/output

signals.

2.5 CLOCK AND MODE CONTROL SIGNALS

These four pins are used to connect an external crystal to the on-chip oscillator and define
the four multifunction pins.

2.5.1 Crystal Oscillator (EXTAL, XTAL)

These two pins are the connections for an external crystal to the internal oscillator circuit.
If an external oscillator is used, it should be connected to EXTAL, with XTAL left open,
and must drive CMOS levels. A crystal or clock input must be supplied at all times.

2.5.2 Clock Out (CLKOUT)

This output signal is the system clock output and is used as the bus timing reference by
external devices.

2.5.3 Address Mode (AMODE)

This input signal provides mode control for the multi-function chip select pins. When set to
zero, A23–A20 is selected and when set to one, CS7–CS4 is selected. The mode
selection is static: AMODE is latched at the end of any system reset.

2.6 SERIAL MODULE SIGNALS

The following paragraphs describe the signals used by the serial module on the MC68306.

2-10 MC68306 USER'S MANUAL MOTOROLA

2.6.1 Channel A Receiver Serial-Data Input (RxDA)

CTSA

RTSA

CTSB

RTSB

This signal is the receiver serial-data input for channel A. The least-significant bit is
received first. Data on this pin is sampled on the rising edge of the programmed clock
source.

2.6.2 Channel A Transmitter Serial-Data Output (TxDA)

This signal is the transmitter serial-data output for channel A. The least-significant bit is
transmitted first. This output is held high (mark condition) when the transmitter is disabled,
idle, or operating in the local loopback mode. (Mark is high and space is low). Data is
shifted out this pin on the falling edge of the programmed clock source.

2.6.3 Channel B Receiver Serial-Data Input (RxDB)

This signal is the receiver serial-data input for channel B. The least-significant bit is
received first. Data on this pin is sampled on the rising edge of the programmed clock
source.

2.6.4 Channel B Transmitter Serial-Data Output (TxDB)

This signal is the transmitter serial-data output for channel B. The least-significant bit is
transmitted first. This output is held high (mark condition) when the transmitter is disabled,
idle, or operating in the local loopback mode. Data is shifted out of this pin on the falling
edge of the programmed clock source.

2.6.5

This input can be used as the channel A clear-to-send active low input ( CTSA) or general­purpose input (IP0). A change-of-state detector is also associated with this input.

2.6.6

This output can be used as the channel A active low request-to-send (RTSA) output, or a
general-purpose output (OP0). When used as RTSA, it is automatically negated and
reasserted by either the receiver or transmitter.

2.6.7

This input can be used as the channel B clear-to-send active low input ( CTSB) or general ­purpose input. A change-of-state detector is also associated with this input.

2.6.8

This output can be used as a general-purpose output or the channel B active low request­to-send (RTSB) output. When used for this function, it is automatically negated and
reasserted by either the receiver or transmitter.

MOTOROLA MC68306 USER'S MANUAL 2-11

2.6.9 Crystal Oscillator (X1/CLK, X2)

TRST

These two pins are the connections for an external crystal to the internal oscillator circuit.
If an external oscillator is used, it should be connected to X1/CLK, with X2 left floating,
and must drive CMOS levels. A crystal or clock input must be supplied at all times.

2.6.10 IP2

This input can be used as a general-purpose input, the channel B receiver external clock
input (RxCB), or the counter/timer external clock input. When this input is used as the
external clock by the receiver, the received data is sampled on the rising edge of the
clock. A change-of-state detector is also associated with this input.

2.6.11 OP3

This output can be used as a general-purpose output, the open-drain active low counter­ready output, the open-drain timer output, the channel B transmitter 1X-clock output, or
the channel B receiver 1X-clock output.

2.7 JTAG PORT TEST SIGNALS

The following signals are used with the on-chip test logic defined by the IEEE 1149.1
standard. See IEEE 1149.1 Test Access Port for more information on the use of these
signals.

2.7.1 Test Clock (TCK)

This input provides a clock for on-chip test logic defined by the IEEE 1149.1 standard.

2.7.2 Test Mode Select (TMS)

This input controls test mode operations for on-chip test logic defined by the IEEE 1149.1
standard. Connecting TMS to VCC disables the test controller, making all JTAG circuits
transparent to the system.

2.7.3 Test Data In (TDI)

This input is used for serial test instructions and test data for on-chip test logic defined by
the IEEE 1149.1 standard.

2.7.4 Test Data Out (TDO)

This output is used for serial test instructions and test data for on-chip test logic defined by
the IEEE 1149.1 standard.

2.7.5 Test Reset (

)

This input is the master reset for on-chip test logic defined by the IEEE 1149.1 standard.

2-12 MC68306 USER'S MANUAL MOTOROLA

SECTION 3
68000 BUS OPERATION DESCRIPTION

This section describes control signal and bus operation during data transfer operations,
bus arbitration, bus error and halt conditions, and reset operation.

NOTE

The terms assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of
"active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true,
independently of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.

3.1 DATA TRANSFER OPERATIONS

Transfer of data between devices involves the following signals:

1. Address bus A1 through A31

2. Data bus D0 through D7 and/or D8 through D15

3. Control signals

The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master must deskew all signals it issues
at both the start and end of a bus cycle. In addition, the bus master must deskew the
acknowledge and data signals from the slave device.

The following paragraphs describe the read, write, read-modify-write, and CPU space
cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor
communications. A CPU space cycle is a special processor cycle.

3.1.1 Read Cycle

During a read cycle, the processor receives either one or two bytes of data from the
memory or from a peripheral device. If the instruction specifies a word or long-word
operation, the processor reads both upper and lower bytes simultaneously by asserting
both upper and lower data strobes. A long-word read is accomplished by two consecutive
word reads. When the instruction specifies byte operation, the processor uses the internal
A0 bit to determine which byte to read and issues the appropriate data strobe. When A0 is
zero, the upper data strobe is issued; when A0 is one, the lower data strobe is issued.
When the data is received, the processor internally positions the byte appropriately.

MOTOROLA MC68306 USER'S MANUAL 3-1

The word read cycle flowchart is shown in Figure 3-1. The byte read cycle flowchart is
shown in Figure 3-2. The read and write cycle timing is shown in Figure 3-3. Figure 3-4
shows the word and byte read cycle timing diagram.

BUS MASTER

ADDRESS THE DEVICE

1) SET R/W TO READ

2) PLACE FUNCTION CODE ON FC2–FC0

3) PLACE ADDRESS ON ADDRESS BUS

4) ASSERT ADDRESS STROBE (AS)

5) ASSERT UPPER DATA STROBE (UDS)
AND LOWER DATA STROBE (LDS)

ACQUIRE THE DATA

1) LATCH DATA

2) NEGATE UDS AND LDS

3) NEGATE AS

START NEXT CYCLE

Figure 3-1. Word Read Cycle Flowchart

SLAVE

OUTPUT THE DATA

1) DECODE ADDRESS

2) PLACE DATA ON D15–D0

3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

TERMINATE THE CYCLE

1) REMOVE DATA FROM D15–D0

2) NEGATE DTACK

BUS MASTER

ADDRESS THE DEVICE

1) SET R/W TO READ

2) PLACE FUNCTION CODE ON FC2–FC0

3) PLACE ADDRESS ON ADDRESS BUS

4) ASSERT ADDRESS STROBE (AS)

5) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
(BASED ON A0)

ACQUIRE THE DATA

1) LATCH DATA

2) NEGATE UDS AND LDS

3) NEGATE AS

START NEXT CYCLE

1) DECODE ADDRESS

2) PLACE DATA ON D7–D0 OR D15–D8
(BASED ON UDS OR LDS)

3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

1) REMOVE DATA FROM D7–D0
OR D15–D8

2) NEGATE DTACK

SLAVE

OUTPUT THE DATA

TERMINATE THE CYCLE

Figure 3-2. Byte Read Cycle Flowchart

3-2 MC68306 USER'S MANUAL MOTOROLA

CLK

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7

FC2–FC0

A31–A1

AS

UDS

LDS

R/W

DTACK

D15–D8

D7–D0

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w w w w S5 S6 S7

READ WRITE 2 WAIT STATE READ

Figure 3-3. Read and Write Cycle Timing Diagram

CLK

FC2–FC0

A31–A1

A0 *

AS

UDS

LDS

R/W

DTACK

D15–D8

D7–D0

*Internal Signal Only

READ WRITE

READ

Figure 3-4. Word and Byte Read Cycle Timing Diagram

MOTOROLA MC68306 USER'S MANUAL 3-3

A bus cycle consists of eight states. The various signals are asserted during specific
states of a read cycle as follows:

STATE 0 The read cycle starts in state 0 (S0). The processor places valid function

codes on FC0–FC2, a valid address on the bus, and drives R/W high to

identify a read cycle.
STATE 1 During state 1 (S1), no bus signals are altered.
STATE 2 On the rising edge of state 2 (S2), the processor asserts AS and

UDS/LDS .
STATE 3 During state 3 (S3), no bus signals are altered.
STATE 4 During state 4 (S4), the processor waits for a cycle termination signal

(DTACK or BERR ). If neither termination signal is asserted before the falling

edge at the end of S4, the processor inserts wait states (full clock cycles)

until either DTACK or BERR is asserted.

Case 1: DTACK received, with or without BERR .
STATE 5 During state 5 (S5), no bus signals are altered.
STATE 6 Sometime between state 2 (S2) and state 6 (S6), data from the device is

driven onto the data bus.
STATE 7 On the falling edge of the clock entering state 7 (S7), the processor latches

data from the addressed device and negates AS and UDS , LDS . The device

negates DTACK or BERR at this time.

Case 2: BERR received without DTACK .
STATE 5 During state 5 (S5), no bus signals are altered.
STATE 6 During state 6 (S6), no bus signals are altered.
STATE 7 During state 7 (S7), no bus signals are altered.
STATE 8 During state 8 (S8), no bus signals are altered.
STATE 9 AS and UDS/LDS negated. Slave negates BERR.

3.1.2 Write Cycle

During a write cycle, the processor sends bytes of data to the memory or peripheral
device. If the instruction specifies a word or long-word operation, the processor issues
both UDS and LDS and writes both bytes. A long-word write is accomplished by two
consecutive word writes. When the instruction specifies a byte operation, the processor
uses the internal A0 bit to determine which byte to write and issues the appropriate data

3-4 MC68306 USER'S MANUAL MOTOROLA

strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is

BUS MASTER

asserted.
The word write cycle flowchart is shown in Figure 3-5. The byte write cycle flowchart is

shown in Figure 3-6. The word and byte write cycle timing is shown in Figure 3-7.

ADDRESS THE DEVICE

1) PLACE FUNCTION CODE ON FC2–FC0

2) PLACE ADDRESS ON ADDRESS BUS

3) ASSERT ADDRESS STROBE (AS)

4) SET R/W TO WRITE

5) PLACE DATA ON D15–D0

6) ASSERT UPPER DATA STROBE (UDS)
AND LOWER DATA STROBE (LDS)

TERMINATE OUTPUT TRANSFER

1) NEGATE UDS AND LDS

2) NEGATE AS

3) REMOVE DATA FROM D15–D0

4) SET R/W TO READ

START NEXT CYCLE

Figure 3-5. Word Write Cycle Flowchart

SLAVE

INPUT THE DATA

1) DECODE ADDRESS

2) LATCH DATA ON D15–D0

3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

TERMINATE THE CYCLE

1) NEGATE DTACK

MOTOROLA MC68306 USER'S MANUAL 3-5

BUS MASTER

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7

ADDRESS THE DEVICE

1) PLACE FUNCTION CODE ON FC2–FC0

2) PLACE ADDRESS ON ADDRESS BUS

3) ASSERT ADDRESS STROBE (AS)

4) SET R/W TO WRITE

5) PLACE DATA ON D0–D7 OR D15–D8
(ACCORDING TO INTERNAL A0)

6) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
(BASED ON INTERNAL A0)

TERMINATE OUTPUT TRANSFER

1) NEGATE UDS AND LDS

2) NEGATE AS

3) REMOVE DATA FROM D7-D0 OR
D15-D8

4) SET R/W TO READ

START NEXT CYCLE

Figure 3-6. Byte Write Cycle Flowchart

SLAVE

INPUT THE DATA

1) DECODE ADDRESS

2) LATCH DATA ON D7–D0 IF LDS IS
ASSERTED. LATCH DATA ON D15–D8
IF UDS IS ASSERTED

3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

TERMINATE THE CYCLE

1) NEGATE DTACK

CLK

FC2–FC0

A31–A1

*

A0

AS

UDS

LDS

R/W

DTACK

D15–D8

D7–D0

*INTERNAL SIGNAL ONLY

WORD WRITE ODD BYTE WRITE

EVEN BYTE WRITE

Figure 3-7. Word and Byte Write Cycle Timing Diagram

3-6 MC68306 USER'S MANUAL MOTOROLA

The descriptions of the eight states of a write cycle are as follows:
STATE 0 The write cycle starts in S0. The processor places valid function codes on

FC2–FC0, a valid address on the address bus, and drives R/W high (if

a preceding write cycle has left R/W low).
STATE 1 During S1, no bus signals are altered.
STATE 2 On the rising edge of S2, the processor asserts AS and drives R/W low.
STATE 3 During S3, the data bus is driven out of the high-impedance state as the

data to be written is placed on the bus.
STATE 4 At the rising edge of S4, the processor asserts UDS and/or LDS;. The

processor waits for a cycle termination signal (DTACK or BERR ). If

neither termination signal is asserted before the falling edge at the end of

S4, the processor inserts wait states (full clock cycles) until either DTACK or

BERR is asserted.

Case 1: DTACK received, with or without BERR .
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered.
STATE 7 On the falling edge of the clock entering S7, the processor negates AS,

UDS , and/or LDS. As the clock rises at the end of S7, the processor places

the data bus in the high-impedance state, and drives R/W

high. The device negates DTACK or BERR at this time.

Case 2: BERR received without DTACK .
STATE 5 During state 5 (S5), no bus signals are altered.
STATE 6 During state 6 (S6), no bus signals are altered.
STATE 7 During state 7 (S7), no bus signals are altered.
STATE 8 During state 8 (S8), no bus signals are altered.
STATE 9 AS and UDS/LDS negated. Slave negates BERR. At the end of S9, three-

state data and drive R/W high.

3.1.3 Read-Modify-Write Cycle

The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe (AS ) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS )
instruction uses this cycle to provide a signaling capability without deadlock between
processors in a multiprocessing environment. The TAS instruction (the only instruction

MOTOROLA MC68306 USER'S MANUAL 3-7

that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write
cycles are byte operations. The read-modify-write flowchart is shown in Figure 3-8 and the
timing diagram is shown in Figure 3-9.

BUS MASTER

ADDRESS THE DEVICE

1) SET R/W TO READ

2) PLACE FUNCTION CODE ON FC2–FC0

3) PLACE ADDRESS ON ADDRESS BUS

4) ASSERT ADDRESS STROBE (AS)

5) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)

1) DECODE ADDRESS

2) PLACE DATA ON D7–D0 OR D15–D0

3) ASSERT DATA TRANSFER

ACQUIRE THE DATA

1) LATCH DATA

1) NEGATE UDS AND LDS

2) START DATA MODIFICATION

START OUTPUT TRANSFER

1) SET R/W TO WRITE

2) PLACE DATA ON D7–D0 OR D15–D8

3) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)

TERMINATE OUTPUT TRANSFER

1) NEGATE UDS OR LDS

2) NEGATE AS

3) REMOVE DATA FROM D7–D0 OR
D15–D8

4) SET R/W TO READ

ACKNOWLEDGE (DTACK)

1) REMOVE DATA FROM D7–D0
OR D15–D8

2) NEGATE DTACK

1) STORE DATA ON D7–D0 OR D15–D8

2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)

1) NEGATE DTACK

SLAVE

OUTPUT THE DATA

TERMINATE THE CYCLE

INPUT THE DATA

TERMINATE THE CYCLE

START NEXT CYCLE

Figure 3-8. Read-Modify-Write Cycle Flowchart

3-8 MC68306 USER'S MANUAL MOTOROLA

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19

CLK

A31–A1

AS

UDS OR LDS

R/W

DTACK

D15–D8 OR
D7–D0

FC2–FC0

INDIVISIBLE CYCLE

Figure 3-9. Read-Modify-Write Cycle Timing Diagram

The descriptions of the read-modify-write cycle states are as follows:
STATE 0 The read cycle starts in S0. The processor places valid function codes on

FC2–FC0, a valid address on the address bus, and drives R/W high to

identify a read cycle.
STATE 1 During S1, no bus signals are altered.
STATE 2 On the rising edge of S2, the processor asserts AS and UDS /LDS.
STATE 3 During S3, no bus signals are altered.
STATE 4 During S4, the processor waits for a cycle termination signal ( DTACK or

BERR ). If neither termination signal is asserted before the falling

edge at the end of S4, the processor inserts wait states (full clock cycles)

until either DTACK or BERR is asserted.

Case R1: DTACK only.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, data from the device are driven onto the data bus.
STATE 7 On the falling edge of the clock entering S7, the processor accepts data from

the device and negates UDS /LDS . The device negates DTACK at this

time.
STATES

8–11 The bus signals are unaltered during S8–S11, during which the arithmetic

logic unit makes appropriate modifications to the data.

MOTOROLA MC68306 USER'S MANUAL 3-9

STATE 12 The write portion of the cycle starts in S12. The valid function codes on

FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
STATE 13 During S13, no bus signals are altered.
STATE 14 On the rising edge of S14, the processor drives R/W low.
STATE 15 During S15, the data bus is driven out of the high-impedance state as the

data to be written are placed on the bus.
STATE 16 At the rising edge of S16, the processor asserts UDS /LDS . The processor

waits for DTACK or BERR . If neither termination signal is asserted

before the falling edge at the close of S16, the processor inserts wait states

(full clock cycles) until either DTACK or BERR is asserted.

Case W1: DTACK with or without BERR .
STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 On the falling edge of the clock entering S19, the processor negates AS and

UDS /LDS . As the clock rises at the end of S19, the processor

places the data bus in the high-impedance state, and drives

R/W high. The device negates DTACK or BERR at this time.

Case R2: DTACK and BERR on read.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered, and data from the device is ignored.
STATE 7 AS and UDS/LDS are negated. The cycle terminates without the write

portion.

Case R3: BERR only on read.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered..
STATE 7 During S7, no bus signals are altered.
STATE 8 During S8, no bus signals are altered.
STATE 9 AS and UDS/LDS are negated. The cycle terminates without the write

portion.

Case W2: BERR only on write.

3-10 MC68306 USER'S MANUAL MOTOROLA

STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 During S19, no bus signals are altered.
STATE 20 During S20. no bus signals are altered.
STATE 21 The processor negates AS and UDS /LDS.

3.1.4 CPU Space Cycle

A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. In the 68EC000 core, CPU space is used only for interrupt acknowledge cycles.
Figure 3-10 shows the encoding of an interrupt acknowledge cycle.

310

LEVEL 1

INTERRUPT

ACKNOWLEDGE

31

1111111111111111111111111111111

Figure 3-10. Interrupt Acknowledge Cycle

The interrupt acknowledge cycle places the level of the interrupt being acknowledged on
address bits A3–A1 and drives all other address lines high. The interrupt acknowledge
cycle reads a vector number when the device places a vector number on the data bus.

The timing diagram for an interrupt acknowledge cycle is shown in Figure 3-11.

MOTOROLA MC68306 USER'S MANUAL 3-11

IPL2–IPL0 SAMPLED

IPL2–IPL0 VALID INTERNALLY

IPL2–IPL0 TRANSITION

CLK

FC2–FC0

A23–A4

A3–A1

AS

UDS*

LDS

IACK

R/W

DTACK

D15–D8

S0 S1 S2 S3 S4 S5 S6 S7 S0S1S2 S3 S4 S5

SW

SW

S6 S7 S0

S1 S2 S3 S4 S5 S6

D7–D0

IPL2–IPL0

LAST BUS CYCLE OF INSTRUCTION

(READ OR WRITE)

*

Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not
recognize anything on data lines D8 through D15 at this time.

STACK

PCL

(SSP)

IACK CYCLE

(VECTOR NUMBER

ACQUISITION)

STACK AND

VECTOR

FETCH

Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram

3.2 BUS ARBITRATION

Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:

1. Asserting a bus mastership request

2. Receiving a grant indicating that the bus is available at the end of the current cycle

3. Acknowledging that mastership has been assumed

Figure 3-12 is a flowchart showing the bus arbitration cycle of the EC000 core. Figure 3­13 is a timing diagram of the bus arbitration cycle charted in Figure 3-12. This technique
allows processing of bus requests during data transfer cycles.

3-12 MC68306 USER'S MANUAL MOTOROLA

There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration . The EC000

REQUESTING DEVICE

PROCESSOR

core can do either 2-wire or 3-wire bus arbitration. Figures 3-12 and 3-14 show 3-wire bus
arbitration and Figures 3-13 and 5-15 show 2-wire bus arbitration. BGACK must be pulled
high for 2-wire bus arbitration.

REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

GRANT BUS ARBITRATION

1) ASSERT BUS GRANT (BG)

ACKNOWLEDGE BUS MASTERSHIP

1) EXTERNAL ARBITRATION DETER­ MINES NEXT BUS MASTER

2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE

3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK)

TERMINATE ARBITRATION

1) NEGATE BG (AND WAIT FOR BGACK
TO BE NEGATED)

2) IF BR REMAINS ASSERTED AFTER
BGACK ASSERTED, RE-ASSERT BG.

TO BECOME NEW MASTER

4) BUS MASTER NEGATES BR

OPERATE AS BUS MASTER

1) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING

TO THE SAME RULES THE PRO­ CESSOR USES

REARBITRATE OR RESUME

PROCESSOR OPERATION

RELEASE BUS MASTERSHIP

1) NEGATE BGACK

Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart

MOTOROLA MC68306 USER'S MANUAL 3-13

GRANT BUS ARBITRATION

PROCESSOR

1) ASSERT BUS GRANT (BG)

REQUESTING DEVICE

REQUEST THE BUS

1) ASSERT BUS REQUEST (BR)

OPERATE AS BUS MASTER

1) EXTERNAL ARBITRATION DETER­ MINES NEXT BUS MASTER

2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE

ACKNOWLEDGE RELEASE OF

BUS MASTERSHIP

1) NEGATE BUS GRANT (BG)

RELEASE BUS MASTERSHIP

1) NEGATE BUS REQUEST (BR)

REARBITRATE OR RESUME

PROCESSOR OPERATION

Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart

3-14 MC68306 USER'S MANUAL MOTOROLA

CLK

S0S6S2

S0 S2 S4 S6

FC2–FC0

A31–A1

AS

LDS/ UDS

R/W

DTACK

D15–D0

BR

BG

BGACK

PROCESSOR DMA DEVICE PROCESSOR DMA DEVICE

Figure 3-14. Three-Wire Bus Arbitration Timing Diagram

S4 S0 S2 S4 S6

S0 S2 S4 S6

CLK

FC2–FC0

A19–A0

AS

DS

R/W

DTACK

D7–D0

BR

BG

PROCESSOR

DMA DEVICE PROCESSOR DMA DEVICE

Figure 3-15. Two-Wire Bus Arbitration Timing Diagram

MOTOROLA MC68306 USER'S MANUAL 3-15

The timing diagram in Figure 3-14 shows that the bus request is negated at the time that
an acknowledge is asserted. This type of operation applies to a system consisting of a
processor and one other device capable of becoming bus master. In systems having
several devices that can be bus masters, bus request lines from these devices can be
wire-ORed at the processor, and more than one bus request signal could occur.

The bus grant signal is negated a few clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus requests are pending, the processor reasserts bus
grant for another request a few clock cycles after bus grant (for the previous request) is
negated. In response to this additional assertion of bus grant, external arbitration circuitry
selects the next bus master before the current bus master has completed the bus activity.

The timing diagram in Figure 3-15 also applies to a system consisting of a processor and
one other device capable of becoming bus master. Since the 2-wire bus arbitration
scheme does not use a bus grant acknowledge signal, the external master must continue
to assert BR until it has completed its bus activity. The processor negates bus grant when
BR is negated.

3.2.1 Requesting the Bus

External devices capable of becoming bus masters assert BR to request the bus. This
signal can be wire-ORed (not necessarily constructed from open-collector devices) from
any of the devices in the system that can become bus master. The processor, which is at
a lower bus priority level than the external devices, relinquishes the bus after it completes
the current bus cycle.

3.2.2 Receiving the Bus Grant

The processor asserts BG as soon as possible. Normally, this process immediately
follows internal synchronization, except when the processor has made an internal decision
to execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is
delayed until AS is asserted to indicate to external devices that a bus cycle is in progress.

BG can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.

3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only)

Upon receiving BG , the requesting device waits until AS, DTACK, and BGACK are
negated before asserting BGACK. The negation of AS indicates that the previous bus
master has completed its cycle. (No device is allowed to assume bus mastership while AS
is asserted.) The negation of BGACK indicates that the previous master has released the
bus. The negation of DTACK indicates that the previous slave has terminated the
connection to the previous master. (In some applications, DTACK might not be included in
this function; general-purpose devices would be connected using AS only.) When BGACK
is asserted, the asserting device is bus master until it negates BGACK . BGACK should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACK .

3-16 MC68306 USER'S MANUAL MOTOROLA

The bus request from the granted device should be negated after BGACK is asserted. If

CLK

BR (EXTERNAL)

BR (iNTERNAL)

47

INTERNAL SIGNAL VALID

EXTERNAL SIGNAL SAMPLED

another bus request is pending, BG is reasserted within a few clocks, as described in 3.3
Bus Arbitration Control. The processor does not perform any external bus cycles before

reasserting BG .

3.3 BUS ARBITRATION CONTROL

All asynchronous bus arbitration signals to the processor are synchronized before being
used internally. As shown in Figure 3-16, synchronization requires a maximum of one and
a half cycles of the system clock. The input asynchronous signal is sampled on the falling
edge of the clock and is valid internally after the next rising edge.

This synchronization scheme is used for all other asynchronous inputs also: RESET,
HALT, DTACK, BERR, IPL2–IPL0.

Bus arbitration control is implemented with a finite state machine (see Figure 3-17). In
Figure 3-17, input signals R and A are the internally synchronized versions of BR and
BGACK. The BG output is shown as G, and the internal three-state control signal is shown
as T. If T is true, the address, data, and control buses are placed in the high-impedance
state when AS is negated. All signals are shown in positive logic (active high), regardless
of their true active voltage level. State changes (valid outputs) occur on the next rising
edge of the clock after the internal signal is valid.

A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in
Figure 3-18. The bus arbitration timing while the bus is inactive (e.g., the processor is
performing internal operations for a multiply instruction) is shown in Figure 3-19.

MOTOROLA MC68306 USER'S MANUAL 3-17

Figure 3-16. External Asynchronous Signal Synchronization

When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.

RA

RA

XX

GT

GT

RA

XA

RA

RA

1

GT

RA

GT

RA

RA

GT

RA

(a) 3-Wire Bus Arbitration

R

RA

R+A

XA

1

RA

GT

RX

GT

XX

GT

STATE 0

R

GT

STATE 3

R

GT

STATE 4

X

Notes:

1. State machine will not change if
the bus is S0 or S1. Refer to

BUS ARBITRATION CONTROL.

2. The address bus will be placed in
the high-impedance state if T is

asserted and AS is negated.

5.2.3.

GT

STATE 1

X

GT

STATE 2

R

R = Bus Request Internal
A = Bus Grant Acknowledge Internal

G = Bus Grant

T = Three-state Control to Bus Control Logic
X = Don't Care

R

R

(b) 2-Wire Bus Arbitration

Figure 3-17. Bus Arbitration Unit State Diagrams

3-18 MC68306 USER'S MANUAL MOTOROLA

Figures 3-18, 3-19, and 3-20 apply to processors using 3-wire bus arbitration. Figures

BUS THREE-STATED

3-21, 3-22, and 3-23 apply to processors using 2-wire bus arbitration.

CLK

BR

BG

BGACK

FC2–FC0

A31–A1

AS

UDS

LDS

R/W

BG ASSERTED
BR VALID INTERNAL

BR SAMPLED
BR ASSERTED

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1

BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE

BGACK NEGATED INTERNAL
BGACK SAMPLED
BGACK NEGATED

DTACK

D15–D0

PROCESSOR

ALTERNATE BUS MASTER PROCESSOR

Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active

MOTOROLA MC68306 USER'S MANUAL 3-19

CLK

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE

BR

BG

BGACK

FC2–FC0

A31–A1

AS

UDS

LDS

R/W

BGACK NEGATED
BG ASSERTED AND BUS THREE STATED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4

DTACK

D15–D0

PROCESSOR

BUS

INACTIVE

ALTERNATE BUS MASTER

PROCESSOR

Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive

3-20 MC68306 USER'S MANUAL MOTOROLA

CLK

BR

BG

BGACK

FC2–FC0

A31–A1

AS

UDS

LDS

BUS THREE-STATED
BG ASSERTED

BR VALID INTERNAL
BR SAMPLED

BR ASSERTED

S0 S2 S4 S6 S0 S2 S4 S6 S0

BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE

BGACK NEGATED INTERNAL
BGACK SAMPLED

BGACK NEGATED

R/W

DTACK

D15–D0

PROCESSOR

ALTERNATE BUS MASTER PROCESSOR

Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case

MOTOROLA MC68306 USER'S MANUAL 3-21

BUS THREE-STATED

BG ASSERTED
BR VALID INTERNAL

BR SAMPLED
BR ASSERTED

BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE

BR NEGATED INTERNAL
BR SAMPLED
BR NEGATED

CLK

BR

BG

BGACK

FC2–FC0

A31–A1

AS

UDS

LDS

R/W

DTACK

D15–D0

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1

PROCESSOR

ALTERNATE BUS MASTER PROCESSOR

Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active

3-22 MC68306 USER'S MANUAL MOTOROLA

BR NEGATED

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE

BG ASSERTED AND BUS THREE STATED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED

CLK

S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4

BR

BG

BGACK

FC2–FC0

A31–A1

AS

UDS

LDS

R/W

DTACK

D15–D0

PROCESSOR

BUS

INACTIVE

ALTERNATE BUS MASTER

PROCESSOR

Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive

MOTOROLA MC68306 USER'S MANUAL 3-23

CLK

BR

BG

BGACK

FC2–FC0

A31–A1

UDS

LDS

BUS THREE-STATED
BG ASSERTED

BR VALID INTERNAL
BR SAMPLED

BR ASSERTED

AS

BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE

BR NEGATED INTERNAL
BR SAMPLED

BR NEGATED

S0 S2 S4 S6 S0 S2 S4 S6 S0

R/W

DTACK

D15–D0

PROCESSOR

ALTERNATE BUS MASTER PROCESSOR

Figure 3-23. Two-Wire Bus Arbitration Timing Diagram—Special Case

3.4 BUS ERROR AND HALT OPERATION

In a bus architecture that requires a handshake from an external device, such as the
asynchronous bus used in the M68000 Family, the handshake may not always occur. A
bus error input is provided to terminate a bus cycle in error when the expected signal is
not asserted. Different systems and different devices within the same system require
different maximum-response times. External circuitry can be provided to assert the bus
error signal after the appropriate delay following the assertion of address strobe.

3.4.1 Bus Error Operation

A bus error is recognized when BERR is asserted, HALT is negated, and DTACK is not
asserted before BERR (or not at all).

When the bus error condition is recognized, the current bus cycle is terminated in S7
(DTACK and BERR together) or S9 (BERR alone) for a read cycle, a write cycle, or the
read portion of a read-modify-write cycle. For the write portion of a read-modify-write
cycle, the current bus cycle is terminated in S19 (DTACK and BERR together) or S21

3-24 MC68306 USER'S MANUAL MOTOROLA

(BERR alone). As long as BERR remains asserted, the data bus is in the high-impedance
state. Figure 3-24 shows the timing for the normal bus error.

CLK

FC2–FC0

A31–A1

AS

LDS/UDS

R/W

DTACK

D15–D0

BERR

HALT

S0 S2 S4

INITIATE

READ

Figure 3-24. Bus Error Timing Diagram

ww

RESPONSE

FAILURE

w

w

S6

BUS ERROR
DETECTION

S8

INITIATE BUS

ERROR STACKING

After the aborted bus cycle is terminated and BERR is negated, the processor enters
exception processing for the bus error exception. During the exception processing
sequence, the following information is placed on the supervisor stack:

1. Status register

2. Program counter (two words, which may be up to five words past the instruction
being executed)

3. Error information

The first two items are identical to the information stacked by any other exception. The
EC000 core stacks bus error information to help determine and to correct the error.

After the processor has placed the required information on the stack, the bus error
exception vector is read from vector table entry 2 (offset $08) and placed in the program
counter. The processor resumes execution at the address in the vector, which is the first
instruction in the bus error handler routine.

3.4.2 Retrying the Bus Cycle

The assertion of the bus error signal during a bus cycle in which HALT is also asserted by
an external device initiates a retry operation. Figure 3-25 is a timing diagram of the retry
operation.

MOTOROLA MC68306 USER'S MANUAL 3-25

S0S2S4S6CLK

FC2-FC0

A23–A1

S8S0S2S4S6ASLDS/UDS

R/W

DTACK

D15–D0

BERR

HALT

1 CLOCK PERIOD

≥

READ

HALT

RETRY

HALT

Figure 3-25. Retry Bus Cycle Timing Diagram

The processor terminates the bus cycle, and remains in this state until HALT is negated.
Then the processor retries the preceding cycle using the same function codes, address,
and data (for a write operation). BERR should be negated at least one clock cycle before
HALT is negated.

NOTE

To guarantee that the entire read-modify-write cycle runs
correctly and that the write portion of the operation is
performed without negating the address strobe, the processor
does not retry a read-modify-write cycle. When BERR occurs
during a read-modify-write operation, a bus error operation is
performed whether or not HALT is asserted.

3.4.3 Halt Operation

performs a halt/run/single-step operation. When HALT is asserted by an external

device, the processor halts and remains halted as long as the signal remains asserted, as
shown in Figure 3-26.

While the processor is halted, bus arbitration is performed as usual. Should a bus error
occur while HALT is asserted, the processor performs the retry operation previously
described.

NOTE

If a RESET instruction is executed while HALT is asserted, the
CPU will be reset.

3-26 MC68306 USER'S MANUAL MOTOROLA

S0 S2 S4 S6

CLK

FC2–FC0

A31–A1

AS

LDS/UDS

R/W

DTACK

D15–D0

HALT

READ HALT READ

S0 S2 S4 S6

Figure 3-26. Halt Operation Timing Diagram

The single-step mode is derived from correctly timed transitions of HALT. HALT is negated
to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the
cycle completes. The single-step mode proceeds through a program one bus cycle at a
time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.

3.4.4 Double Bus Fault

When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.

A retry operation does not initiate exception processing; a bus error during a retry
operation does not cause a double bus fault. The processor can continue to retry a bus
cycle indefinitely if external hardware requests.

A double bus fault occurs during a reset operation when a bus error occurs while the
processor is reading the vector table (before the first instruction is executed). The reset
operation is described in the following paragraph.

3.5 RESET OPERATION

RESET is asserted externally for the initial processor reset. Subsequently, the signal can
be asserted either externally or internally (executing a RESET instruction).

MOTOROLA MC68306 USER'S MANUAL 3-27

After the processor is reset, it reads the reset vector table entry (address $00000) and

DTACK, BERR

HALT

Ñ

loads the contents into the supervisor stack pointer (SSP). Next, the processor loads the
contents of address $00004 (vector table entry 1) into the program counter. Then the
processor initializes the interrupt level in the status register to a value of seven. No other
register is affected by the reset sequence. Figure 3-27 shows the timing of the reset
operation.

CLK

+ 5 VOLTS

V

CC

RESET

HALT

T 100 MILLISECONDS

≥

BUS CYCLES

NOTES:

1. Internal start-up time

2. SSP high read in here

3. SSP low read in here

<

T 4 CLOCKS

4. PC High read in here

5. PC Low read in here

6. First instruction fetched here

All Control Signals Inactive.

Data Bus in Read Mode:

1

23456

Bus State Unknown:

Figure 3-27. Reset Operation Timing Diagram

The active-low RESET signal is asserted by the EC000 core when a RESET instruction is
executed. This signal should reset all external devices (the EC000 core itself is not
affected). The processor drives RESET for 124 clock periods. The RESET signal is
asserted by an external source to reset the EC000 core. RESET by itself will reset the
EC000 core unless the processor is executing a RESET instruction. To guarantee a reset
of the core, RESET must be asserted for at least 132 clocks (i.e., longer than the
maximum duration of the RESET instruction), or RESET and HALT must be asserted
together for at least 10 clocks.

3.6 THE RELATIONSHIP OF

, AND

To properly control termination of a bus cycle for a retry or a bus error condition, DTACK,
BERR , and HALT should be asserted and negated on the rising edge of the processor

clock. This relationship assures that when two signals are asserted simultaneously, the
required setup time (specification #47, AC Electrical Specifications

Cycles ) for both of them is met during the same bus state. External circuitry should be

Read and Write

designed to incorporate this precaution. A related specification, #48, can be ignored when
DTACK, BERR , and HALT are asserted and negated on the rising edge of the processor
clock.

3-28 MC68306 USER'S MANUAL MOTOROLA

The possible bus cycle terminations can be summarized as follows (case numbers refer to

DTACK, BERR

HALT

Table 3-1).

Normal Termination: DTACK is asserted. BERR and HALT remain negated (case 1).
Halt Termination: HALT is asserted coincident with or preceding DTACK, and

BERR remains negated (case 2).

Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding

DTACK (case 3).

Retry Termination: HALT and BERR asserted in lieu of, coincident with, or before

DTACK (case 5).

Table 3-1 shows the details of the resulting bus cycle terminations for various
combinations of signal sequences.

Table 3-1.

Case

No.

Control

Signal

1 DTACK

BERR

HALT

2 DTACK

BERR

HALT

3 DTACK

BERR

HALT

4 DTACK

BERR

HALT

5 DTACK

BERR

HALT

6 DTACK

BERR

HALT

, and

Asserted on Rising

Edge of State EC000 Core Results

N N+2

A
NA
NA

A
NA

A/S

X

A
NA

A
NA
NA

X

A

A/S

A
NA
NA

S

NA

X
S

NA

S
X

S

NA

S
A

NA

X
S
S

S
A
A

Normal cycle terminate and continue.

Normal cycle terminate and halt. Continue
when HALT negated.

Terminate and take bus error trap.

Normal cycle terminate and continue.

Terminate and retry when HALT removed.

Normal cycle terminate and continue.

Assertion Results

LEGEND:

N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state

NA — Signal not asserted in this bus state

X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state

NOTE: All operations are subject to relevant setup and hold times.

MOTOROLA MC68306 USER'S MANUAL 3-29

The negation of BERR and HALT under several conditions is shown in Table 3-2. (DTACK

BERR

HALT

is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).

EXAMPLE A:

A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).

EXAMPLE B:

A system uses error detection on random-access memory (RAM) contents. The system
designer may:

1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
simultaneously to retry the error cycle (case 5).

2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
time as DTACK (case 3).

Table 3-2.

Conditions of

Termination in

Table 4-4

Bus Error BERR

Rerun BERR

Rerun BERR

Normal BERR

Normal BERR

• = Signal is negated in this bus state.

Control Signal N N+2 Results—Next Cycle

HALT

HALT

HALT

HALT

HALT •or

and

Negated on Rising

Edge of State

•

•

•

•

•

•

•or•

or
or

or • Illegal sequence; usually traps to vector number 0.

Negation Results

•

Takes bus error trap.

•

Reruns the bus cycle.

•
May lengthen next cycle.

•

If next cycle is started, it will be terminated as a bus

none

error.

3.7 ASYNCHRONOUS OPERATION

To achieve clock frequency independence at a system level, the bus can be operated in
an asynchronous manner. Asynchronous bus operation uses the bus handshake signals
to control the transfer of data. The handshake signals are AS , UDS, LDS , DTACK, BERR ,
and HALT. AS indicates the start of the bus cycle, and UDS and LDS signal valid data for
a write cycle. After placing the requested data on the data bus (read cycle) or latching the
data (write cycle), the slave device (memory or peripheral) asserts DTACK to terminate
the bus cycle. If no device responds or if the access is invalid, external control logic
asserts BERR , or BERR and HALT, to abort or retry the cycle. Figure 3-28 shows the use
of the bus handshake signals in a fully asynchronous read cycle. Figure 3-29 shows a fully
asynchronous write cycle.

3-30 MC68306 USER'S MANUAL MOTOROLA

AS

R/W

DTACK

UDS/LDS

DATA

ADDR

Figure 3-28 Fully Asynchronous Read Cycle

ADDRASR/W

UDS/LDS

DATA

DTACK

Figure 3-29. Fully Asynchronous Write Cycle

In the asynchronous mode, the accessed device operates independently of the frequency
and phase of the system clock. For example, the MC68681 dual universal asynchronous
receiver/transmitter (DUART) does not require any clock-related information from the bus
master during a bus transfer. Asynchronous devices are designed to operate correctly
with processors at any clock frequency when relevant timing requirements are observed.

A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5
MHz), but without a defined phase relationship to the system clock. This mode of
operation is pseudo-asynchronous; it increases performance by observing timing
parameters related to the system clock frequency without being completely synchronous
with that clock. A memory array designed to operate with a particular frequency processor
but not driven by the processor clock is a common example of a pseudo-asynchronous
device.

The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. With the system clock frequency
known, the slave device can be designed to decode the address bus before recognizing
an address strobe. Parameter #11 (refer to AC Electrical Specifications—Read and
Write Cycles) specifies the minimum time before address strobe during which the
address is valid.

MOTOROLA MC68306 USER'S MANUAL 3-31

In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a

ADDRASR/W

UDS/LDS

DATA

DTACK

1117A3128

29

read cycle before the data from a slave device is valid. The length of time that DTACK
may precede data is specified as parameter #31. This parameter must be met to ensure
the validity of the data latched into the processor. No maximum time is specified from the
assertion of AS to the assertion of DTACK. During this unlimited time, the processor
inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 3-30
shows the important timing parameters for a pseudo-asynchronous read cycle.

Figure 3-30. Pseudo-Asynchronous Read Cycle

During a write cycle, after the processor asserts AS but before driving the data bus, the
processor drives R/W low. Parameter #55 specifies the minimum time between the
transition of R/W and the driving of the data bus, which is effectively the maximum turnoff
time for any device driving the data bus.

After the processor places valid data on the bus, it asserts the data strobe signal(s). A
data setup time, similar to the address setup time previously discussed, can be used to
improve performance. Parameter #26 is the minimum time a slave device can accept valid
data before recognizing a data strobe. The slave device asserts DTACK after it accepts
the data. Parameter #25 is the minimum time after negation of the strobes during which
the valid data remains on the address bus. Parameter #28 is the maximum time between
the negation of the strobes by the processor and the negation of DTACK by the slave
device. If DTACK remains asserted past the time specified by parameter #28, the
processor may recognize it as being asserted early in the next bus cycle and may
terminate that cycle prematurely. Figure 3-31 shows the important timing specifications for
a pseudo-asynchronous write cycle.

3-32 MC68306 USER'S MANUAL MOTOROLA

ADDRASR/W

UDS/LDS

DATA

DTACK

11552226282920A

C

Figure 3-31. Pseudo-Asynchronous Write Cycle

3.8 SYNCHRONOUS OPERATION

In some systems, external devices use the system clock to generate DTACK and other
asynchronous input signals. This synchronous operation provides a closely coupled
design with maximum performance, appropriate for frequently accessed parts of the
system. For example, memory can operate in the synchronous mode, but peripheral
devices operate asynchronously. For a synchronous device, the designer uses explicit
timing information shown in AC Electrical Specifications—Read and Write Cycles.
These specifications define the state of all bus signals relative to a specific state of the
processor clock.

The standard M68000 bus cycle consists of four clock periods (eight bus cycle states)
and, optionally, an integral number of clock cycles inserted as wait states. Wait states are
inserted as required to allow sufficient response time for the external device. The following
state-by-state description of the bus cycle differs from those descriptions in 3.1.1 Read
Cycle and 3.1.2 Write Cycle by including information about the important timing
parameters that apply in the bus cycle states.

STATE 0 The bus cycle starts in S0, during which the clock is high. At the rising edge

of S0, the function code for the access is driven externally. Parameter #6A
defines the delay from this rising edge until the function codes are valid.
Also, the R/ W signal is driven high; parameter #18 defines the delay from
the same rising edge to the transition of R/W. The minimum value for
parameter #18 applies to a read cycle preceded by a write cycle; this value
is the maximum hold time for a low on R/W beyond the initiation of the read
cycle.

MOTOROLA MC68306 USER'S MANUAL 3-33

STATE 1 Entering S1, a low period of the clock, the address of the accessed device

is driven externally with an assertion delay defined by parameter #6.

STATE 2 On the rising edge of S2, a high period of the clock, AS is asserted. During

a read cycle, UDS and/or LDS is also asserted at this time. Parameter
#9 defines the assertion delay for these signals. For a write cycle, the R/W
signal is driven low with a delay defined by parameter #20.

STATE 3 On the falling edge of the clock entering S3, the data bus is driven out of

the high-impedance state with the data being written to the accessed
device (in a write cycle). Parameter #23 specifies the data assertion delay.
In a read cycle, no signal is altered in S3.

STATE 4 Entering the high clock period of S4, UDS/LDS is asserted

(during a write cycle) on the rising edge of the clock. As in S2 for a read
cycle, parameter #9 defines the assertion delay from the rising edge of S4
for UDS/LDS . In a read cycle, no signal is altered by the
processor during S4.

Until the falling edge of the clock at the end of S4 (beginning of S5), no
response from any external device except RESET is acknowledged by the
processor. If either DTACK or BERR is asserted before the falling edge of
S4 and satisfies the input setup time defined by parameter #47, the
processor enters S5 and the bus cycle continues. If either DTACK or BERR
is asserted but without meeting the setup time defined by parameter #47,
the processor may recognize the signal and continue the bus cycle; the
result is unpredictable. If neither DTACK nor BERR is asserted before the
next rise of clock, the bus cycle remains in S4, and wait states (complete
clock cycles) are inserted until one of the bus cycle terminations is met.

STATE 5 S5 is a low period of the clock, during which the processor does not alter

any signal.

STATE 6 S6 is a high period of the clock, during which data for a read operation is

set up relative to the falling edge (entering S7). Parameter #27 defines the
minimum period by which the data must precede the falling edge. For a
write operation, the processor changes no signal during S6.

STATE 7 On the falling edge of the clock entering S7, the processor latches data

and negates AS and UDS/LDS during a read cycle. The hold
time for these strobes from this falling edge is specified by parameter #12.
The hold time for data relative to the negation of AS and UDS/LDS is
specified by parameter #29. For a write cycle, only AS and UDS / LDS ,
are negated; timing parameter #12 also applies.

3-34 MC68306 USER'S MANUAL MOTOROLA

On the rising edge of the clock, at the end of S7 (which may be the start of

ADDR

UDS/LDS

R/WASCLOCK

DTACK

69S0S1S2S3S4S5S6S7S0184727DATA

S0 for the next bus cycle), the processor places the address bus in the
high-impedance state. During a write cycle, the processor also places the
data bus in the high-impedance state and drives R/W high. External logic
circuitry should respond to the negation of the AS and UDS /LDS by negating
DTACK and/or BERR . Parameter #28 is the hold time for DTACK, and
parameter #30 is the hold time for BERR .

Figure 3-32 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
shown in Figure 3-33.

Figure 3-32. Synchronous Read Cycle

MOTOROLA MC68306 USER'S MANUAL 3-35

ADDR

UDS/LDS

R/WASCLOCK

DTACK

6S0S1S2S3S4S5S6S7S018

DATA2353479

Figure 3-33. Synchronous Write Cycle

A key consideration when designing in a synchronous environment is the timing for the
assertion of DTACK and BERR by an external device. To properly use external inputs, the
processor must synchronize these signals to the internal clock. The processor must
sample the external signal, which has no defined phase relationship to the CPU clock,
which may be changing at sampling time, and must determine whether to consider the
signal high or low during the succeeding clock period. Successful synchronization requires
that the internal machine receives a valid logic level, whether the input is high, low, or in
transition.

Parameter #47 of AC Electrical Specifications—Read and Write Cycles is the
asynchronous input setup time. Signals that meet parameter #47 are guaranteed to be
recognized at the next falling edge of the system clock. However, signals that do not meet
parameter #47 are not guaranteed to be recognized. In addition, if DTACK is recognized
on a falling edge, valid data is latched into the processor (during a read cycle) on the next
falling edge, provided the data meets the setup time required (parameter #27). When
parameter #27 has been met, parameter #31 may be ignored. If DTACK is asserted with
the required setup time before the falling edge of S4, no wait states are incurred, and the
bus cycle runs at its maximum speed of four clock periods.

3-36 MC68306 USER'S MANUAL MOTOROLA

SECTION 4
EC000 CORE PROCESSOR

The EC000 core has a 16-bit data bus and 32-bit address bus while the full architecture
provides for 32-bit address and data register operations.

4.1 FEATURES

The following resources are available to the EC000 core:

• 8 32-Bit Address Registers

• 8 32-Bit Data Registers

• 4-Gbyte Direct Addressing Range

• 56 Powerful Instructions

• Operations on Five Main Data Types

• Memory-Mapped Input/Output (I/O)

• 14 Addressing Modes

4.2 PROCESSING STATES

The processor is always in one of three states: normal processing, exception processing,
or halted. It is in the normal processing state when executing instructions, fetching
instructions and operands, and storing instruction results.

Exception processing is the transition from program processing to system, interrupt, and
exception handling. Exception processing includes fetching the exception vector, stacking
operations, and refilling the instruction pipe after an exception. The processor enters
exception processing when an exceptional internal condition arises such as tracing an
instruction, an instruction results in a trap, or executing specific instructions. External
conditions, such as interrupts and access errors, also cause exceptions. Exception
processing ends when the first instruction of the exception handler begins to execute.

The processor halts when it receives an access error or generates an address error while
in the exception processing state. For example, if during exception processing of one
access error another access error occurs, the processor is unable to complete the
transition to normal processing and cannot save the internal state of the machine. The
processor assumes that the system is not operational and halts. Only an external reset
can restart a halted processor. Note that when the processor executes a STOP
instruction, it is in a special type of normal processing state, one without bus cycles. The
processor stops, but it does not halt.

MOTOROLA MC68306 USER'S MANUAL 4-1

4.3 PROGRAMMING MODEL

The EC000 core executes instructions in one of two modes—user mode or supervisor
mode. The user mode provides the execution environment for the majority of application
programs. The supervisor mode, which allows some additional instructions and privileges,
is used by the operating system and other system software.

To provide upward compatibility of code written for a specific implementation of the EC000
core, the user programmer's model, illustrated in Figure 4-1, is common to all
implementations. In the user programmer's model, the EC000 core offers 16, 32-bit,
general-purpose registers (D0–D7, A0–A7), a 32-bit program counter, and an 8-bit
condition code register. The first eight registers (D0–D7) are used as data registers for
byte (8-bit), word (16-bit), and long-word (32-bit) operations. The second set of seven
registers (A0–A6) and the user stack pointer (USP) can be used as software stack
pointers and base address registers. In addition, the address registers can be used for
word and long-word operations. All of the 16 registers can be used as index registers. The
supervisor programmer's model consists of supplementary registers used in the
supervisor mode.

31 0

D0
D1

D2
D3

D4
D5
D6

D7
A0
A1

A2
A3
A4

A5
A6
A7/USP

PC
CCR

DATA REGISTERS

ADDRESS REGISTERS

USER STACK POINTER
PROGRAM COUNTER

CONDITION CODE REGISTER

USER PROGRAMMING MODEL

31 0

SSP
SR(CCR)

SUPERVISOR PROGRAMMING MODEL

SUPERVISOR STACK POINTER
STATUS REGISTER (CCR IS ALSO SHOWN IN

THE USER PROGRAMMING MODEL)

EC1

Figure 4-1. Programmer's Model

4-2 MC68306 USER'S MANUAL MOTOROLA

The status register, illustrated in Figure 4-2, contains the interrupt mask (eight levels
available) and the following condition codes: overflow (V), zero (Z), negative (N), carry (C),
and extend (X). Additional status bits indicate that the processor is in the trace (T) mode
and/or in the supervisor (S) state.

USER BYTE

SYSTEM BYTE

15 14 13 12 11 10 9 8 7 56 43210

T0 S00I2I1I0 XNZVC000

TRACE MODE

SUPERVISOR/USER STATE

INTERRUPT

PRIORITY MASK

EXTEND

NEGATIVE

ZERO

OVERFLOW

CARRY

(CONDITION CODE REGISTER)

EC2

Figure 4-2. Status Register

4.3.1 Data Format Summary

The processor supports the basic data formats of the M68000 family. The instruction set
supports operations on other data formats such as memory addresses.

The operand data formats supported by the integer unit (IU) are the standard twos­complement data formats defined in the M68000 family architecture. Registers, memory,
or instructions themselves can contain IU operands. The operand size for each instruction
is either explicitly encoded in the instruction or implicitly defined by the instruction
operation. Table 4-1 lists the data formats for the processor. Refer to M68000PM/AD,

M68000 Family Programmer’s Reference Manual,

in registers and memory.

Operand Data Format Size Notes

Bit 1 Bit —
Binary-Coded Decimal (BCD) 8 Bits Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte
Byte Integer 8 Bits —
Word Integer 16 Bits —
Long-Word Integer 32 Bits —

Table 4-1. Processor Data Formats

for details on data format organization

MOTOROLA MC68306 USER'S MANUAL 4-3

4.3.2 Addressing Capabilities Summary

The EC000 core supports the basic addressing modes of the M68000 family. The register
indirect addressing modes support postincrement, predecrement, offset, and indexing,
which are particularly useful for handling data structures common to sophisticated
applications and high-level languages. The program counter indirect mode also has
indexing and offset capabilities. This addressing mode is typically required to support
position-independent software. Besides these addressing modes, the processor provides
index sizing and scaling features.

An instruction’s addressing mode can specify the value of an operand, a register
containing the operand, or how to derive the effective address of an operand in memory.
Each addressing mode has an assembler syntax. Some instructions imply the addressing
mode for an operand. These instructions include the appropriate fields for operands that
use only one addressing mode. Table 4-2 lists a summary of the effective addressing
modes for the processor. Refer to M68000PM/AD,

Reference Manual,

for details on instruction format and addressing modes.

Table 4-2. Effective Addressing Modes

Addressing Modes Syntax

Register Direct Addressing

Data Register Direct
Address Register Direct

EA=Dn
EA=An

M68000 Family Programmer’s

Absolute Data Addressing

Absolute Short
Absolute Long

Program Counter Relative Addressing

Relative with Offset
Relative with Index and Offset

Register Indirect Addressing

Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

Immediate Data Addressing

Immediate
Quick Immediate

Implied Addressing
Implied Register

EA=(Next Word)
EA=(Next Two Words)

EA=(PC)+d
EA=(PC)+d

EA=(An)
EA=(An), An ¨ An+N
An ¨ An–N, EA=(An)
EA=(An)+d
EA=(An)+(Xn)+d

DATA=Next Word(s)
Inherent Data

EA=SR, USP, SSP, PC,

16
8

16

8

VBR, SFC, DFC

4-4 MC68306 USER'S MANUAL MOTOROLA

4.3.3 Notation Conventions

Table 4-3 lists the notation conventions used in this manual unless otherwise specified.

Table 4-3. Notation Conventions

Single and Double Operand Operations

+ Arithmetic addition or postincrement indicator.
– Arithmetic subtraction or predecrement indicator.

× Arithmetic multiplication.
÷ Arithmetic division or conjunction symbol.

~ Invert; operand is logically complemented.
Λ Logical AND
V Logical OR
⊕ Logical exclusive OR

˘ Source operand is moved to destination operand.

¯ ˘ Two operands are exchanged.

<op> Any double-operand operation.

<operand>tested Operand is compared to zero and the condition codes are set appropriately.

sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion.

Other Operations

TRAP Equivalent to Format ÷ Offset Word ˘ (SSP); SSP – 2 ˘ SSP; PC ˘ (SSP); SSP – 4 ˘ SSP; SR

(SSP); SSP – 2 ˘ SSP; (Vector) ˘ PC

˘

STOP Enter the stopped state, waiting for interrupts.

<operand>

If <condition>
then <operations>
else <operations>

10

The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then” are performed. If the condition is false

and the optional “else” clause is present, the operations after “else” are performed. If the
condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc
instruction description as an example.

Register Specification

An Any Address Register n (example: A3 is address register 3)

Ax, Ay Source and destination address registers, respectively.

BR Base Register—An, PC, or suppressed.

Dc Data register D7–D0, used during compare.

Dh, Dl Data registers high- or low-order 32 bits of product.

Dn Any Data Register n (example: D5 is data register 5)

Dr, Dq Data register’s remainder or quotient of divide.

Du Data register D7–D0, used during update.

Dx, Dy Source and destination data registers, respectively.

Rn Any Address or Data Register

Rx, Ry Any source and destination registers, respectively.

Xn Index Register—An, Dn, or suppressed.

MOTOROLA MC68306 USER'S MANUAL 4-5

Table 4-3. Notation Conventions (Continued)

Data Format And Type

<fmt> Operand Data Format: Byte (B), Word (W), Long (L), or Packed (P).

B, W, L Specifies a signed integer data type (twos complement) of byte, word, or long word.

k A twos complement signed integer (–64 to +17) specifying a number’s format to be stored in

the packed decimal format.

Subfields and Qualifiers

#<xxx> or #<data> Immediate data following the instruction word(s).

( ) Identifies an indirect address in a register.

[ ] Identifies an indirect address in memory.
bd Base Displacement
d

n

LSB Least Significant Bit
LSW Least Significant Word
MSB Most Significant Bit
MSW Most Significant Word

od Outer Displacement

SCALE A scale factor (1, 2, 4, or 8, for no-word, word, long-word, or quad-word scaling, respectively).

SIZE The index register’s size (W for word, L for long word).

{offset:width} Bit field selection.

CCR Condition Code Register (lower byte of status register)

PC Program Counter
SR Status Register

Displacement Value, n Bits Wide (example: d16 is a 16-bit displacement).

Register Names

4-6 MC68306 USER'S MANUAL MOTOROLA

Table 4-3. Notation Conventions (Concluded)

Register Codes

* General Case.

C Carry Bit in CCR

cc Condition Codes from CCR

FC Function Code

N Negative Bit in CCR
U Undefined, Reserved for Motorola Use.
V Overflow Bit in CCR
X Extend Bit in CCR

Z Zero Bit in CCR

— Not Affected or Applicable.

Stack Pointers

SP Active Stack Pointer
SSP Supervisor Stack Pointer
USP User Stack Pointer

Miscellaneous

<ea> Effective Address

<label> Assemble Program Label

<list> List of registers, for example D3–D0.

LB Lower Bound

m Bit m of an Operand

m–n Bits m through n of Operand

UB Upper Bound

4.4 EC000 CORE INSTRUCTION SET OVERVIEW

Design of the instruction set gives special emphasis to support of structured, high-level
languages and to ease of assembly language programming. Each instruction, with a few
exceptions, operates on bytes, words, and long words, and most instructions can use any
of the 14 addressing modes. Over 1000 useful instructions are provided by combining
instruction types, data types, and addressing modes. These instructions include signed
and unsigned multiply and divide, "quick" arithmetic operations, BCD arithmetic, and
expanded operations (through traps). Additionally, the highly symmetric, proprietary
microcoded structure of the instruction set provides a sound, flexible base for the future.

The EC000 core instruction set is listed in Table 4-4. For detailed information on the
EC000 core instruction set, refer to M68000PM/AD,

Manual

MOTOROLA MC68306 USER'S MANUAL 4-7

.

M68000 Programmer's Reference

Table 4-4. EC000 Core Instruction Set Summary

Opcode Operation Syntax

ABCD BCD Source + BCD Destination + X ˘ Destination ABCD Dy,Dx

ABCD –(Ay),–(Ax)

ADD Source + Destination ˘ Destination ADD <ea>,Dn

ADD Dn,<ea>
ADDA Source + Destination ˘ Destination ADDA <ea>,An
ADDI Immediate Data + Destination ˘ Destination ADDI #<data>,<ea>
ADDQ Immediate Data + Destination ˘ Destination ADDQ #<data>,<ea>
ADDX Source + Destination + X ˘ Destination ADDX Dy,Dx

ADDX –(Ay),–(Ax)
AND Source Λ Destination ˘ Destination AND <ea>,Dn

AND Dn,<ea>
ANDI Immediate Data Λ Destination ˘ Destination ANDI #<data>,<ea>
ANDI to CCR Source Λ CCR ˘ CCR ANDI #<data>,CCR
ANDI to SR If supervisor state

then Source Λ SR ˘ SR

else TRAP

ASL, ASR Destination Shifted by count ˘ Destination ASd Dx,Dy

Bcc If condition true

then PC + dn ˘ PC

BCHG ~(bit number of Destination) ˘ Z;

~(bit number of Destination) ˘ (bit number) of
Destination

ANDI #<data>,SR

1

ASd #<data>,Dy

ASd <ea>

Bcc <label>

BCHG Dn,<ea>

BCHG #<data>,<ea>

1

1

BCLR ~(bit number of Destination) ˘ Z;

0 ˘ bit number of Destination
BRA PC + dn ˘ PC BRA <label>
BSET ~(bit number of Destination) ˘ Z;

1 ˘ bit number of Destination
BSR SP – 4 ˘ SP; PC ˘ (SP); PC + dn ˘ PC BSR <label>
BTST –(bit number of Destination) ˘ Z; BTST Dn,<ea>

CHK If Dn < 0 or Dn > Source

then TRAP
CLR 0 ˘ Destination CLR <ea>
CMP Destination – Source ˘ cc CMP <ea>,Dn
CMPA Destination – Source CMPA <ea>,An
CMPI Destination – Immediate Data CMPI #<data>,<ea>

BCLR Dn,<ea>
BCLR #<data>,<ea>

BSET Dn,<ea>
BSET #<data>,<ea>

BTST #<data>,<ea>
CHK <ea>,Dn

4-8 MC68306 USER'S MANUAL MOTOROLA

Table 4-4. EC000 Core Instruction Set Summary (Continued)

Opcode Operation Syntax

CMPM Destination – Source ˘ cc CMPM (Ay)+,(Ax)+
DBcc If condition false

then (Dn–1 ˘ Dn;

If Dn ≠ –1

then PC + dn ˘ PC)

DIVS Destination ÷ Source ˘ Destination DIVS.W <ea>,Dn 32 ÷ 16 ˘ 16r:16q

DIVU Destination ÷ Source ˘ Destination DIVU.W <ea>,Dn 32 ÷ 16 ˘ 16r:16q

EOR Source ⊕ Destination ˘ Destination EOR Dn,<ea>
EORI Immediate Data ⊕ Destination ˘ Destination EORI #<data>,<ea>
EORI to CCR Source ⊕ CCR ˘ CC R EORI #<data>,CCR
EORI to SR If supervisor state

then Source ⊕ SR ˘ SR

else TRAP

EXG Rx ¯ ˘ Ry EXG Dx,Dy

DBcc Dn,<label>

DIVS.L <ea>,Dq 32 ÷ 32 ˘ 32q
DIVS.L <ea>,Dr:Dq 64 ÷ 32 ˘ 32r:32q

DIVU.L <ea>,Dq 32 ÷ 32 ˘ 32q
DIVU.L <ea>,Dr:Dq 64 ÷ 32 ˘ 32r:32q

EORI #<data>,SR

EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx

EXT Destination Sign – Extended ˘ Destination EXT.W Dn extend byte to word

EXT.L Dn extend word to long word
JMP Destination Address ˘ PC JMP <ea>
JSR SP – 4 ˘ SP; PC ˘ (SP)

Destination Address ˘ PC
LEA <ea> ˘ An LEA <ea>,An
LINK SP – 4 ˘ SP; An ˘ (SP)

SP ˘ An, SP+d ˘ SP
LSL, LSR Destination Shifted by count ˘ Destination LSd Dx,Dy

MOVE Source ˘ Destination MOVE <ea>,<ea>
MOVE from SR If supervisor state

then SR ˘ Destination

else TRAP
MOVE to CCR Source ˘ CCR MOVE <ea>,CCR
MOVE to SR If supervisor state

then Source ˘ SR

else TRAP
MOVE USP If supervisor state

then USP ˘ An or An ˘ USP

else TRAP

JSR <ea>

LINK An,d

LSd #<data>,Dy
LSd <ea>

MOVE SR,<ea>

MOVE <ea>,SR

MOVE USP,An
MOVE An,USP

n

1

1

1

MOTOROLA MC68306 USER'S MANUAL 4-9

Table 4-4. EC000 Core Instruction Set Summary (Continued)

Opcode Operation Syntax

MOVEA Source ˘ Destination MOVEA <ea>,An
MOVEM Registers ˘ Destination

Source ˘ Registers

MOVEP Source ˘ Destination MOVEP Dx,(dn,Ay)

MOVEQ Immediate Data ˘ Destination MOVEQ #<data>,Dn
MULS Source × Destination ˘ Destination MULS.W <ea>,Dn 16 × 16 ˘ 32

MULU Source × Destination ˘ Destination MULU.W <ea>,Dn 16 × 16 ˘ 32

NBCD 0 – (Destination10) – X ˘ Destination NBCD <ea>
NEG 0 – (Destination) ˘ Destination NEG <ea>
NEGX 0 – (Destination) – X ˘ Destination NEGX <ea>
NOP None NOP
NOT ~ Destination ˘ Destination NOT <ea>
OR Source V Destination ˘ Destination OR <ea>,Dn

MOVEM <list>,<ea>
MOVEM <ea>,<list>

MOVEP (dn,Ay),Dx

MULS.L <ea>,Dl 32 × 32 ˘ 32
MULS.L <ea>,Dh–Dl 32 × 32 ˘ 64

MULU.L <ea>,Dl 32 × 32 ˘ 32
MULU.L <ea>,Dh–Dl 32 × 32 ˘ 64

OR Dn,<ea>

2
2

ORI Immediate Data V Destination ˘ Destination ORI #<data>,<ea>
ORI to CCR Source V CCR ˘ CC R ORI #<data>,CCR
ORI to SR If supervisor state

then Source V SR ˘ SR

else TRAP
PEA SP – 4 ˘ SP; <ea> ˘ (SP) PEA <ea>
RESET If supervisor state

then Assert RSTO Line

else TRAP
ROL, ROR Destination Rotated by count ˘ Destination ROd Rx,Dy

ROXL, ROXR Destination Rotated with X by count ˘ Destination ROXd Dx,Dy

RTE If supervisor state

then (SP) ˘ SR; SP + 2 ˘ SP; (SP) ˘ PC;
SP + 4 ˘ SP; restore state and deallocate
stack according to (SP)

else TRAP
RTR (SP) ˘ CCR; SP + 2 ˘ SP;

(SP) ˘ PC; SP + 4 ˘ SP

ORI #<data>,SR

RESET

1

ROd #<data>,Dy

1

ROXd #<data>,Dy
ROXd <ea>

RTE

RTR

1

1

1

RTS (SP) ˘ PC; SP + 4 ˘ SP RTS

4-10 MC68306 USER'S MANUAL MOTOROLA

Table 4-4. EC000 Core Instruction Set Summary (Concluded)

Opcode Operation Syntax

SBCD Destination10 – Source10 – X ˘ Destination SBCD Dx,Dy

SBCD –(Ax),–(Ay)

Scc If condition true

then 1s ˘ Destination

else 0s ˘ Destination

STOP If supervisor state

then Immediate Data ˘ SR; STOP

else TRAP

SUB Destination – Source ˘ Destination SUB <ea>,Dn

SUBA Destination – Source ˘ Destination SUBA <ea>,An
SUBI Destination – Immediate Data ˘ Destination SUBI #<data>,<ea>
SUBQ Destination – Immediate Data ˘ Destination SUBQ #<data>,<ea>
SUBX Destination – Source – X ˘ Destination SUBX Dx,Dy

SWAP Register 31–16 ¯ ˘ Register 15–0 SWAP Dn
TAS Destination Tested ˘ Condition Codes;

1 ˘ bit 7 of Destination

TRAP SSP – 2 ˘ SSP; Format ÷ Offset ˘ (SSP);

SSP – 4 ˘ SSP; PC ˘ (SSP); SSP – 2 ˘ SSP;
SR ˘ (SSP); Vector Address ˘ PC

Scc <ea>

STOP #<data>

SUB Dn,<ea>

SUBX –(Ax),–(Ay)

TAS <ea>

TRAP #<vector>

TRAPV If V

then TRAP
TST Destination Tested ˘ Condition Codes TST <ea>
UNLK An ˘ SP; (SP) ˘ An; SP + 4 ˘ SP UNLK An

NOTES:

1. d is direction, left or right.

2. List refers to register.

TRAPV

MOTOROLA MC68306 USER'S MANUAL 4-11

4.5 EXCEPTION PROCESSING

This section describes the processing for each type of exception, exception priorities, the
return from an exception, and bus fault recovery. This section also describes the formats
of the exception stack frames.

Exception processing is the activity performed by the processor in preparing to execute a
special routine for any condition that causes an exception. In particular, exception
processing does not include the execution of the routine itself. Exception processing is the
transition from the normal processing of a program to the processing required for any
special internal or external condition that preempts normal processing. External conditions
that cause exceptions are interrupts from external devices, bus errors, and resets. Internal
conditions that cause exceptions are instructions, address errors, and tracing. For
example, the TRAP, TRAPV, CHK, RTE, and DIV instructions can generate exceptions as
part of their normal execution. In addition, illegal instructions and privilege violations cause
exceptions. Exception processing uses an exception vector table and an exception stack
frame.

Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not
guaranteed to occur in the order in which they are described in this section. Figure 4-3
illustrates a general flowchart for the steps taken by the processor during exception
processing.

During the first step, the processor makes an internal copy of the status register (SR).
Then the processor changes to the supervisor mode by setting the S-bit and inhibits
tracing of the exception handler by clearing the trace enable (T) bit in the SR. For the
reset and interrupt exceptions, the processor also updates the interrupt priority mask in
the SR.

During the second step, the processor determines the vector number for the exception.
For interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the
vector number. For all other exceptions, internal logic provides the vector number. This
vector number is used in the last step to calculate the address of the exception vector.
Throughout this section, vector numbers are given in decimal notation.

4-12 MC68306 USER'S MANUAL MOTOROLA

SAVE INTERNAL

FETCH VECTOR

ENTRY

COPY OF SR

S 1

➧

T 0

➧

(SEE NOTE)

NUMBER

OTHERWISE

SAVE CONTENTS

TO STACK FRAME

(SEE NOTE)

OTHERWISE

EXECUTE EXCEPTION

HANDLER

OTHERWISE

BEGIN INSTRUCTION

EXECUTION

BUS ERROR

(DOUBLE BUS FAULT)

BUS ERROR

(DOUBLE BUS FAULT)

BUS ERROR OR

ADDRESS ERROR

(DOUBLE BUS FAULT)

EXIT

EXIT

NOTE: These blocks vary for reset and interrupt exceptions.

EC28

Figure 4-3. General Exception Processing Flowchart

MOTOROLA MC68306 USER'S MANUAL 4-13

The third step is to save the current processor contents for all exceptions other than reset

EVEN BYTE

ODD BYTE

PROGRAM COUNTER LOW

PROGRAM COUNTER HIGH

SSP7070015

STATUS REGISTER

HIGHER

A

S

exception, which does not stack information. The processor creates an exception stack
frame on th e active supervisor stack and fills it with information appropriate for the type of
exception. Other information can also be stacked, depending on which exception is being
processed and the state of the processor prior to the exception. Figure 4-4 illustrates the
general form of the exception stack frame.

DDRES

Figure 4-4. General Form of Exception Stack Frame

The last step initiates execution of the exception handler. The new program counter value
is fetched from the exception vector. The processor then resumes instruction execution.
The instruction at the address in the exception vector is fetched, and normal instruction
decoding and execution is started.

4.5.1 Exception Vectors

An exception vector is a memory location from which the processor fetches the address of
a routine to handle an exception. Each exception type requires a handler routine and a
unique vector. All exception vectors are two words in length (see Figure 4-5), except for
the reset vector, which is four words long. All exception vectors reside in the supervisor
data space, except for the reset vector, which is in the supervisor program space. A vector
number is an 8-bit number that is multiplied by four to obtain the offset of an exception
vector. Vector numbers are generated internally or externally, depending on the cause of
the exception. For interrupts, during the interrupt acknowledge bus cycle, a peripheral
provides an 8-bit vector number (see Figure 4-6) to the processor on data bus lines D7–
D0.

The processor forms the vector offset by left-shifting the vector number two bit positions
and zero-filling the upper-order bits to obtain a 32-bit long-word vector offset. In the
EC000 core this offset is used as the absolute address to obtain the exception vector
itself, which is illustrated in Figure 4-6.

4-14 MC68306 USER'S MANUAL MOTOROLA

EVEN BYTE (A0=0) ODD BYTE (A0=0)

A31A0A10

ALL ZEROES

v7v6v5v4v3v2v1v00

0

WORD 0

WORD 1

NEW PROGRAM COUNTER (HIGH)

NEW PROGRAM COUNTER (LOW)

A1=0

A1=1

EC30

Figure 4-5. Exception Vector Format

Figure 4-6. Address Translated from 8-Bit Vector Number

The actual address on the address bus is truncated to the number of address bits
available on the bus of the particular implementation of the M68000 architecture. In the
EC000 core, this is 24 address bits. The memory map for exception vectors is shown in
Table 4-5.

The vector table is 512 words long (1024 bytes), starting at address 0 (decimal) and
proceeding through address 1023 (decimal). The vector table provides 255 unique
vectors, some of which are reserved for trap and other system function vectors. Of the
255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not
protected, so user interrupt vectors may overlap at the discretion of the systems designer.

MOTOROLA MC68306 USER'S MANUAL 4-15

Table 4-5. Exception Vector Assignments

Vector

Number(s)

0
1
2
3

4
5
6
7

8

9
10
11

1

12

1

13

14
15

1

16–23

24
25
26
27

28
29
30
31

32–47 080–0BC SD TRAP #0–15 Instruction Vectors

1

48–63
64–255 100–3FC SD User Defined Vectors

NOTES:

1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future enhancements by Motorola.
No user peripheral devices should be assigned these numbers.

2. Reset vector (0) requires four words, unlike the other vectors which only require two words,
and is located in the supervisor program space.

3. The spurious interrupt vector is taken when there is a bus error indication during interrupt processing.

4. TRAP #n uses vector number 32+ n.

5. Reserved.

6. SP denotes supervisor program space, and SD denotes supervisor data space.

Vector Offset

(Hex) Space

000
004
008

00C

010
014
018

01C

020
024
028

02C

030
034
038

03C

040–05C — (Unassigned, Reserved)

060
064
068

06C

070
074
078

07C

0C0–0FC — (Unassigned, Reserved)

SP

SP
SD
SD

SD
SD
SD
SD

SD
SD
SD
SD

—

—
SD
SD

SD
SD
SD
SD

SD
SD
SD
SD

6

Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter
Bus Error
Address Error

Illegal Instruction
Integer Divide by Zero
CHK Instruction
TRAPV Instruction

Privilege Violation
Trace
Line 1010 Emulator (Unimplemented A-Line Opcode)
Line 1111 Emulator (Unimplemented F-Line Opcode)

(Unassigned, Reserved)
(Unassigned, Reserved)
Format Error
Uninitialized Interrupt Vector

Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector

Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector

5

Assignment

2

2

3

4

4.6 PROCESSING OF SPECIFIC EXCEPTIONS

The exceptions are classified according to their sources, and each type is processed
differently. The following paragraphs describe in detail the types of exceptions and the
processing of each type.

4-16 MC68306 USER'S MANUAL MOTOROLA

4.6.1 Reset Exception

The reset exception corresponds to the highest exception level. The processing of the
reset exception is performed for system initiation and recovery from catastrophic failure.
Any processing in progress at the time of the reset is aborted and cannot be recovered.
The processor is forced into the supervisor state, and the trace state is forced off. The
interrupt priority mask is set at level 7. The vector number is internally generated to
reference the reset exception vector at location 0 in the supervisor program space.
Because no assumptions can be made about the validity of register contents, in particular
the SSP, neither the program counter nor the status register are saved. The address in
the first two words of the reset exception vector is fetched as the initial SSP, and the
address in the last two words of the reset exception vector is fetched as the initial program
counter. Finally, instruction execution is started at the address in the program counter.
The initial program counter should point to the power-up/restart code.

The RESET instruction does not cause a reset exception; it asserts the RESET signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.

4.6.2 Interrupt Exceptions

Seven levels of interrupt priorities are provided, numbered from 1–7. Level 7 has the
highest priority. Devices can be chained externally within interrupt priority levels, allowing
an unlimited number of peripheral devices to interrupt the processor. The status register
contains a 3-bit mask indicating the current interrupt priority, and interrupts are inhibited
for all priority levels less than or equal to the current priority. Priority level 7 is a special
case. Level 7 interrupts cannot be inhibited by the interrupt priority mask, thus providing a
non-maskable interrupt capability. An interrupt is generated each time the interrupt
request level changes from some lower level to level 7. A level 7 interrupt may still be
caused by the level comparison if the request level is a 7 and the processor priority is set
to a lower level by an instruction.

An interrupt request is made to the processor by encoding the interrupt request level on
the IPL2–IPL0; a zero indicates no interrupt request. Interrupt requests arriving at the
processor do not force immediate exception processing, but the requests are made
pending. Pending interrupts are detected between instruction executions. If the priority of
the pending interrupt is lower than or equal to the current processor priority, execution
continues with the next instruction, and the interrupt exception processing is postponed
until the priority of the pending interrupt becomes greater than the current processor
priority.

If the priority of the pending interrupt is greater than the current processor priority, the
exception processing sequence is started. A copy of the status register is saved; the
privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority
level is set to the level of the interrupt being acknowledged. The processor fetches the
vector number from the interrupting device by executing an interrupt acknowledge cycle,
which displays the level number of the interrupt being acknowledged on the address bus.
If external logic requests an automatic vector, the processor internally generates a vector
number corresponding to the interrupt level number. If external logic indicates a bus error,

MOTOROLA MC68306 USER'S MANUAL 4-17

the interrupt is considered spurious, and the generated vector number references the
spurious interrupt vector. The processor then proceeds with the usual exception
processing. The saved value of the program counter is the address of the instruction that
would have been executed had the interrupt not been taken. The appropriate interrupt
vector is fetched and loaded into the program counter, and normal instruction execution
commences in the interrupt handling routine.

4.6.3 Uninitialized Interrupt Exception

An interrupting device provides a EC000 core interrupt vector number and asserts data
transfer acknowledge (DTACK) or bus error ( BERR ) during an interrupt acknowledge
cycle by the EC000 core. If the vector register has not been initialized, the responding
M68000 family peripheral provides vector number 15, the uninitialized interrupt vector.
This response conforms to a uniform way to recover from a programming error.

4.6.4 Spurious Interrupt Exception

During the interrupt acknowledge cycle, if no device responds by asserting DTACK, BERR
should be asserted to terminate the vector acquisition. The processor separates the
processing of this error from bus error by forming a short format exception stack and
fetching the spurious interrupt vector instead of the bus error vector. The processor then
proceeds with the usual exception processing.

4.6.5 Instruction Traps

Traps are exceptions caused by instructions; they occur when a processor recognizes an
abnormal condition during instruction execution or when an instruction is executed that
normally traps during execution.

Exception processing for traps is straightforward. The status register is copied; the
supervisor mode is entered; and tracing is turned off. The vector number is internally
generated; for the TRAP instruction, part of the vector number comes from the instruction
itself. The program counter, and the copy of the status register are saved on the
supervisor stack. The saved value of the program counter is the address of the instruction
following the instruction that generated the trap. Finally, instruction execution commences
at the address in the exception vector.

Some instructions are used specifically to generate traps. The TRAP instruction always
forces an exception and is useful for implementing system calls for user programs. The
TRAPV and CHK instructions force an exception if the user program detects a run-time
error, which may be an arithmetic overflow or a subscript out of bounds. A signed divide
(DIVS) or unsigned divide (DIVU) instruction forces an exception if a division operation is
attempted with a divisor of zero.

4.6.6 Illegal and Unimplemented Instructions

Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal processor instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define

4-18 MC68306 USER'S MANUAL MOTOROLA

instructions using the opcodes of any of the illegal instructions. Three bit patterns always
force an illegal instruction trap on all M68000 family-compatible microprocessors. The
patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are
reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer
use (as the take illegal instruction trap (ILLEGAL) instruction).

Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit
efficient emulation. These separate vectors allow the operating system to emulate
unimplemented instructions in software.

Exception processing for illegal instructions is similar to that for traps. After the instruction
is fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
is then pushed on the supervisor stack, and the illegal instruction vector is fetched.

4.6.7 Privilege Violations

To provide system security, various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user mode causes an exception. The privileged
instructions are as follows:

AND Immediate to SR MOVE USP
EOR Immediate to SR OR Immediate to SR
MOVE to SR RESET
MOVE from SR RTE
MOVEC STOP
MOVES

Exception processing for privilege violations is nearly identical to that for illegal
instructions. After the instruction is fetched and decoded and the processor determines
that a privilege violation is being attempted, the processor starts exception processing.
The status register is copied; the supervisor mode is entered; and tracing is turned off.
The vector number is generated to reference the privilege violation vector, and the current
program counter and the copy of the status register are saved on the supervisor stack.
The saved value of the program counter is the address of the first word of the instruction
causing the privilege violation. Finally, instruction execution commences at the address in
the privilege violation exception vector.

4.6.8 Tracing

To aid in program development, the EC000 core includes a facility to allow tracing
following each instruction. When tracing is enabled, an exception is forced after each
instruction is executed. Thus, a debugging program can monitor the execution of the
program under test.

The trace facility is controlled by the T-bit in the supervisor portion of the status register. If
the T-bit is cleared (off), tracing is disabled and instruction execution proceeds from
instruction to instruction as normal. If the T-bit is set (on) at the beginning of the execution
of an instruction, a trace exception is generated after the instruction is completed. If the

MOTOROLA MC68306 USER'S MANUAL 4-19

instruction is not executed because an interrupt is taken or because the instruction is
illegal or privileged, the trace exception does not occur. The trace exception also does not
occur if the instruction is aborted by a reset, bus error, or address error exception. If the
instruction is executed and an interrupt is pending on completion, the trace exception is
processed before the interrupt exception. During the execution of the instruction, if an
exception is forced by that instruction, the exception processing for the instruction
exception occurs before that of the trace exception.

As an extreme illustration of these rules, consider the arrival of an interrupt during the
execution of a TRAP instruction while tracing is enabled. First, the trap exception is
processed, then the trace exception, and finally the interrupt exception. Instruction
execution resumes in the interrupt handler routine.

After the execution of the instruction is complete and before the start of the next
instruction, exception processing for a trace begins. A copy is made of the status register.
The transition to supervisor mode is made, and the T-bit of the status register is turned off,
disabling further tracing. The vector number is generated to reference the trace exception
vector, and the current program counter and the copy of the status register are saved on
the supervisor stack. The saved value of the program counter is the address of the next
instruction. Instruction execution commences at the address contained in the trace
exception vector.

4.6.9 Bus Error

When a bus error exception occurs, the current bus cycle is aborted. The current
processor activity, whether instruction or exception processing, is terminated, and the
processor immediately begins exception processing.

Exception processing for a bus error follows the usual sequence of steps. The status
register is copied, the supervisor mode is entered, and tracing is turned off. The vector
number is generated to refer to the bus error vector. Since the processor is fetching the
instruction or an operand when the error occurs, the context of the processor is more
detailed. To save more of this context, additional information is saved on the supervisor
stack. The program counter and the copy of the status register are saved. The value
saved for the program counter is advanced 2–10 bytes beyond the address of the first
word of the instruction that made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved program counter has a value in
the vicinity of the current instruction, even if the current instruction is a branch, a jump, or
a return instruction. In addition to the usual information, the processor saves its internal
copy of the first word of the instruction being processed and the address being accessed
by the aborted bus cycle. Specific information about the access is also saved: type of
access (read or write), processor activity (processing an instruction), and function code
outputs when the bus error occurred. The processor is processing an instruction if it is in
the normal state or processing a group 2 exception; the processor is not processing an
instruction if it is processing a group 0 or a group 1 exception. Figure 4-7 illustrates how
this information is organized on the supervisor stack. If a bus error occurs during the last
step of exception processing, while either reading the exception vector or fetching the
instruction, the value of the program counter is the address of the exception vector.
Although this information is not generally sufficient to effect full recovery from the bus

4-20 MC68306 USER'S MANUAL MOTOROLA

error, it does allow software diagnosis. Finally, the processor commences instruction
processing at the address in the vector. It is the responsibility of the error handler routine
to clean up the stack and determine where to continue execution.

If a bus error occurs during the exception processing for a bus error, an address error, or
a reset, the processor halts and all processing ceases. This halt simplifies the detection of
a catastrophic system failure, since the processor removes itself from the system to
protect memory contents from erroneous accesses. Only an external reset operation can
restart a halted processor.

LOWER

ADDRESS

15

R/W

ACCESS ADDRESS

PROGRAM COUNTER

R/W (READ/WRITE): WRITE = 0, READ = 1. I/N
(INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1.

2345

FUNCTION CODE

I/N

HIGH

LOW

INSTRUCTION REGISTER

STATUS REGISTER

HIGH
LOW

0

EC33

Figure 4-7. Supervisor Stack Order for Bus or Address Error Exception

4.6.10 Address Error

An address error exception occurs when the processor attempts to access a word or long­word operand or an instruction at an odd address. An address error is similar to an
internally generated bus error. The bus cycle is aborted, and the processor ceases current
processing and begins exception processing. The exception processing sequence is the
same as that for a bus error, including the information to be stacked, except that the
vector number refers to the address error vector. Likewise, if an address error occurs
during the exception processing for a bus error, address error, or reset, the processor is
halted.

4.6.11 Multiple Exceptions

When multiple exceptions occur simultaneously, they are processed according to a fixed
priority. Table 4-6 lists the exceptions, grouped by characteristics, with group 0 as the
highest priority. Within group 0, reset has highest priority, followed by address error and
then bus error. Within group 1, trace has priority over external interrupts, which in turn
takes priority over illegal instruction and privilege violation. Since only one instruction can
be executed at a time, no priority relationship applies within group 2.

MOTOROLA MC68306 USER'S MANUAL 4-21

Table 4-6. Exception Grouping and Priority

Group Exception Processing

0 Reset, Address

Error, and Bus
Error

1 Trace, Interrupt,

Illegal, and
Privilege

Exception processing begins within two clock cycles.

Exception processing begins before the next instruction.

2 TRAP, TRAPV,

CHK, and DIV

Exception processing is started by normal instruction execution.

The priority relationship between two exceptions determines which is taken, or taken first,
if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is
aborted. In another example, if an interrupt request occurs during the execution of an
instruction while the T-bit in the status register (SR) is asserted, the trace exception has
priority and is processed first. Before instruction execution resumes, however, the interrupt
exception is also processed, and instruction processing finally commences in the interrupt
handler routine. As a general rule, the lower the priority of an exception, the sooner the
handler routine for that exception executes. This rule does not apply to the reset
exception; its handler is executed first even though it has the highest priority, because the
reset operation clears all other exceptions.

4-22 MC68306 USER'S MANUAL MOTOROLA

SECTION 5

RESET

SYSTEM OPERATION

This section contains detailed descriptions and programming information for the system
functions and registers outside the EC000 core in the MC68306.

NOTE

None of the MC68306 internal resources are accessible by an
external bus master. The following address map and operation
descriptions apply only to accesses by the internal EC000
core.

The effect of the RESET instruction and external assertion of the hardware RESET signal
on MC68306 components is:

External

EC000 Core Yes No

Serial Module Yes Yes

MC68306 Registers See Individual Descriptions No

RESET Instruction

5.1 MC68306 ADDRESS SPACE

The full 32-bit address capability of the MC68306 (corresponding to a 4-Gbyte address
space) is decoded internally. A small portion of this address space is devoted to internal
resources such as the serial module, configuration registers, and parallel ports. Table 5-1
is a memory map of the MC68306.

MOTOROLA MC68306 USER'S MANUAL 5-1

Table 5-1. MC68306 Memory Map

FC A(31–0) D(15–8) (EVEN ADDRESS) D(7–0) (ODD ADDRESS)

5 FFFFFFFE/F SYSTEM TIMER VECTOR
5 FFFFFFFC/D REFRESH RATE BUS TIMEOUT PERIOD
5 FFFFFFFA INTERRUPT CONTROL REGISTER
5 FFFFFFF8 INTERRUPT STATUS REGISTER
5 FFFFFFF6 RESERVED
5 FFFFFFF4/5 PORT A PIN ASSIGNMENT PORT B PIN ASSIGNMENT
5 FFFFFFF2/3 PORT A DATA DIRECTION PORT B DATA DIRECTION
5 FFFFFFF0/1 PORT A DATA PORT B DATA
5 FFFFFFEF–

RESERVED

FFFFFFE8

5 FFFFFFE6

FFFFFFE4

5 FFFFFFE2

FFFFFFE0

5 FFFFFFDE

FFFFFFDC

5 FFFFFFDA

FFFFFFD8

5 FFFFFFD6

FFFFFFD4

5 FFFFFFD2

FFFFFFD0

5 FFFFFFCE

FFFFFFCC

5 FFFFFFCA

FFFFFFC8

5 FFFFFFC6

FFFFFFC4

5 FFFFFFC2

FFFFFFC0

5 FFFFFFBF–

DRAM BANK 1 CONFIGURATION (LOW)

DRAM BANK 1 CONFIGURATION (HIGH)

DRAM BANK 0 CONFIGURATION (LOW)

DRAM BANK 0 CONFIGURATION (HIGH)

CHIP SELECT 7 CONFIGURATION (LOW)

CHIP SELECT 7 CONFIGURATION (HIGH)

CHIP SELECT 6 CONFIGURATION (LOW)

CHIP SELECT 6 CONFIGURATION (HIGH)

CHIP SELECT 5 CONFIGURATION (LOW)

CHIP SELECT 5 CONFIGURATION (HIGH)

CHIP SELECT 4 CONFIGURATION (LOW)

CHIP SELECT 4 CONFIGURATION (HIGH)

CHIP SELECT 3 CONFIGURATION (LOW)

CHIP SELECT 3 CONFIGURATION (HIGH)

CHIP SELECT 2 CONFIGURATION (LOW)

CHIP SELECT 2 CONFIGURATION (HIGH)

CHIP SELECT 1 CONFIGURATION (LOW)

CHIP SELECT 1 CONFIGURATION (HIGH)

CHIP SELECT 0 CONFIGURATION (LOW)

CHIP SELECT 0 CONFIGURATION (HIGH)

RESERVED

FFFFF800

5 FFFFF7FF–

RESERVED

2

FFFFF7E0

5 FFFFF7DF–

RESERVED

FFFFF000

1, 2, 6 FFFFFFFF–

AVAILABLE FOR CHIP SELECT/DRAM

FFFFF000

1, 2, 5, 6 FFFFEFFF–

AVAILABLE FOR CHIP SELECT/DRAM

00000000

7 – INTERRUPT ACKNOWLEDGE: VECTOR SUPPLIED ON D7–D0

1. A(31–24) are copied from A23 (sign-extended) in 16 Mbyte emulation mode.

2. Write data ignored, read data indeterminate.

3. Duplicate of FFFFFFC0–FFFFFFFF.

4. Duplicate of FFFF7FE0–FFFF7FFF

2

2

3

SERIAL MODULE

4

5-2 MC68306 USER'S MANUAL MOTOROLA

5.2 REGISTER DESCRIPTION

The following paragraphs describe the registers in the MC68306. The address of the
register is listed above the register. The numbers in the first row are the bit positions of
each bit in the register. The second row is the bit mnemonic. The reset value for each bit
is listed beneath the bit mnemonic. Where the reset value is U, the value is indeterminate
after power-up, and not affected by reset.

5.2.1 System Register

The system register controls system functions. The value of the AMODE bit after reset is
the value of the AMODE pin latched at reset.

FFFFFFFE

15

BTERR BTEN 0 AMODE0 DUIPL2DUIPL1DUIPL

RESET

:

0

BTERR—Bus Timeout Error

13 12 11 10

14

0 AMODE0 1 0 0

0

8

9

0

SUPERVISOR ONLY

This bit is read-only, and is cleared when read. Writes to this bit are ignored.

0 = No bus timeout bus error.
1 = Bus timeout bus error occurred.

BTEN—Bus Timeout Enable

This bit is used to enable the bus timeout timer.

0 = Bus timeout timer is disabled.
1 = Bus timeout timer is enabled.

AMODE—Address Mode

This bit selects the function of the multiplexed address and chip select pins. The
address mode pin is latched at the end of reset, so the value must be valid and stable at
this time. Writes to this bit are ignored.

0 = Address lines selected.
1 = Chip select lines selected.

MOTOROLA MC68306 USER'S MANUAL 5-3

DUIPL2–0—DUART Interrupt Priority Level

This bit selects the interrupt priority level for the serial module.

000 = Reserved
001 = Interrupt priority level 1
010 = Interrupt priority level 2
011 = Interrupt priority level 3
100 = Interrupt priority level 4
101 = Interrupt priority level 5
110 = Interrupt priority level 6
111 = Interrupt priority level 7

5.2.2 Timer Vector Register

FFFFFFFF

76543210

TVEC7TVEC6TVEC5TVEC4TVEC3TVEC2TVEC1TVEC

RESE

T:

0

0 0 0 1 1 1 1

SUPERVISOR ONLY

0

TVEC7–0—Timer Vector

The value set in this field supplies the vector for the DUART timer interrupt handler.

5.2.3 Bus Timeout Period Register

FFFFFFFC

76543210

BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0

RESE

T:

U

A programmable-period timer can generate a bus error to terminate any bus cycle after 16
to 4096 wait states, programmable in 16-wait state increments. The bus timeout timer is
enabled by the BTEN bit in the system register.

The bus timeout timer restarts between the read and write portions of a TAS indivisible
cycle.

BT7–0—Bus Timeout Period

U U U U U U U

SUPERVISOR ONLY

The value set in this field supplies the bus timeout timer period. The bus timeout timer
period can be calculated from the equation:

Period = (16 × (register value +1)) × EXTAL

5-4 MC68306 USER'S MANUAL MOTOROLA

Where:
EXTAL is the crystal period in nanoseconds and period is in nanoseconds.

5.2.4 Interrupt Registers

Up to seven prioritized external interrupts can be supported by programming the following
registers. More interrupt sources can be supported by external daisy-chaining. The
interrupt inputs are internally synchronized. Edge-triggered interrupts are not supported.

Each interrupt can be either active-high or active-low. The active level is self-programmed
during reset, with no software intervention. Every interrupt must be at its inactive level at
the end of reset. Each interrupt can be enabled or disabled by programming the
corresponding bit in the interrupt control register.

Each interrupt can be auto-vectored, by programming the interrupt control register . Auto­vectored interrupt acknowledge cycles are zero wait states. If no active interrupt is present
at the level being acknowledged, the MC68306 automatically generates a spurious
interrupt vector, which is a zero wait state. Interrupt input synchronization is frozen during
an interrupt acknowledge cycle, so the acknowledge can safely be used to automatically
negate the interrupt.

5.2.4.1 INTERRUPT CONTROL REGISTER

FFFFFFFA/B

1514131211109876543210

IENT IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 — AVEC7AVEC6 AVEC5 AVEC4 AVEC3 AVEC2AVEC

1

RESE

T:

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0

SUPERVISOR ONLY

IENT—Timer Interrupt Enable

This bit enables the DUART timer interrupt.

0 = Interrupts disabled.
1 = Interrupts enabled.

IEN7–1—Interrupt Enable 7 through 1

These bits enable interrupt 7, 6, 5, 4, 3, 2, and 1.

0 = Interrupt disabled.
1 = Interrupt enabled.

AVEC7–1—Autovector Enable 7 through 1

These bits enable autovectoring for interrupts 7, 6, 5, 4, 3, 2, and 1.

0 = No autovector.

MOTOROLA MC68306 USER'S MANUAL 5-5

1 = Autovector.

5.2.4.2 INTERRUPT STATUS REGISTER. An enabled, active interrupt appears as a one
in the interrupt status register, regardless of the active voltage level programmed at reset.
This register is read-only, writes to this register are ignored.

FFFFFFF8/9

1514131211109876543210

IRQT IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQD IX7 IX6 IX5 IX4 IX3 IX 2 IX1

RESE

T:

0

0 0 0 0 0 0 0 IRQ7 PB7/IRQ6PB6/IRQ5IRQ4 PB5/IRQ3PB4/IRQ2IRQ1

0

SUPERVISOR ONLY

IRQT—DUART Timer Interrupt State

0 = No interrupt.
1 = Interrupt asserted.

IRQ7–1—Interrupt Request 7 through 1

These bits indicate interrupt status for the external interrupts 7, 6, 5, 4, 3, 2, and 1.

0 = No interrupt.
1 = Interrupt asserted.

IRQD—DUART Interrupt State

This bit indicates the DUART interrupt state.

0 = No DUART interrupt.
1 = DUART interrupt asserted

IX7–1—Reset (inactive) level of external interrupts 7 through 1.

0 = Active high interrupt pin.
1 = Active low interrupt pin.

5.2.5 I/O Port Registers

The following paragraphs describe the registers controlling the parallel ports. All port pins
are reset to input by a system reset, so pullup or pulldown resistors should be added
externally as needed. To enable a port A bit as an output, write a one to the appropriate
bit position of the port direction register. If a bit is programmed as an output, the data
written to the port data register appears in true form at the pin. The data read back from
the port pins register is the same level as appears at the pin. The data read from the port
data register is the last value written to the register, regardless of the level at the pin. The
port data register is not affected by any reset, so it should be initialized before enabling
any bits as outputs.

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Port B pins can be individually programmed as either IRQ, IACK or parallel port signals.
To use any of the port B pins PB7–PB4 as interrupt request signals (IRQ6, IRQ5, IRQ3,
IRQ2) be sure the bit is programmed as an input. Interrupt enables are provided for each
interrupt level.

To use any of the port B pins PB3–PB0 as IACK6, IACK5, IACK3, or IACK2, program the
port data bit and the autovector bit to zero.

To use any of the port B pins PB3–PB0 as port inputs, ensure that the autovector bit is
one.

Open-drain or open-source operation can be emulated by programming the appropriate
fixed data (e.g. 0 = open-drain) and toggling the direction control. PB7–PB4 pins can be
programmed as outputs even when enabled as interrupt inputs, allowing inputs to be
tested or emulated if the interrupt is open-drain or open-source. The active interrupt level
is the inverse of the IX register bit.

5.2.5.1 PORT PINS REGISTER

FFFFFFF4/5

1514131211109876543210

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

RESE

T:

PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PA7

SUPERVISOR ONLY

The port pin register bits are the data at the port pins, regardless of pin direction. The
port pins register is read-only, writes are ignored.

5.2.5.2 PORT DIRECTION REGISTER

FFFFFFF2/3

1514131211109876543210

PADIR7PADIR6PADIR5PADIR4PADIR3PADIR2PADIR1PADIR0PBDIR7PBDIR6PBDIR5 PBDIR4 PBDIR3 PBDIR2 PBDIR1PBDIR

0

RESE

T:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

SUPERVISOR ONLY

The port direction register bits determine the direction of data flow at the port pins.

PADIR7–0—Port A Direction Register Bit 7–0

This bit determines the direction of data flow at port A pins 7 through 0.

0 = Input.
1 = Output.

PBDIR7–0—Port B Direction Register Bit 7–0

MOTOROLA MC68306 USER'S MANUAL 5-7

This bit determines the direction of data flow at port B pins 7–0.

0 = Input.
1 = Output.

5.2.5.3 PORT DATA REGISTER. The port data register bits return the value as written,
regardless of the direction register and pin state. For pins configured as outputs, the
corresponding value in the port data register is driven externally.

FFFFFFF0/1

1514131211109876543210

PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0

RESE

T:

U

U

U U U U U U U U U U U U U U

SUPERVISOR ONLY

PAD7–0—Port A Data Bit 7 through 0.
PBD7–0—Port B Data Bit 7 through 0.

5.2.6 Chip Selects

The chip-select outputs are all active-low decodes of the high fifteen internal address bits
(A31–A17), the three function code bits, and the read/write cycle type. The active duration
of any chip select is the period of the address strobe low and either a data strobe or
read/write low. Thus there are separate chip select pulses for the read and write portions
of a read-modify-write cycle.

The four mask bits (CSM3–CSM0) are decoded to an n-of-15 mask, where n is the binary
value of CSM3–CSM0. On every bus cycle, the n most significant address bits of the
range A31–A17 are compared, and the remaining less significant bits are ignored.

The fifteen address bits are first masked by each chip select mask, then compared with
each chip select base address (CSA31–CSA17). All CSAx bits not used in the comparison
must be zero. The function code is matched with the CSFC qualifiers, and the cycle type
is matched with the CSR/CSW qualifiers. If all three qualifiers are successful for any chip
select, the cycle is a hit.

If the cycle hits multiple chip selects, the lowest numbered chip select has priority. All chip
selects have priority over DRAM. After reset, CS0 responds to the entire 4 Gbyte address
space, except for the range dedicated to internal resources, i.e., CS0 responds to
00000000–FFFFEFFF. The other chip selects are not affected by any reset, and must be
explicitly programmed. This applies to all chip selects, whether used or not.

5-8 MC68306 USER'S MANUAL MOTOROLA

NOTE

Unused chip selects must be disabled to prevent interference
with other chip selects, DRAM, or externally decoded
resources.

There are three ways to disable a chip select, corresponding to the three match
conditions:

1. All CSFCx bits are zero

2. Both CSW/CSR are zero

3. Any unused CSAx bit is one.

Chip selects 7 through 4 are still matched even if running in address mode (AMODE = 0).
They can be disabled, or they can be used to provide automatic DTACK timing for
externally decoded resources.

If more decodes are necessary than are supplied on the MC68306, one of the existing
chip selects should be used (Figure 5-1) to enable the external decoding, since some
signals used to qualify the chip selects are not available externally.

The registers listed below allow the base address, range, and cycle duration of each chip
select to be independently programmed. The chip select configuration registers do not
support byte writes. The registers can be written as either 16-bit or 32-bit, but 32-bit
accesses are preferred. Any write access affects all 16 bits of the high half or low half
register. Only chip select 0 is affected by reset.

5.2.6.1 CHIP SELECT CONFIGURATION REGISTERS (HIGH HALF)

FFFFFFC0 (CS0)

1514131211109876543210

CSA31 CSA30CSA29CSA28CSA27CSA26CSA25CSA24CSA23CSA22 CSA21 CSA20 CSA19 CSA18 CSA17 CSW

RESE

T:

FFFFFFDC (CS7), FFFFFFD8 (CS6), FFFFFFD4 (CS5), FFFFFFD0 (CS4), FFFFFFCC (CS3), FFFFFFC8 (CS2),
FFFFFFC4 (CS1)

1514131211109876543210

CSA31 CSA30CSA29CSA28CSA27CSA26CSA25CSA24CSA23CSA22 CSA21 CSA20 CSA19 CSA18 CSA17 CSW

RESE

T:
U

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

0

SUPERVISOR ONLY

U U U U U U U U U U U U U U U

SUPERVISOR ONLY

CSA31–CSA17—Chip Select Address

This bit field selects the base address for each chip select.

MOTOROLA MC68306 USER'S MANUAL 5-9

CSW—Chip Select Write

This bit determines whether write cycles are permitted to chip select space. If read and
write cycles are both inhibited, chip select is inhibited.

0 = Write cycles are inhibited to chip select space
1 = Write cycles are permitted to chip select space

5.2.6.2 CHIP SELECT CONFIGURATION REGISTERS (LOW HALF)

FFFFFFC2 (CS0)

1514131211109876543210

CSR CSFC6CSFC5— — CSFC2CSFC1— CSM3 CSM2 CSM1 CSM0 CSDT3 CSDT2 CSDT1CSDT

0

RESE

T:

FFFFFFDE (CS7), FFFFFFDA (CS6), FFFFFFD6 (CS5), FFFFFFD2 (CS4), FFFFFFCE (CS3), FFFFFFCA (CS2),
FFFFFFC6 (CS1)

1514131211109876543210

CSR CSFC6CSFC5— — CSFC2CSFC1— CSM3 CSM2 CSM1 CSM0 CSDT3 CSDT2 CSDT1CSDT

RESE

T:

U

1 1 1 1 1 1 1 0 0 0 0 1 1 1 0

0

SUPERVISOR ONLY

0

U U U U U U U U U U U U U U U

SUPERVISOR ONLY

CSR—Chip Select Read

This bit determines whether read cycles are permitted to chip select space. If read and
write cycles are both inhibited, chip select is inhibited.

0 = Read cycles are inhibited to chip select space
1 = Read cycles are permitted to chip select space

CSFC 6, 5, 2, 1—Chip Select Function Code Enable

This bit determines which function code accesses are permitted to chip select space. If
all function code cycles are inhibited, chip select is inhibited.

0 = Function code ‘n’ cycles are inhibited to chip select space
1 = Function code ‘n’ cycles are permitted to chip select space

CSM3–0—Chip Select Address Match

This field determines which chip select bits must match address bits for chip select to
occur. CSA bits not included in match must be set to zero, or else this chip select is
inhibited.

0000 = A31–A17 ignored in chip select address match
0001 = A31 must match CSA31; A30–A17 ignored in chip select address match
0010 = A31–A30 must match CSA31–CSA30; A29–A17 ignored in chip select

address match

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