MOTOROLA MC68040V Technical data

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MOTOROLA
by MC68040V/D
SEMICONDUCTOR
PRODUCT INFORMATION
MC68040V
Third-Generation 32-Bit Low-Power Microprocessor
The MC68040V is a high-performance, 32-bit, 3.3-V, static microprocessor that provides a low-power mode of operation. The MC68040V is MC68LC040 compatible, featuring dual on-chip caches, fully independent instruction and data demand-paged memory management units (MMUs), and a pipelined integer unit. A high degree of instruction execution parallelism is achieved through the use of a full internal Harvard architecture, multiple internal buses, and independent execution units. Accessed through the LPSTOP instruction, a low ­power mode of operation is provided that allows for full power-down capability. The operating current is further reduced by the use of a 3.3-V power supply. The 3.3-V power supply and the low-power mode reduce system power usage dramatically. The functionality provided by the MC68040V makes it the ideal choice for a range of high-performance, power-sensitive, general computing and embedded processing applications.
The high level of integration results in high performance while reducing overall system power consumption for the MC68040V. Complete code compatibility with the MC68000 family allows the designer to utilize existing code and past experience to bring products to market quickly. Additionally, a broad base of established development tools, including real-time kernels, operating systems, languages, and applications, assist in product development. Figure 1 shows a simplified block diagram of the MC68040V.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© MOTOROLA INC., 1993
INSTRUCTION DATA BUS
INSTRUCTION
FETCH
DECODE
EFFECTIVE
ADDRESS
CALCULATE
EFFECTIVE
ADDRESS
FETCH
EXECUTE
WRITE-BACK
INTEGER
UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE/ACCESS/SNOOP
CONTROLLER
INSTRUCTION MEMORY MANAGEMENT UNIT
DATA MEMORY MANAGEMENT UNIT
CACHE/ACCESS/SNOOP
CONTROLLER
DATA
ATC
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
DATA
CACHE
INSTRUCTION
ADDRESS
DATA
ADDRESS
B U
ADDRESS
S C
O N T R O L L E R
BUS
DATA
BUS
BUS
CONTROL
SIGNALS
Figure 1. MC68040V Simplified Block Diagram
The primary features of the MC68040V are as follows:
• MC68040 Integer Performance —26.1 MIPS at 25 MHz and 34.8 MIPS at 33 MHz
• Independent Instruction and Data MMUs
• Dual 4-Kbyte On-chip Caches — Separate Data and Instruction Cache
— Simultaneous Access
• Bus Snooping — Multi-Master and Multi-Processor Support
— MC68LC040-Compatible Function
• Full 32-Bit Nonmultiplexed Address and Data Bus — 32-Bit Bus Maximizes Data Throughput
— Nonmultiplexed Bus Simplifies Design — Provides for Highest Possible Performance
• Concurrent Operation of Integer Unit, MMUs, Caches, and Bus Controller Provides High Performance
• Power Consumption Control — Static HCMOS Technology Reduces Power in Normal Operation
— Low-Voltage Operation at 3.3 V ±300 mV — LPSTOP Provides an Idle State for Lowest Standby Current
• 0–33 MHz
• 184-Pin Ceramic Quad Flat Pack
2 MC68040V PRODUCT INFORMATION MOTOROLA
SIGNALS
Figure 2 shows the MC68040V signals in their functional groups. Three signals have been added to the MC68040V: system clock disable (SCD), loss of clock (LOC), and low-frequency operations (LFO).
ADDRESS
BUS
DATA BUS
TRANSFER
ATTRIBUTES
MASTER
TRANSFER
CONTROL
SLAVE
TRANSFER
CONTROL
A31–A0
D31–D0
TT0 TT1 TM0 TM1 TM2
TLN0
TLN1 UPA0 UPA1
R/W
SIZ0
SIZ1 LOCK
LOCKE CIOUT
TS
TIP
TA
TEA
TCI
TBI
MC68040V
SC0 SC1
M I
BR BG BB
CDIS MDIS RSTI RSTO
IPL0 IPL1 IPL2
IPEND
AVEC
PST0 PST1 PST2 PST3 BCLK SCD LOC LFO
TCK TMS TDI
TDO TRST JS0
BUS SNOOP CONTROL  AND RESPONSE
BUS ARBITRATION
PROCESSOR  CONTROL
INTERRUPT  CONTROL
STATUS AND  CLOCKS
TEST
V
CC
GND
POWER SUPPLY
Figure 2. MC68040V Functional Signal Groups
MOTOROLA MC68040V PRODUCT INFORMATION 3
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