MOTOROLA MC68030 User Guide
查询MC68030FE20供应商
MOTOROLA
MC68030
ENHANCED 32-BIT
MICROPROCESSOR
USER’S MANUAL
Third Edition
MOTOROLA INC., 1992
PREFACE
The
MC68030 User's Manual
MC68030 32-bit second-generation enhanced microprocessor. The manual consists of the
following sections and appendix. For detailed information on the MC68030 instruction set
refer to M68000PM/AD,
Section 1. Introduction
Section 2. Data Organization and Addressing Capabilities
Section 3. Instruction Set Summary
Section 4. Processing States
describes the capabilities, operation, and programming of the
M68000 Family Programmer's Reference Manual.
Section 5. Signal Description
Section 6. On-Chip Cache Memories
Section 7. Bus Operation
Section 8. Exception Processing
Section 9. Memory Management Unit
Section 10. Coprocessor Interface Description
Section 11. Instruction Execution Timing
Section 12. Applications Information
Section 13. Electrical Characteristics
Section 14. Ordering Information and Mechanical Data
Appendix A. M68000 Family Summary
Index
NOTE
In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate
indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they represent.
The audience of this manual includes systems designers, systems programmers, and
applications programmers. Systems designers need some knowledge of all sections, with
particular emphasis on Sections 1, 5, 6, 7, 13, 14, and Appendix A. Designers who
implement a coprocessor for their system also need a thorough knowledge of Section 10.
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Systems programmers should become familiar with Sections 1, 2, 3, 4, 6, 8, 9, 11, and
Appendix A. Applications programmers can find most of the information they need in
Sections 1, 2, 3, 4, 9, 11, 12, and Appendix A.
From a different viewpoint, the audience for this book consists of users of other M68000
Family members and those who are not familiar with these microprocessors. Users of the
other family members can find references to similarities to and differences from the other
Motorola microprocessors throughout the manual. However, Section 1 and Appendix A
specifically identify the MC68030 within the rest of the family and contrast its differences.
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TABLE OF CONTENTS
Paragraph
Title
Number
Section 1
Introduction
1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 MC68030 Extensions to the M68000 Family . . . . . . . . . . . . . . . . . . . 1-4
1.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Data Types and Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.5 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6 Virtual Memory and Virtual Machine Concepts . . . . . . . . . . . . . . . . . 1-12
1.6.1 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.6.2 Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.7 The Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.8 Pipelined Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.9 The Cache Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Section 2
Data Organization and Addressing Capabilities
2.1 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Organization of Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.1 Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.2 Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Organization of Data in Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.4.1 Data Register Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4.2 Address Register Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.3 Address Register Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.4 Address Register Indirect with Postincrement Mode. . . . . . . . . . . . 2-10
2.4.5 Address Register Indirect with Predecrement Mode. . . . . . . . . . . . 2-11
2.4.6 Address Register Indirect with Displacement Mode . . . . . . . . . . . . 2-12
2.4.7 Address Register Indirect with Index (8-Bit Displacement) Mode . . 2-12
2.4.8 Address Register Indirect with Index (Base Displacement) Mode. . 2-13
2.4.9 Memory Indirect Postindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.10 Memory Indirect Preindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.11 Program Counter Indirect with Displacement Mode . . . . . . . . . . . . 2-16
2.4.12 Program Counter Indirect with Index (8-Bit Displacement) Mode . . 2-16
2.4.13 Program Counter Indirect with Index (Base Displacement) Mode. . 2-17
2.4.14 Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . 2-18
2.4.15 Program Counter Memory Indirect Preindexed Mode. . . . . . . . . . . 2-19
2.4.16 Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.17 Absolute Long Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.18 Immediate Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5 Effective Address Encoding Summary. . . . . . . . . . . . . . . . . . . . . . . . 2-22
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Paragraph
Title
Number
2.6 Programmer`s View of Addressing Modes. . . . . . . . . . . . . . . . . . . . . 2-24
2.6.1 Addressing Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.6.2 General Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . 2-31
2.7 M68000 Family Addressing Compatibility . . . . . . . . . . . . . . . . . . . . . 2-36
2.8 Other Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.8.1 System Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.8.2 User Program Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
2.8.3 Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Section 3
Instruction Set Summary
3.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.2 Integer Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.3 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.4 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.5 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.6 Bit Field Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.7 Binary–coded Decimal Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.8 Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.9 System Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.10 Memory Management Unit Instructions. . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.11 Multiprocessor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.3 Integer Condition Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.1 Condition Code Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.2 Conditional Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.5 Instruction Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.5.1 Using the CAS and CAS2 Instructions . . . . . . . . . . . . . . . . . . . . . . 3-25
3.5.2 Nested Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.5.3 Bit Field Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.5.4 Pipeline Synchronization with the Nop Instruction. . . . . . . . . . . . . . 3-32
Page
Number
Section 4
Processing States
4.1 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.1 Supervisor Privilege Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.1.2 User Privilege Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.3 Changing Privilege Level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2 Address Space Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
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Paragraph
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4.3.1 Exception Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.2 Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Section 5
Signal Description
5.1 Signal Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Function Code Signals (FC0–FC2) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.3 Address Bus (A0–A31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4 Data Bus (D0–D31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.5 Transfer Size Signals (SIZ0, SIZ1). . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.6 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.6.1 Operand Cycle Start (OCS
5.6.2 External Cycle Start (ECS
5.6.3 Read/Write (R/W
5.6.4 Read-Modify-Write Cycle (RMC
5.6.5 Address Strobe (AS
5.6.6 Data Strobe (DS
5.6.7 Data Buffer Enable (DBEN
5.6.8 Data Transfer and Size Acknowledge (DSACK0
5.6.9 Synchronous Termination (STERM
5.7 Cache Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.7.1 Cache Inhibit Input (CIIN
5.7.2 Cache Inhibit Output (CIOUT
5.7.3 Cache Burst Request (CBREQ
5.7.4 Cache Burst Acknowledge (CBACK
5.8 Interrupt Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.1 Interrupt Priority Level Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.8.2 Interrupt Pending (IPEND
5.8.3 Autovector (AVEC
5.9 Bus Arbitration Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.9.1 Bus Request (BR
5.9.2 Bus Grant (BG
5.9.3 Bus Grant Acknowledge (BGACK
5.10 Bus Exception Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.10.1 Reset (RESET
5.10.2 Halt (HALT
5.10.3 Bus Error (BERR
5.11 Emulator Support Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.11.1 Cache Disable (CDIS
5.11.2 MMU Disable (MMUDIS
5.11.3 Pipeline Refill (REFILL
5.11.4 Internal Microsequencer Status (STATUS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
). . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
, DSACK1). . . . . . 5-6
) . . . . . . . . . . . . . . . . . . . . . . . . 5-6
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
). . . . . . . . . . . . . . . . . . . . . . . . 5-7
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
) . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
). . . . . . . . . . . . . . . . . . . 5-10
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Number
5.12 Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.13 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.14 Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Section 6
On-Chip Cache Memories
6.1 On-Chip Cache Organization and Operation . . . . . . . . . . . . . . . . . . . 6-3
6.1.1 Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.1.2 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.1.2.1 Write Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.1.2.2 Read-Modify-Write Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.1.3 Cache Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.1.3.1 Single Entry Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.1.3.2 Burst Mode Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.2 Cache Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.3 Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.3.1 Cache Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6.3.1.1 Write Allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.1.2 Data Burst Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.1.3 Clear Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.1.4 Clear Entry in Data Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.3.1.5 Freeze Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.1.6 Enable Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.1.7 Instruction Burst Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.1.8 Clear Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.1.9 Clear Entry in Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.3.1.10 Freeze Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.3.1.11 Enable Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.3.2 Cache Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Page
Number
Section 7
Bus Operation
7.1 Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Bus Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.2 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.1.3 Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
7.1.4 Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.1.5 Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.1.6 Data Buffer Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.1.7 Bus Cycle Termination Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2 Data Transfer Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.1 Dynamic Bus Sizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
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7.2.2 Misaligned Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment . . . . . . 7-19
7.2.4 Address, Size, and Data Bus Relationships . . . . . . . . . . . . . . . . . . 7-22
7.2.5 MC68030 versus MC68020 Dynamic Bus Sizing . . . . . . . . . . . . . . 7-24
7.2.6 Cache Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
7.2.7 Cache Interactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.2.8 Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
7.2.9 Synchronous Operation with DSACKx
7.2.10 Synchronous Operation with STERM
7.3 Data Transfer Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
7.3.1 Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
7.3.2 Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
7.3.3 Asynchronous Read-Modify-Write Cycle. . . . . . . . . . . . . . . . . . . . . 7-43
7.3.4 Synchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48
7.3.5 Synchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51
7.3.6 Synchronous Read-Modify-Write Cycle. . . . . . . . . . . . . . . . . . . . . . 7-54
7.3.7 Burst Operation Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-59
7.4 CPU Space Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-68
7.4.1 Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . 7-69
7.4.1.1 Interrupt Acknowledge Cycle — Terminated Normally . . . . . . . . 7-70
7.4.1.2 Autovector Interrupt Acknowledge Cycle. . . . . . . . . . . . . . . . . . . 7-71
7.4.1.3 Spurious Interrupt Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-74
7.4.2 Breakpoint Acknowledge Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-74
7.4.3 Coprocessor Communication Cycles . . . . . . . . . . . . . . . . . . . . . . . 7-74
7.5 Bus Exception Control Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-75
7.5.1 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-82
7.5.2 Retry Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-89
7.5.3 Halt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91
7.5.4 Double Bus Fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-94
7.6 Bus Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-95
7.7 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-96
7.7.1 Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-98
7.7.2 Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
7.7.3 Bus Grant Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-100
7.7.4 Bus Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-100
7.8 Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-103
. . . . . . . . . . . . . . . . . . . . . . 7-28
. . . . . . . . . . . . . . . . . . . . . . . 7-29
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Section 8
Exception Processing
8.1 Exception Processing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 Reset Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.1.2 Bus Error Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
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8.1.3 Address Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.1.4 Instruction Trap Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.1.5 Illegal Instruction and Unimplemented Instruction Exceptions . . . . 8-9
8.1.6 Privilege Violation Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.1.7 Trace Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.1.8 Format Error Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.1.9 Interrupt Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
8.1.10 MMU Configuration Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
8.1.11 Breakpoint Instruction Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.1.12 Multiple Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
8.1.13 Return from Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
8.2 Bus Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
8.2.1 Special Status Word (SSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
8.2.2 Using Software to Complete the Bus Cycles. . . . . . . . . . . . . . . . . . 8-29
8.2.3 Completing the Bus Cycles with Rte . . . . . . . . . . . . . . . . . . . . . . . . 8-31
8.3 Coprocessor Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
8.4 Exception Stack Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Section 9
Memory Management Unit
9.1 Translation Table Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
9.1.1 Translation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.1.2 Translation Table Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9.2 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.2.1 General Flow for Address Translation. . . . . . . . . . . . . . . . . . . . . . . 9-13
9.2.2 Effect of RESET
9.2.3 Effect of MMUDIS
9.3 Transparent Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
9.4 Address Translation Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
9.5 Translation Table Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.5.1 Descriptor Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.5.1.1 Descriptor Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
9.5.1.2 Root Pointer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9.5.1.3 Short-Format Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.5.1.4 Long-Fomat Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9.5.1.5 Short-Format Early Termination Page Descriptor . . . . . . . . . . . . 9-25
9.5.1.6 Long-Format Early Termination Page Descriptor . . . . . . . . . . . . 9-25
9.5.1.7 Short-Format Page Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.5.1.8 Long-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.5.1.9 Short-Format Invalid Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9.5.1.10 Long-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9.5.1.11 Short-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
On MMU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
On Address Translation. . . . . . . . . . . . . . . . . . . 9-15
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9.5.1.12 Long-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.5.2 General Table Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9.5.3 Variations in Translation Table Structure . . . . . . . . . . . . . . . . . . . . 9-33
9.5.3.1 Early Termination and Contiguous Memory. . . . . . . . . . . . . . . . . 9-33
9.5.3.2 Indirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
9.5.3.3 Table Sharing Between Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.5.3.4 Paging of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37
9.5.3.5 Dynamic Allocation of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9.5.4 Detail of Table Search Operations . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
9.5.5 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
9.5.5.1 Function Code Lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45
9.5.5.2 Supervisor Translation Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
9.5.5.3 Supervisor Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
9.5.5.4 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
9.6 MC68030 and MC68851 Mmu Differences . . . . . . . . . . . . . . . . . . . . 9-51
9.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52
9.7.1 Root Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52
9.7.2 Translation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
9.7.3 Transparent Translation Registers . . . . . . . . . . . . . . . . . . . . . . . . . 9-57
9.7.4 MMU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59
9.7.5 Register Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 9-61
9.7.5.1 Register Side Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-61
9.7.5.2 MMU Status Register Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . 9-61
9.7.5.3 MMU Configuration Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-62
9.8 Mmu Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-63
9.9 Defining and Using Page Tables in An Operating System. . . . . . . . . 9-65
9.9.1 Root Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-65
9.9.2 Task Memory Map Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-66
9.9.3 Impact of MMU Features On Table Definition. . . . . . . . . . . . . . . . . 9-68
9.9.3.1 Number of Table Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-68
9.9.3.2 Initial Shift Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-69
9.9.3.3 Limit Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-70
9.9.3.4 Early Termination Page Descriptors . . . . . . . . . . . . . . . . . . . . . . 9-70
9.9.3.5 Indirect Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-71
9.9.3.6 Using Unused Descriptor Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-71
9.10 An Example of Paging Implementation in an Operating System . . . . 9-72
9.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-72
9.10.2 Allocation Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-78
9.10.3 Bus Error Handler Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-82
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Section 10
Coprocessor Interface Description
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10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1.1 Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.2 Concurrent Operation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.1.3 Coprocessor Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.1.4 Coprocessor System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.4.1 Coprocessor Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.4.2 Processor-Coprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.1.4.3 Coprocessor Interface Register Selection. . . . . . . . . . . . . . . . . . 10-8
10.2 Coprocessor Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.2.1 Coprocessor General Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.2.1.1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.2.1.2 Protocol.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.2.2 Coprocessor Conditional Instructions . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.2.2.1 Branch On Coprocessor Condition Instruction. . . . . . . . . . . . . . . 10-13
10.2.2.1.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.2.2.1.2 Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.2.2.2 Set On Coprocessor Condition Instruction. . . . . . . . . . . . . . . . . . 10-15
10.2.2.2.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.2.2.2.2 Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.2.2.3 Test Coprocessor Condition, Decrement and Branch Instruction 10-17
10.2.2.3.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.2.2.3.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.2.2.4 Trap On Coprocessor Condition.. . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.2.2.4.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
10.2.2.4.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10.2.3 Coprocessor Save and Restore Instructions. . . . . . . . . . . . . . . . . . 10-20
10.2.3.1 Coprocessor Internal State Frames. . . . . . . . . . . . . . . . . . . . . . . 10-20
10.2.3.2 Coprocessor Format Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.2.3.2.1 Empty/Reset Format Word.. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.2.3.2.2 Not Ready Format Word.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.2.3.2.3 Invalid Format Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.2.3.2.4 Valid Format Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.2.3.3 Coprocessor Context Save Instruction . . . . . . . . . . . . . . . . . . . . 10-24
10.2.3.3.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
10.2.3.3.2 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.2.3.4 Coprocessor Context Restore Instruction.. . . . . . . . . . . . . . . . . . 10-27
10.2.3.4.1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
10.2.3.4.2 Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28
10.3 Coprocessor Interface Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10.3.1 Response CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10.3.2 Control CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.3.3 Save CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
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10.3.4 Restore CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.3.5 Operation Word CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.3.6 Command CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.3.7 Condition CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10.3.8 Operand CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.3.9 Register Select CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
10.3.10 Instruction Address CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.3.11 Operand Address CIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.4 Coprocessor Response Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.4.1 ScanPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.4.2 Coprocessor Response Primitive General Format . . . . . . . . . . . . . 10-35
10.4.3 Busy Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10.4.4 Null Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
10.4.5 Supervisor Check Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10.4.6 Transfer Operation Word Primitive . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10.4.7 Transfer from Instruction Stream Primitive . . . . . . . . . . . . . . . . . . . 10-41
10.4.8 Evaluate and Transfer Effective Address Primitive . . . . . . . . . . . . . 10-42
10.4.9 Evaluate Effective Address and Transfer Data Primitive. . . . . . . . . 10-43
10.4.10 Write to Previously Evaluated Effective Address Primitive . . . . . . . 10-46
10.4.11 Take Address and Transfer Data Primitive . . . . . . . . . . . . . . . . . . . 10-48
10.4.12 Transfer to/from Top of Stack Primitive. . . . . . . . . . . . . . . . . . . . . . 10-49
10.4.13 Transfer Single Main Processor Register Primitive. . . . . . . . . . . . . 10-50
10.4.14 Transfer Main Processor Control Register Primitive . . . . . . . . . . . . 10-50
10.4.15 Transfer Multiple Main Processor Registers Primitive. . . . . . . . . . . 10-52
10.4.16 Transfer Multiple Coprocessor Registers Primitive . . . . . . . . . . . . . 10-52
10.4.17 Transfer Status Register and ScanPC Primitive . . . . . . . . . . . . . . . 10-55
10.4.18 Take Pre-Instruction Exception Primitive. . . . . . . . . . . . . . . . . . . . . 10-56
10.4.19 Take Mid-Instruction Exception Primitive . . . . . . . . . . . . . . . . . . . . 10-58
10.4.20 Take Post-Instruction Exception Primitive. . . . . . . . . . . . . . . . . . . . 10-60
10.5 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-61
10.5.1 Coprocessor-Detected Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 10-61
10.5.1.1 Coprocessor-Detected Protocol Violations . . . . . . . . . . . . . . . . . 10-62
10.5.1.2 Coprocessor-Detected Illegal Command or Condition Words. . . 10-63
10.5.1.3 Coprocessor Data-Processing Exceptions . . . . . . . . . . . . . . . . . 10-63
10.5.1.4 Coprocessor System-Related Exceptions . . . . . . . . . . . . . . . . . . 10-64
10.5.1.5 Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-64
10.5.2 Main-Processor-Detected Exceptions. . . . . . . . . . . . . . . . . . . . . . . 10-65
10.5.2.1 Protocol Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-65
10.5.2.2 F-Line Emulator Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-68
10.5.2.3 Privilege Violations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69
10.5.2.4 cpTRAPcc Instruction Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-69
10.5.2.5 Trace Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-70
Page
Number
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Paragraph
Title
Number
10.5.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-71
10.5.2.7 Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-71
10.5.2.8 Address and Bus Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-72
10.5.3 Coprocessor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-72
10.6 Coprocessor Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-72
Section 11
Instruction Execution Timing
11.1 Performance Tradeoffs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Resource Scheduling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.1 Microsequencer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.2 Instruction Pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2.3 Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.4 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.5 Bus Controller Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.2.5.1 Instruction Fetch Pending Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.2.5.2 Write Pending Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.2.5.3 Micro Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.2.6 Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.3 Instruction Execution Timing Calculations . . . . . . . . . . . . . . . . . . . . . 11-6
11.3.1 Instruction-Cache Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.3.2 Overlap and Best Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.3.3 Average No-Cache Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.3.4 Actual Instruction-Cache-Case Execution Time Calculations . . . . . 11-11
11.4 Effect of Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.5 Effect of Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.6 Instruction Timing Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24
11.6.1 Fetch Effective Address (fea) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
11.6.2 Fetch Immediate Effective Address (fiea) . . . . . . . . . . . . . . . . . . . . 11-28
11.6.3 Calculate Effective Address (cea) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30
11.6.4 Calculate Immediate Effective Address (ciea). . . . . . . . . . . . . . . . . 11-32
11.6.5 Jump Effective Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
11.6.6 MOVE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
11.6.7 Special-Purpose Move Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 11-39
11.6.8 Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40
11.6.9 Immediate Arithmetical/Logical Instructions . . . . . . . . . . . . . . . . . . 11-42
11.6.10 Binary-Coded Decimal and Extended Instructions . . . . . . . . . . . . . 11-43
11.6.11 Single Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44
11.6.12 Shift/Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45
11.6.13 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46
11.6.14 Bit Field Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 11-47
11.6.15 Conditional Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
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Paragraph
Title
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11.6.16 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
11.6.17 Exception-Related Instructions and Operations . . . . . . . . . . . . . . . 11-50
11.6.18 Save and Restore Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51
11.7 Address Translation Tree Search Timing. . . . . . . . . . . . . . . . . . . . . . 11-51
11.7.1 MMU Effective Address Calculation . . . . . . . . . . . . . . . . . . . . . . . . 11-58
11.7.2 MMU Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-60
11.8 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-61
11.9 Bus Arbitration Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62
Section 12
Applications Information
12.1 Adapting the MC68030 to MC68020 Designs . . . . . . . . . . . . . . . . . . 12-1
12.1.1 Signal Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.1.2 Hardware Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.3 Software Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.2 Floating-Point Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
12.3 Byte Select Logic for the MC68030 . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.4 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.4.1 Access Time Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.4.2 Burst Mode Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.5 Static RAM Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.5.1 A Two-Clock Synchronous Memory Bank Using SRAMS. . . . . . . . 12-18
12.5.2 A 2-1-1-1 Burst Mode Memory Bank Using SRAMS. . . . . . . . . . . . 12-24
12.5.3 A 3-1-1-1 Burst Mode Memory Bank Using SRAMS. . . . . . . . . . . . 12-27
12.6 External Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.6.1 Cache Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.6.2 Instruction-Only External Cache Implementations . . . . . . . . . . . . . 12-35
12.7 Debugging Aids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.7.1 Status and Refill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
12.7.2 Real-Time Instruction Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.8 Power and Ground Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
Page
Number
Section 13
Electrical Characteristics
13.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Thermal Characteristics — PGA Package. . . . . . . . . . . . . . . . . . . . . 13-1
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Paragraph
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Section 14
Ordering Information
and Mechanical Data
14.1 Standard MC68030 Ordering Information . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Pin Assignments — Pin Grid Array (RC Suffix) . . . . . . . . . . . . . . . . . 14-2
14.3 Pin Assignments — Ceramic Surface Mount (FE Suffix). . . . . . . . . . 14-3
14.4 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Appendix A
M68000 Family Summary
Page
Number
xxxvi
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MOTOROLA
LIST OF ILLUSTRATIONS
Figure
Number
1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 User Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1-3 Supervisor Programming Model Supplement. . . . . . . . . . . . . . . . . . . . . . . 1-7
1-4 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
2-1 Memory Operand Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-2 Memory Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-3 Single Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-4 Effective Address Specification Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-5 Using SIZE in the Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-6 Using Absolute Address with Indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2-7 Addressing Array Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-8 Using Indirect Absolute Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . 2-28
2-9 Accessing an Item in a Structure Using a Pointer . . . . . . . . . . . . . . . . . . . 2-28
2-10 Indirect Addressing, Suppressed Index Register. . . . . . . . . . . . . . . . . . . . 2-29
2-11 Preindexed Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
2-12 Postindexed Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-13 Preindexed Indirect Addressing with Outer Displacement. . . . . . . . . . . . . 2-30
2-14 Postindexed Indirect Addressing with Outer Displacement . . . . . . . . . . . . 2-31
2-15 M68000 Family Address Extension Words . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Title
Number
Page
3-1 Instruction Word General Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 Linked List Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3-3 Linked List Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3-4 Doubly Linked List Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3-5 Doubly Linked List Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
4-1 General Exception Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
5-1 Functional Signal Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
6-1 Internal Caches and the MC68030. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6-2 On-Chip Instruction Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6-3 On-Chip Data Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6-4 No-Write-Allocation and Write-Allocation Mode Examples . . . . . . . . . . . . 6-9
6-5 Single Entry Mode Operation — 8-Bit Port . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6-6 Single Entry Mode Operation — 16-Bit Port . . . . . . . . . . . . . . . . . . . . . . . 6-12
6-7 Single Entry Mode Operation — 32-Bit Port . . . . . . . . . . . . . . . . . . . . . . . 6-12
6-8 Single Entry Mode Operation — Misaligned Long Word and 8-Bit Port. . . 6-13
6-9 Single Entry Mode Operation — Misaligned Long Word and 16-Bit Port. . 6-14
6-10 Single Entry Mode Operation — Misaligned Long Word and 32-Bit
DSACKx Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
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Figure
Number
6-11 Burst Operation Cycles and Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6-12 Burst Filling Wraparound Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6-13 Deferred Burst Filling Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6-14 Cache Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6-15 Cache Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
7-1 Relationship between External and Internal Signals . . . . . . . . . . . . . . . . . 7-2
7-2 Asynchronous Input Sample Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7-3 Internal Operand Representation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7-4 MC68030 Interface to Various Port Sizes . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7-5 Example of Long-Word Transfer to Word Port. . . . . . . . . . . . . . . . . . . . . . 7-11
7-6 Long-Word Operand Write Timing (16-Bit Data Port) . . . . . . . . . . . . . . . . 7-12
7-7 Example of Word Transfer to Byte Port . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7-8 Word Operand Write Timing (8-Bit Data Port) . . . . . . . . . . . . . . . . . . . . . . 7-14
7-9 Misaligned Long-Word Transfer to Word Port Example. . . . . . . . . . . . . . . 7-15
7-10 Misaligned Long-Word Transfer to Word Port . . . . . . . . . . . . . . . . . . . . . . 7-16
7-11 Misaligned Cachable Long-Word Transfer from Word Port Example . . . . 7-17
7-12 Misaligned Word Transfer to Word Port Example . . . . . . . . . . . . . . . . . . . 7-17
7-13 Misaligned Word Transfer to Word Port. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
7-14 Example of Misaligned Cachable Word Transfer from Word Bus . . . . . . . 7-20
7-15 Misaligned Long-Word Transfer to Long-Word Port. . . . . . . . . . . . . . . . . . 7-20
7-16 Misaligned Write Cycles to Long-Word Port. . . . . . . . . . . . . . . . . . . . . . . . 7-21
7-17 Misaligned Cachable Long-Word Transfer from Long-Word Bus. . . . . . . . 7-22
7-18 Byte Data Select Generation for 16- and 32-Bit Ports . . . . . . . . . . . . . . . . 7-25
7-19 Asynchronous Long-Word Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . 7-32
7-20 Asynchronous Byte Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 7-32
7-21 Asynchronous Byte and Word Read Cycles — 32-Bit Port . . . . . . . . . . . . 7-33
7-22 Long-Word Read — 8-Bit Port with CIOUT
7-23 Long-Word Read — 16-Bit and 32-Bit Port . . . . . . . . . . . . . . . . . . . . . . . . 7-35
7-24 Asynchronous Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
7-25 Asynchronous Read-Write-Read Cycles — 32-Bit Port. . . . . . . . . . . . . . . 7-38
7-26 Asynchronous Byte and Word Write Cycles — 32-Bit Port . . . . . . . . . . . . 7-39
7-27 Long-Word Operand Write — 8-Bit Port. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40
7-28 Long-Word Operand Write — 16-Bit Port. . . . . . . . . . . . . . . . . . . . . . . . . . 7-41
7-29 Asynchronous Read-Modify-Write Cycle Flowchart. . . . . . . . . . . . . . . . . . 7-44
7-30 Asynchronous Byte Read-Modify-Write Cycle — 32-Bit Port
(TAS Instruction with CIOUT
7-31 Synchronous Long-Word Read Cycle Flowchart —
No Burst Allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-49
7-32 Synchronous Read with CIIN
7-33 Synchronous Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52
7-34 Synchronous Write Cycle with Wait States — CIOUT
or CIIN Asserted). . . . . . . . . . . . . . . . . . . . . 7-45
Asserted and CBACK Negated. . . . . . . . . . 7-50
Title
Number
Asserted. . . . . . . . . . . . . . . . . 7-34
Asserted . . . . . . . . 7-53
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LIST OF ILLUSTRATIONS (Continued)
Figure
Title
Number
7-35 Synchronous Read-Modify-Write Cycle Flowchart. . . . . . . . . . . . . . . . . . . 7-55
7-36 Synchronous Read-Modify-Write Cycle Timing — CIIN
7-37 Burst Operation Flowchart — Four Long Words Transferred. . . . . . . . . . . 7-62
7-38 Long-Word Operand Request from $07 with
Burst Request and Wait Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-63
7-39 Long-Word Operand Request from $07 with
Burst Request — CBACK
7-40 Long-Word Operand Request from $0E — Burst Fill Deferred . . . . . . . . . 7-65
7-41 Long-Word Operand Request from $07 with
Burst Request — CBACK
7-42 MC68030 CPU Space Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . 7-69
7-43 Interrupt Acknowledge Cycle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-71
7-44 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72
7-45 Autovector Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-73
7-46 Breakpoint Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-75
7-47 Breakpoint Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-76
7-48 Breakpoint Acknowledge Cycle Timing (Exception Signaled) . . . . . . . . . . 7-77
7-49 Bus Error without DSACKx
7-50 Late Bus Error with DSACKx
7-51 Late Bus Error with STERM
7-52 Long-Word Operand Request — Late BERR
7-53 Long-Word Operand Request — BERR
7-54 Asynchronous Late Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-90
7-55 Synchronous Late Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91
7-56 Late Retry Operation for a Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-92
7-57 Halt Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-93
7-58 Bus Synchronization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-96
7-59 Bus Arbitration Flowchart for Single Request. . . . . . . . . . . . . . . . . . . . . . . 7-98
7-60 Bus Arbitration Operation Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
7-61 Bus Arbitration State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-101
7-62 Single-Wire Bus Arbitration Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 7-103
7-63 Bus Arbitration Operation (Bus Inactive) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-104
7-64 Initial Reset Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-105
7-65 Processor-Generated Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-106
Negated Early. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
and CIIN Asserted . . . . . . . . . . . . . . . . . . . . . . 7-66
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-84
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-85
— Exception Taken. . . . . . . . . . . . . . . . . . . . 7-86
on Third Access . . . . . . . . . 7-87
on Second Access . . . . . . . . . . . 7-88
Asserted . . . . . . . 7-56
Page
Number
8-1 Reset Operation Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
8-2 Interrupt Pending Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8-3 Interrupt Recognition Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
8-4 Assertion of IPEND
8-5 Interrupt Exception Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8-6 Examples of Interrupt Recognition and Instruction Boundaries . . . . . . . . . 8-20
8-7 Breakpoint Instruction Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
MOTOROLA
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MC68030 USER’S MANUAL
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xl
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
8-8 RTE Instruction for Throwaway Four-Word Frame . . . . . . . . . . . . . . . . . . 8-26
8-9 Special Status Word (SSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
9-1 MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9-2 MMU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9-3 Translation Table Tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9-4 Example Translation Table Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
9-5 Example Translation Tree Layout in Memory. . . . . . . . . . . . . . . . . . . . . . . 9-8
9-6 Derivation of Table Index Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9-7 Example Translation Tree Using Different Format Descriptors . . . . . . . . . 9-12
9-8 Address Translation General Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9-9 Root Pointer Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
9-10 Short-Format Table Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9-11 Long-Format Table Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
9-12 Short-Format Page Descriptor and Short-Format Early
Termination Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
9-13 Long-Format Early Termination Page Descriptor. . . . . . . . . . . . . . . . . . . . 9-25
9-14 Long-Format Page Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9-15 Short-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26
9-16 Long-Format Invalid Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9-17 Short-Format Indirect Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
9-18 Long-Format Indirect Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
9-19 Simplified Table Search Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29
9-20 Five-Level Table Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
9-21 Example Translation Tree Using Contiguous Memory. . . . . . . . . . . . . . . . 9-35
9-22 Example Translation Tree Using Indirect Descriptors . . . . . . . . . . . . . . . . 9-36
9-23 Example Translation Tree Using Shared Tables . . . . . . . . . . . . . . . . . . . . 9-38
9-24 Example Translation Tree with Nonresident Tables. . . . . . . . . . . . . . . . . . 9-39
9-25 Detailed Flowchart of MMU Table Search Operation. . . . . . . . . . . . . . . . . 9-41
9-26 Table Search Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9-27 ATC Entry Creation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42
9-28 Limit Check Procedure Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43
9-29 Detailed Flowchart of Descriptor Fetch Operation . . . . . . . . . . . . . . . . . . . 9-44
9-30 Logical Address Map Using Function Code Lookup . . . . . . . . . . . . . . . . . 9-45
9-31 Example Translation Tree Using Function Code Lookup. . . . . . . . . . . . . . 9-46
9-32 Example Translation Tree Structure for Two Tasks. . . . . . . . . . . . . . . . . . 9-47
9-33 Exmple Logical Address Map with Shared Supervisor
and User Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49
9-34 Exmple Translation Tree Using S and WP Bits to Set Protection . . . . . . . 9-50
9-35 Root Pointer Register (CRP, SRP) Format . . . . . . . . . . . . . . . . . . . . . . . . 9-54
9-36 Translation Control Register (TC) Format . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
9-37 Transparent Translation Register (TT0 and TT1) Format . . . . . . . . . . . . . 9-57
Title
Number
Page
MC68030 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure
Title
Number
9-38 MMU Status Register (MMUSR) Format . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59
9-39 MMU Status Interpretation PTEST Level 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-62
9-40 MMU Status Interpretation PTEST Level 7 . . . . . . . . . . . . . . . . . . . . . . . . 9-63
10-1 F-Line Coprocessor Instruction Operation Word . . . . . . . . . . . . . . . . . . . . 10-4
10-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage. . 10-6
10-3 MC68030 CPU Space Address Encodings . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10-4 Coprocessor Address Map in MC68030 CPU Space. . . . . . . . . . . . . . . . . 10-8
10-5 Coprocessor Interface Register Set Map. . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10-6 Coprocessor General Instruction Format (cpGEN) . . . . . . . . . . . . . . . . . . 10-10
10-7 Coprocessor Interface Protocol for General Category Instructions . . . . . . 10-11
10-8 Coprocessor Interface Protocol for Conditional Category Instructions. . . . 10-13
10-9 Branch on Coprocessor Condition Instruction (cpBcc.W) . . . . . . . . . . . . . 10-14
10-10 Branch On Coprocessor Condition Instruction (cpBcc.L). . . . . . . . . . . . . . 10-14
10-11 Set On Coprocessor Condition (cpScc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10-12 Test Coprocessor Condition, Decrement and Branch
Instruction Format (cpDBcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10-13 Trap On Coprocessor Condition (cpTRAPcc) . . . . . . . . . . . . . . . . . . . . . . 10-18
10-14 Coprocessor State Frame Format in Memory . . . . . . . . . . . . . . . . . . . . . . 10-21
10-15 Coprocessor Context Save Instruction Format (cpSAVE) . . . . . . . . . . . . . 10-25
10-16 Coprocessor Context Save Instruction Protocol. . . . . . . . . . . . . . . . . . . . . 10-26
10-17 Coprocessor Context Restore Instruction Format (cpRESTORE) . . . . . . . 10-27
10-18 Coprocessor Context Restore Instruction Protocol . . . . . . . . . . . . . . . . . . 10-28
10-19 Control CIR Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10-20 Condition CIR Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
10-21 Operand Alignment for Operand CIR Accesses. . . . . . . . . . . . . . . . . . . . . 10-32
10-22 Coprocessor Response Primitive Format. . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10-23 Busy Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10-24 Null Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37
10-25 Supervisor Check Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40
10-26 Transfer Operation Word Primitive Format . . . . . . . . . . . . . . . . . . . . . . . . 10-41
10-27 Transfer from Instruction Stream Primitive Format . . . . . . . . . . . . . . . . . . 10-41
10-28 Evaluate and Transfer Effective Address Primitive Format . . . . . . . . . . . . 10-42
10-29 Evaluate Effective Address and Transfer Data Primitive . . . . . . . . . . . . . . 10-43
10-30 Write to Previously Evaluated EffectiveAddress Primitive Format. . . . . . . 10-46
10-31 Take Address and Transfer Data Primitive Format . . . . . . . . . . . . . . . . . . 10-48
10-32 Transfer To/From Top of Stack Primitive Format. . . . . . . . . . . . . . . . . . . . 10-49
10-33 Transfer Single Main Processor Register Primitive Format . . . . . . . . . . . . 10-50
10-34 Transfer Main Processor Control Register Primitive Format . . . . . . . . . . . 10-51
10-35 Transfer Multiple Main Processor Registers Primitive Format. . . . . . . . . . 10-52
10-36 Register Select Mask Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52
10-37 Transfer Multiple Coprocessor Registers Primitive Format . . . . . . . . . . . . 10-53
Page
Number
MOTOROLA
MC68030 USER’S MANUAL
xli
LIST OF ILLUSTRATIONS (Concluded)
Figure
Title
Number
10-38 Operand Format in Memory for Transfer to —(An) . . . . . . . . . . . . . . . . . . 10-54
10-39 Transfer Status Register and ScanPC Primitive Format . . . . . . . . . . . . . . 10-55
10-40 Take Pre-Instruction Exception Primitive Format. . . . . . . . . . . . . . . . . . . . 10-56
10-41 MC68030 Pre-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-57
10-42 Take Mid-Instruction Exception Primitive Format. . . . . . . . . . . . . . . . . . . . 10-58
10-43 MC68030 Mid-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-59
10-44 Take Post-Instruction Exception Primitive Format . . . . . . . . . . . . . . . . . . . 10-60
10-45 MC68030 Post-Instruction Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 10-60
11-1 Block Diagram – Eight Independent Resources. . . . . . . . . . . . . . . . . . . . . 11-3
11-2 Simultaneous Instruction Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11-3 Derivation of Instruction Overlap Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11-4 Processor Activity – Even Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
11-5 Processor Activity – Odd Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
12-1 Signal Routing for Adapting the MC68030 to MC68020 Designs . . . . . . . 12-2
12-2 32-Bit Data Bus Coprocessor Connection . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12-3 Chip-Select Generation PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12-4 PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12-5 Bus Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12-6 Example MC68030 Byte Select PAL System Configuration . . . . . . . . . . . 12-12
12-7 MC68030 Byte Select PAL Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12-8 Access Time Computation Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12-9 Example Two-Clock Read, Three-Clock Write Memory Bank . . . . . . . . . . 12-19
12-10 Example PAL Equations for Two-Clock Memory Bank . . . . . . . . . . . . . . . 12-20
12-11 Additional Memory Enable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12-12 Example Two-Clock Read and Write Memory Bank . . . . . . . . . . . . . . . . . 12-22
12-13 Example PAL Equation for Two-Clock Read and Write Memory Bank . . . 12-23
12-14 Example 2-1-1-1 Burst Mode Memory Bank at 20 MHz, 256K Bytes . . . . 12-25
12-15 Example 3-1-1-1 Pipelined Burst Mode Memory Bank at
20 MHz, 256K Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12-16 Additional Memory Enable Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
12-17 Example MC68030 Hardware Configuration with
External Physical Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12-18 Example Early Termination Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12-19 Normal Instruction Boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
12-20 Trace or Interrupt Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
12-21 Other Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
12-22 Processor Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12-23 Trace Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
12-24 PAL Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
12-25 Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45
Page
Number
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MC68030 USER’S MANUAL
MOTOROLA
LIST OF TABLES
Table
Title
Number
1-1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1-2 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2-1 IS–I/IS Memory Indirection Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
3-1 Data Movement Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-2 Integer Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3-3 Logical Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-4 Shift and Rotate Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-5 Bit Manipulation Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-6 Bit Field Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-7 BCD Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3-8 Program Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3-9 System Control Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3-10 MMU Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3-11 Multiprocessor Operations (Read-Modify-Write) . . . . . . . . . . . . . . . . . . . . 3-13
3-12 Condition Code Computations (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 3-15
3-13 Conditional Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3-14 Instruction Set Summary (Sheet 1 of 5). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Page
Number
4-1 Address Space Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
5-1 Signal Index (Sheet 1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-2 Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
7-1 DSACK
7-2 Size Signal Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7-3 Address OffsetEncodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7-4 Data Bus Requirements for Read Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7-5 MC68030 Internal to External Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7-6 Memory Alignment and Port Size Influence on Write Bus Cycles . . . . . . . 7-19
7-7 Data Bus Write Enable Signals for Byte, Word, and Long-Word Ports . . . 7-23
7-8 DSACK
7-9 STERM
8-1 Exception Vector Assignments (Sheet 2 of 2) . . . . . . . . . . . . . . . . . . . . . . 8-2
8-2 Exception Vector Assignments (Sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 8-3
8-3 Microsequencer STATUS
8-4 Tracing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8-5 Interrupt Levels and Mask Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
8-6 Exception Priority Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Codes and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-79
, BERR, and HALT Assertion Results . . . . . . . . . . . . . . . . . . . . . . 7-81
Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
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LIST OF TABLES (Continued)
Table
Title
Number
9-1 Size Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
9-2 Translation Tree Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
9-3 MMUSR Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-60
10-1 cpTRAPcc Opmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19
10-2 Coprocessor Format Word Encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10-3 Null Coprocessor Response Primitive Encodings . . . . . . . . . . . . . . . . . . . 10-39
10-4 Valid EffectiveAddress Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43
10-5 Main Processor Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51
10-6 Exceptions Related to Primitive Processing. . . . . . . . . . . . . . . . . . . . . . . . 10-66
12-1 Data Bus Activity for Byte, Word, and Long-Word Ports . . . . . . . . . . . . . . 12-11
12-2 Memory Access Time Equations at 20 MHz . . . . . . . . . . . . . . . . . . . . . . . 12-16
12-3 Calculated t
Less Than or Equal to the CPU Maximum Frequency Rating . . . . . . . . . 12-17
12-4 Microsequencer STATUS Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
12-5 List of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
12-6 AS
12-7 V
and ECSC Indicates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
and GND Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46
CC
Values for Operation at Frequencies
AVDV
Page
Number
xliv
MC68030 USER’S MANUAL
MOTOROLA
SECTION 1
INTRODUCTION
The MC68030 is a second-generation full 32-bit enhanced microprocessor from Motorola.
The MC68030 is a member of the M68000 Family of devices that combines a central
processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller,
and a memory management unit (MMU) in a single VLSI device. The processor is designed
to operate at clock speeds beyond 20 MHz. The MC68030 is implemented with 32-bit
registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing
modes.
The MC68030 is upward object code compatible with the earlier members of the M68000
Family and has the added features of an on-chip MMU, a data cache, and an improved bus
interface. It retains the flexible coprocessor interface pioneered in the MC68020 and
provides full IEEE floating-point support through this interface with the MC68881 or
MC68882 floating-point coprocessor. Also, the internal functional blocks of this
microprocessor are designed to operate in parallel, allowing instruction execution to be
overlapped. In addition to instruction execution, the internal caches, the on-chip MMU, and
the external bus controller all operate in parallel.
The MC68030 fully supports the nonmultiplexed bus structure of the MC68020, with 32 bits
of address and 32 bits of data. The MC68030 bus has an enhanced controller that supports
both asynchronous and synchronous bus cycles and burst data transfers. It also supports
the MC68020 dynamic bus sizing mechanism that automatically determines device port
sizes on a cycle-by-cycle basis as the processor transfers operands to or from external
devices.
A block diagram of the MC68030 is shown in Figure 1-1. The instructions and data required
by the processor are supplied from the internal caches whenever possible. The MMU
translates the logical address generated by the processor into a physical address utilizing
its address translation cache (ATC). The bus controller manages the transfer of data
between the CPU and memory or devices at the physical address.
MOTOROLA
MC68030 USER’S MANUAL
1-1
Introduction
BUS
DATA
DATA
PADS
INTERNAL
DATA
CACHE
HOLDING
REGISTER
B
STAGE
BUS
(CAHR)
CACHE
INSTRUCTION
SIZE
MULTIPLEXER
DATA
SECTION
DATA
MULTIPLEXER
MISALIGNMENT
CACHE
C
STAGE
INSTRUCTION PIPE
D
STAGE
STORE
CONTROL
CONTROL
MICROSEQUENCER AND
LOGIC
CONTROL
EXECUTION UNIT
BUS
ADDRESS
INSTRUCTION
SECTION
ADDRESS
SECTION
COUNTER
PROGRAM
ADDRESS
BUS
ADDRESS
UNIT
ACCESS
CONTROL
BUS
DATA
ADDRESS
BUFFER
PREFETCH PENDING
MICROBUS
BUS CONTROLLER
WRITE PENDING
CONTROLLER
BUFFER
SIGNALS
BUS CONTROL
1-2
PADS
ADDRESS
BUS
ADDRESS
Figure 1-1. Block Diagram
MC68030 USER’S MANUAL
MOTOROLA
1.1 FEATURES
The features of the MC68030 microprocessor are:
• Object Code Compatible with the MC68020 and Earlier M68000 Microprocessors
• Complete 32-Bit Nonmultiplexed Address and Data Buses
• 16 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Registers
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simultaneously
• Paged MMU that Translates Addresses in Parallel with Instruction Execution and Internal Cache Accesses
• Two Transparent Segments Allow Untranslated Access to Physical Memory To Be D
fined for Systems That Transfer Large Blocks of Data between Predefined Physical Addresses — e.g., Graphics Applications
• Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches
To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped
Introduction
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum),
Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock
minimum) all to the Physical Address Space
• Dynamic Bus Sizing Supports 8-, 16-, 32-Bit Memories and Peripherals
• Support for Coprocessors with the M68000 Coprocessor Interface — e.g., Full IEEE
Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coprocessors
• 4-Gbyte Logical and Physical Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (HighDensity NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum
Die Size
• Processor Speeds Beyond 20 MHz
Both improved performance and increased functionality result from the on-chip
implementation of the MMU and the data and instruction caches. The enhanced bus
controller and the internal parallelism also provide increased system performance. Finally,
the improved bus interface, the reduction in physical size, and the lower power consumption
combine to reduce system costs and satisfy cost/performance goals of the system designer.
MOTOROLA
MC68030 USER’S MANUAL
1-3
Introduction
1.2 MC68030 EXTENSIONS TO THE M68000 FAMILY
In addition to the on-chip instruction cache present in the MC68020, the MC68030 has an
internal data cache. Data that is accessed during read cycles may be stored in the on-chip
cache, where it is available for subsequent accesses. The data cache reduces the number
of external bus cycles when the data operand required by an instruction is already in the
data cache.
Performance is enhanced further because the on-chip caches can be internally accessed in
a single clock cycle. In addition, the bus controller provides a two-clock cycle synchronous
mode and burst mode accesses that can transfer data in as little as one clock per long word.
The MC68030 enhanced microprocessor contains an on-chip MMU that allows address
translation to operate in parallel with the CPU core, the internal caches, and the bus
controller.
Additional signals support emulation and system analysis. External debug equipment can
disable the on-chip caches and the MMU to freeze the MC68030 internal state during
breakpoint processing. In addition, the MC68030 indicates:
1. The start of a refill of the instruction pipe
2. Instruction boundaries
3. Pending trace or interrupt processing
4. Exception processing
5. Halt conditions
This status and control information allows external debugging equipment to trace the
MC68030 activity and interact nonintrusively with the MC68030 to effectively reduce system
debug effort.
1.3 PROGRAMMING MODEL
The programming model of the MC68030 consists of two groups of registers: the user model
and the supervisor model. This corresponds to the user and supervisor privilege levels. User
programs executing at the user privilege level use the registers of the user model. System
software executing at the supervisor level uses the control registers of the supervisor level
to perform supervisor functions.
1-4
MC68030 USER’S MANUAL
MOTOROLA
Introduction
Figure 1-2 shows the user programming model, consisting of 16 32-bit general-purpose registers and two control registers:
• General-Purpose 32-Bit Registers (D0–D7, A0–A7)
• 32-Bit Program Counter (PC)
• 8-Bit Condition Code Register (CCR)
The supervisor programming model consists of the registers available to the user plus 14
control registers:
• Two 32-Bit Supervisor Stack Pointers (ISP and MSP)
• 16-Bit Status Register (SR)
• 32-Bit Vector Base Register (VBR)
• 32-Bit Alternate Function Code Registers (SFC and DFC)
• 32-Bit Cache Control Register (CACR)
• 32-Bit Cache Address Register (CAAR)
• 64-Bit CPU Root Pointer (CRP)
• 64-Bit Supervisor Root Pointer (SRP)
• 32-Bit Translation Control Register (TC)
• 32-Bit Transparent Translation Registers (TT0 and TT1)
• 16-Bit MMU Status Register (MMUSR)
The user programming model remains unchanged from previous M68000 Family
microprocessors. The supervisor programming model supplements the user programming
model and is used exclusively by the MC68030 system programmers who utilize the
supervisor privilege level to implement sensitive operating system functions, I/O control, and
memory management subsystems. The supervisor programming model contains all the
controls to access and enable the special features of the MC68030. This segregation was
carefully planned so that all application software is written to run at the nonprivileged user
level and migrates to the MC68030 from any M68000 platform without modification. Since
system software is usually modified by system programmers when ported to a new design,
the control features are properly placed in the supervisor programming model. For example,
the transparent translation feature of the MC68030 is new to the family supervisor
programming model for the MC68030 and the two translation registers are new additions to
the family supervisor programming model for the MC68030. Only supervisor code uses this
feature, and user application programs remain unaffected.
MOTOROLA
MC68030 USER’S MANUAL
1-5
Introduction
Registers D0–D7 are used as data registers for bit and bit field (1 to 32 bits), byte (8 bit),
word (16 bit), long-word (32 bit), and quad-word (64 bit) operations. Registers A0–A6 and
the user, interrupt, and master stack pointers are address registers that may be used as
software stack pointers or base address registers. Register A7 (shown as A7' and A7'' in
Figure 1-3) is a register designation that applies to the user stack pointer in the user privilege
level and to either the interrupt or master stack pointer in the supervisor privilege level. In
the supervisor privilege level, the active stack pointer (interrupt or master) is called the
supervisor stack pointer (SSP). In addition, the address registers may be used for word and
long-word operations. All of the 16 general-purpose registers (D0–D7, A0–A7) may be used
as index registers.
31 16 15
31 16 15 0
31
31
16 15
15
87
7
0
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
0
A7 (USP)
0
PC
0
CCR
DATA
REGISTERS
ADDRESS
REGISTERS
USER STACK
POINTER
PROGRAM
COUNTER
CONDITION
CODE
REGISTER
1-6
Figure 1-2. User Programming Model
MC68030 USER’S MANUAL
MOTOROLA
Introduction
The program counter (PC) contains the address of the next instruction to be executed by the
MC68030. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate.
31
31
31
31
31
31
31
31
16 15
16 15
15
15
0
0
87 0
(CCR) SR
0
0
0
0
0
0
0
A7' (ISP)
A7" (MSP)
VBR
SFC
DFC
CACR
CAAR
AC0
AC1
ACUSR
INTERRUPT
STACK POINTER
MASTER STACK
POINTER
STATUS REGISTER
VECTOR BASE
REGISTER
ALTERNATE FUNCTION
CODE REGISTERS
CACHE CONTROL
REGISTER
CACHE ADDRESS
REGISTER
ACCESS
CONTROL
REGISTER 0
ACCESS
CONTROL
REGISTER 1
ACU STATUS
REGISTER
Figure 1-3. Supervisor Programming Model Supplement
The status register, SR, (see Figure 1-4) stores the processor status. It contains the
condition codes that reflect the results of a previous operation and can be used for
conditional instruction execution in a program. The condition codes are extend (X), negative
(N), zero (Z), overflow (V), and carry (C). The user byte containing the condition codes is the
only portion of the status register information available in the user privilege level, and it is
referenced as the CCR in user programs. In the supervisor privilege level, software can
access the full status register, including the interrupt priority mask (three bits) as well as
additional control bits. These bits indicate whether the processor is in:
1. One of two trace modes (T1, T0)
2. Supervisor or user privilege level (S)
3. Master or interrupt mode (M)
The vector base register (VBR) contains the base address of the exception vector table in
memory. The displacement of an exception vector is added to the value in this register to
access the vector table.
MOTOROLA
MC68030 USER’S MANUAL
1-7
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