MOTOROLA MC6800 Technical data

——

-——— -—

查询6800供应商

8-BIT MICROPROCESSING UNIT (MPU)

The MC6800 is a monolithic 8-bit microprocessor forming the central

control function for Motorola’s M68~ family. Compatible with TTL, the

MC6B~, as with all M6800 system parts, requires only one + 5.O-volt

power supply, and no external TTL devices for bus interface.

The MC6800 is capable of addressing 64K bytes of memory with its

16-bit address lines. The 8-bit data bus is bidirectional as well as three­state, making direct memory addressing and multiprocessing applica­tions realizable.

● 8-Bit Parallel Processing

● Bidirectional Data Bus

. 16-Bit Address Bus – WK Bytes of Addressing

● 72 Instructions – Variable Length

. Seven Addressing Modes – Direct, Relative, Immediate, Indexed,

Extended, Implied and Accumulator

● Variable Length Stack

. Vectored Restart
. Maskable Interrupt Vector
. Separate Non-Maskable Interrupt – Internal Registers Saved i#’’::$$

Stack

. Six Internal Registers – Two Accumulators, Index Regist~#?Y’:Y’

Program Counter, Stack Pointer and Condition Code Re~@te~

● Direct Memory Addressing (DMA) and Multiple P~@$esso’r

Capability

● Simplified Clocking Characteristics

. Clock Rates as High as 2.0 MHz

● Simple Bus Interface Without TTL ,$~~~~i$~’

● Halt and Single Instruction Executlo*k$~~$bility

~~$$~

....,

,.,.$,.>.‘i,\,.*>

& ‘~~$

..,.

,{,

,:&f*,>~<~’

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$$:$

~:

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~+~,

\*:,.:~’‘

,*.. .+

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.,\.J.*.+,t~

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INFORMATION

PackageType‘$:,~~equency (MHz)

ceramic+,,:,~f~ “

L s~~i~ ~ “

@y*+(k:::

Ti. .... ,

~rdio

.—

!–!–

s suffix

1.0

1.0

2.0

1.0 O“c to 70°c

1.0 –40°C to 85°C

*:;.>

,.*. .\

‘;:$*Y*:,F

.it~

Temperature Order Number

Ooc to 70°c

–40°C to 85°C MC~~CL

Ooc

to 70°c

.:;.!,.,, ...+

,1’.-‘ -->,,:+~..,

*V\>>>.,,**.

‘~:?iii*

...*”,+<

,,:+,..,

‘.~;:),t.{t,.

,~>

,“,.,

I

1.5 O“c to 70°c

1.5 –40°C to 85°C
O“c to 70°c

–40°C to 85°C

to 70°c MC68AOOP

to 85°C

to 70°c MC68BOOP

Plastic

P Suffix

2.0

1.0 O“c to 70°c

1.0

1.5 O“c

1.5 – 40°C

2.0 Ooc

*: ,.. ‘is

.,>s,-.

MC6800L

MC68BOOL
MC68WS

MC@WCS
Mc68Ams
Mc68Amcs
MC68BOOS

MC6800P

MC6800C P

MC68AOOCP

,,2:+.(~

‘~”‘%1*F.

, ~,,)i~. ,{).

.Y,:>,+,-,,,..,,,!,.

........

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,,*!.

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~..!’.

,>:

‘.*$

MCWOO

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PIN ASSIGNMENT

Vss[ 10

HALT[ 2

@l [ 3

4

KQ [

VMA [ 5

6

m[

BA [ 7

Vccc 8

AC[ 9 32 ]Dl
Al [ 10 31 ] D2
A2 [ 11
A3[ 12
A4[ 13 28 ] D5
A5 [ 14

A6 [ 15
A7 [ 16 25 ]A15
A8 [ 17
A9 [ 16

A1O c

19

Al 1q 20

CERAMIC PACKAGE

~

SUFFIX

CASE 715

JRESET

39

]TSC

38 ]N. C.

37 342

36 ]DBE

35 ]N, C.
34 ]Rl~
33 ] DO

30 ] D3
29 ] D4

27 ] D6

26 ] D7

24 ]A14

23 JA13
22 ]A12

21 Jvss

I

i

I

MOTOROLA INC., lW

DS9471-F

MAXIMUM RATINGS

MC6~C MC68A~C

I I -40to +85 I I

Storage Temperature Range

I Tsta l-55to +150 I “C I

THERMAL RESISTANCE

Rating

Symbol Value Unit

Plastic Package Im
Cerdip Package

eJ A

60

“Clw

Ceramic Packaqe m

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in ‘C can be obtained from:

TJ=TA+(PDo OJA)

Where:

TA = Ambient Temperature, ‘C

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electrical fields; however, it is ad­vised that normal precautions be taken to
avoid application of any voltage higher than
maximum-rated voltages to this high­impedance circuit. Reliability of operation is

(1)

OJA= Package Thermal Resistance, Junction-to-Ambient, “C/W ;F’s~;

,.,\\wy\~.::$,i~

PD=PINT+PpORT

.,$ ‘f:?ki,,, ,,$3

~..,..,..

::i~.’.~i.:.,.

PINT= ICC x Vcc, Watts – Chip Internal Power

.<,,..,,

1*+:

,..,

.,+*

PpORT = Port Power Dissipation, Watts – User Determin@:$,,,

. ,.,. .

..,.

For most applications PPORT< PINT and can be neglected. P$o~~ may become significant if the device is configured to

drive Darlington bases or sink LED loads.

%i*\:,+,:,,,**F

..,,,.,,\+,*

An approximate relationship between PD and TJ (if PpO~~$YWbglected) is:

,.>,,,.

PD= K- (TJ+2730C)

~,:*

(2)

.,J:>

Solving equations 1 and 2 for K gives:

,J,t::i,}

.,(*;{:\

K= PD. (TA+2730C)+0JA* PD2 .. ‘}~. $

(3)

,’,:::/:’\,.*:..*>.\\

Where K is a constant pertaining to the parti~$~$~~~it. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K the va~~~~:Qft,@Dand TJ can be obtained by solving equations(1) and (2) iteratively for any
value of TA,

\\*‘:*,.

.,,

,>f:?>,{,,,>i,,t

~“,’.,,\<..

.~\ ‘~$,\.,!.{w

‘-.<~:,.~~y>

V’i,

.\\

,::,2.CF i?~jt:,?..

.},.

DC ELECTRICAL CHARACTERl~%~C~(Vcc= 5,0 Vdc, +5%, Vss = O, TA= TL to TH unless otherwise noted)

,..:$:,?,$,,,..,,.,>

“ ~~@aracteriatic

\t$.<,%,\..&i,t.

Input High Voltage

“i’;,,L,,‘$,

Logic

“a?+$,}.,,’~

,;>?

~.,t...t,

41,42

Input Low Voltage ~w”$&~$,$#

Logic

.,. , ‘<$

.,~’tat;.{,,,\.:,,

~1 ,42

*,,.;’.

Input Leakag@:$~&f$n~

(Vin =Ot&@&~~, Vcc= Max)

Logic

(Vin

~&!0,~~@5 V, Vcc=o V to 5.25 V)

Hi-~@bkti@akage Current

@l, #2
D&D7

f~#’@&.4 to 2.4 V, Vcc = Max)

AO-A15, Rlw

~w~? High Voltage

‘$$lLoad= - 205tiA, Vcc= MinJ

DO-D7

“(lLoad= – 1454A, VCC= Min)

A&A15, R/~, VMA

(lLoad= – 100KA, VCC= Min)

BA

Output Low Voltage (lLoad = 1.6 mA, VCC = Min)

Internal Power Dissipation (Measured at TA = TL)

Capacitance

(Vin=O, TA=250C, f=l.O MHz)

~1
42

DGD7

Logic Inputs

AO-A15, Rl~, VMA

—

Svmkl

VOH

VOL

PINT

Cin

Cout

VSS–0,3 –

VSS+O.8 v

VSS–0,3 –

VSS+O.4

—

1,0

2.5

PA

,

[

1

I

VSS+2.4 – –
VSS+2.4 – –

v

VSS+2.41 – I – I

I

—

!

—

Ivss+o

w

,4 v

—

I 0.5 ]

1,0 w

I I I I

—

25 35

—

45

70 pF

—

10 12.5

—

6.5

10

— —

12 pF

(M)

MOTOROLA Semjconducfor Products Inc.

.-

2

CLOCK TIMING (Vcc= 5,0 V, *5%, VSS=O, TA=TL to TH unless otherwise noted)

Characteristic

Frequency of Operation

Cycle Time (Figure 1)

Clock Pulse Width @l, @2– MCmN

(Measured at VCC– 0.6 V)

Total 01 and 42 Up Time

Rise and Fall Time (Measured between VSS +0.4 and VCC– O.6)
Delay Time or Clock Separation (Figure 1)

(Measured at VOV=VSS+O.6 V@tr=tf=l~ ns)
(Measured at VOV= VSS + 1.0 V@tr=tf S35 ns}

@l, @2– MC6BAO0 pW~H
@l, @2 – MC68BO0

MC~
MC68AO0 f
MCWBW

MCm 1.000 –
MC@AW
MC~BW

MCH
MC~A~

MC6BBW

Symbol Min Typ

0.1 –

0.1 –

0.1 –

tcyc

t“t

tr, tf

td

O.m

O.m – 10

w – 9m
Za –

180 –

90 –
600 –
w –

~

— —

o
o

—

–$; y< “$,~
—.$:~,

?\:i..

Max Unit

9m
9W

,,fj:$’,i~ ,’;?,..~’

%$*t&

,>+1,:

,,

$\*.’,

1.0

1.5 MHz

2.0

10
10 ps

ns

—

–
– ‘$$:fi+s:~

1

, ,,,,

.!>.,:..,.,.:~:~,

Y “~:..

d*“:*’:*L

ns

,*!.

‘*{,1,

td+ +

vl~c*

,, ...>.,,,.

.~t~

4:.

*T, ,+1

,

,~.;.,+-.~’--:$,

..,,.

~,t~,,,:y

- .$~~+’<.~a..~+,k~

~\+,\ -i

*,. :

‘:.$.....

,,,,

tDBEr, tDBEf

Character@i&$iF, ~~’

Address DelaV

C=90pF
C=30 pF

Peripheral Read Access ~fi&~f:

tacc = tut – (tAD +~~~$~.

Data Setup Tim$,:( ~~~?:
Input Data H@me ‘
Output D~@ ‘~l,#Time
Addressf&,&,Jime (Address, R/~, VMA)
Ena~~i~@Time for DBE Input
Data ~lav Time (Write)
Processor Controls

Processor Control Setup Time

Processor Control Rise and Fall Time

8US Available DelaV tBA
Hi-Z Enable
Hi-Z DelaV
Data Bus Enable Down Time During @l Up Time
Data Bus Enable Rise and Fall Times

**3::,:>

,,..,.. >

‘d+ b,’’”

..,,

,.

,, <

Symbol

tA D –

tacc

tDSR

tH 10
tH 10

tA H 30

tEH 450

tDDW

tpcs

tpcr, tpcf

tTSE o – 40 0

tTSD

tDBE

MC~

Min

Typ Max Min

270 –

–

— —

605
lm

– – 225 –

2m

– – Im –
– – 29 –

– –

Iw

– – 25

2W –

– — m
– – 60

– – 10

25 – 10

50 – 30

– –

– – 140

270 –

– –

MC8BAO0

Typ Max Min

–
–

– — 2W
– – 40

– – 10

25 – 10

a – m

280

– –
– 2W –

– –
– 100 –
–

– 40 0

–

120

– –

–

– 25

1BO –
165 –

165 –

270 –

MC6BBO0

220

110

75

–

Typ Max

– 150 ns

135

–

– — ns
– – ns

– – ns
25 – ns

50 – ns

– – ns
– 160

–

–

– 100

135

–

– m

220

–

– –

–

25

Unit

ns

ns

—

m

M070ROLA Semiconductor Products Inc.

3

1

FIGURE 2 – READ DATA FROM MEMORY OR PERIPHERALS

/

Start of Cycle

+

@l

‘VIHC

~

0.4 v

7

0.4 v

Data Not Valid

~ Start of Cvcle

‘):.,

[

Data

2.4 V

From MPU

0.4 v

I

k\\\\\\Y

Data Not Valid

ktDDw+

NOTES:

1. Voltage levels shown are VLSO.4, VH> 2.4 V, unless otherwise specified

2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted

@

MOTOROLA Semiconductor Produck Inc.

4

—

FIGURE 4 – TYPICAL DATA BUS OUTPUT DELAY

versus CAPACITIVE LOADING (TDDw)

600

I OH =-205A max @ 2.4 V

‘lo L=l.6mAmax@0.4V

500 -

Vcc = 5.0v
1A= 25°C

~ 400
=

u
z
F 300
>

/

~

/ ~

: 200

/ ‘

- ~

/

100

/

CL

includes stray capacitance

0’

0 100 200

300

400 500 600

CL,

LOAO CAPACITANCE (pF)

FIGURE 5 – TYPICAL READ/WRITE, VMA, AND ADDRESS

OUTPUT DELAY

versus CAPACITIVE LOADING (TAD)

600

lo H=-145*max@2.4V

‘lo L=l.6mAmax@0.4v

500

-VCC=5.OV

TA = 25°C

-$,:,

z 400
u

z
~ 300

~
u

0 200

100

CL

includes stray capacitance

o

0 100

2og~+~~ ,i$oo

400

500

600

@

MOTOROLA Semiconductor Products Inc.

5

I

FIGURE 7 – =PANDED BLOCK DIAGRAM

A15 A14 A13 A12 All A1O A9 A8

A7 A6 A5

A4 A3 A2 Al AO

Clock, @l
Clock, @2

RESET

Non-Maskable Interrupt

HALT

Interrupt Request

Three-State Control

Data Bus Enable

Bus Available

Valid Memory Address

Read/Wtite, Rl~

37

40

6

a

2

3

Instruction

4

Decode

and

39

Control

36+

34+

1

Instruction

Register

‘*” !*

..l.t\,,

@

MOTOROLA Semiconductor Products Inc.

6

.—

.—

.—

MPU SIGNAL DESCRIPTION

Proper operation of the MPU requires that certain control

and timing signals be provided to accomplish specific func­tions and that other signal lines be monitored to determine
the state of the processor.

Clocks Phase One and Phase Two (o1, 42) – Two pins

are used for a two-phase non-overlapping clock that runs at
the VCC voltage level.

Figure 1 shows the microprocessor clocks. The high level

is specified at VIHC and the low level is specified at VILC.
The allowable clock frequency is specified by f (frequency).
The minimum @l and @2 high level pulse widths are specified

by PW~H (pulse width high time). To guarantee the required
access time for the peripherals, the clock up time, tut, is
specified. Clock separation, td, is measured at a maximum
voltage of VOV (overlap voltage), This allows for a multitude
of clock variations at the system frequency rate.

Address Bus (AOA15) – Sixteen pins are used for the ad­dress bus. The outputs are three-state bus drivers capable of
driving one standard TTL load and 90 pF. When the output is
turned off, it is essentially an open circuit. This permits the

MPU to be used in DMA applications. Putting TSC in its high

state forces the Address bus to go into the three-state mode.

Data Bus (DO-D7) – Eight pins are used for the data bus.

It is bidirectional, transferring data to and from the memory
and peripheral devices. It also has three-state output buffer$
capable of driving one standard TTL load and 130 pF. D,a~$,

Bus is placed in the three-state mode when DBE is Io#t\,t w~$.

,{’.y...:>.:>,,:!:.?..

.+,.‘+:+”‘ ‘$,.?

Data Bus Enable (DBE) – This level sensitive i~[~t~$sthe
three-state control signal for the M PU data ~$~l:~yd will
enable the bus drivers when in the high st~:&$$@j9 Input is
TTL compatible; however in normal op~,atib~~$twould be
driven by the phase two clock. Durin&@n~~,K~ read cycle,
the data bus drivers will be disabled,’~~t~nal ly. When it is
desired that another device contr$PtR~&ata bus, such as in
Direct Memory Access (DMA)j+~k~@~ions, DBE should be
held low.

~t~

.>.:,:,.,,, ,x.

If additional data setup+p[+ho~d~?me is required on an MPU

write, the DB E

down ,~,~~ @n be decreased, as shown in

Figure 3 (DBE#@2\R:~~e~inimum down time for DBE is

tDB E as shown, ~~~.s}~ting D B E with respect to E, data
setup or hold t~,$@# be increased.

\\\$.

;>L:.,.?J~,

Bus Ay~i$~l~.(bA) – The Bus Available signal will nor-

mally ~%~ ~}$’low state; when activated, it will go to the

..,*.’:* Y

high.?ata~:+indicating that the microprocessor has stopped

* “’“’*’l+

and @,@tfhe address bus is available. This will occur if the
HALT~ne is in the low state or the processor is in the WAIT
state as a result of the execution of a WAIT instruction. At
such time, all three-state output drivers will go to their off
state and other outputs to their normally inactive level. The
processor is removed from the WAIT state by the occurrence
of a maskable (mask bit I= O) or nonmaskable interrupt, This
output is capable of driving one standard TTL load and
30 pF. If TSC is in the high state, Bus Available will be low,

Read/Write (R/~) – This TTL compatible output signals

the peripherals and memory devices wether the MPU is in a

@

MOTOROLA

Read (high) or Wrile (low) state, The normal standby state of
this signal is Read (high). Three-State Control going high will
turn Read/Write to the off (high impedance) state. Also,
when the processor is halted, it will be in the off state. This
output is capable of drivina one standard TTL Ioa&?iqnd
90 pF.

~+,r+i~ .:}

RESET – The RESET input is used to rese~&}N~&~rt the
M PU from a power down condition resulti~~,jf~% a power
failure or initial start-up of the processor,+:~@l%~i&el sensitive
input can also be used to reinitialize t,$~~~~~ne

at any time

after start-up.

.)’ k%}?*

:t:;l,\ \

If a high level is detected in th~ Inpw; this will signal the

MPU to begin the reset seqe~$~. During the reset se­quence, the contents of th,~?%f$wb locations (FFFE, FFFF)
in memory will be loade@{~~&,Jtie Program Counter to point
to the beginning of..,$~b.:wet routine. During the reset

~.\J~t.~,,~y..

routine, the interrupt ~s~ bit is set and must be cleared
under program c~~ol, before the M PU can be interrupted by
IRQ. While ‘K%Jk’’low

(assuminga minimum of8 clock

cycles have ~Jcc~$r8d) the MPU output signals will be in the
followinqj$&MVMA= low, BA= low, Data Bus= high im­peda~~e,>~~~= high (read state), and the Address Bus will
con$&8 the ‘reset address FFFE. Figure 8 illustrates a power

?}4

&“~q@~nce using the RESET control line. After the power

~i.

~,P@ reaches 4.75 V, a minimum of eight clock cycles are

?$:jlj$~qtiired for the processor to stabilize in preparation for

‘~trestarting. During these eight cycles, VMA will be in an in-

.lp~

determinate state so any devices that are enabled by VMA
which could accept a false write during this time (such as
battery-backed RAM) must be disabled until VMA is forced
low after eight cycles. RESET can go high asynchronously
with the system clock any time after the eighth cycle.

RESET timing is shown in Figure 8. The maximum rise and
fall transition times are specified by tpcr and tpcf. If RESET
is high at tpcs (processor control setup time), as shown in
Figure 8, in any given cycle then the restart sequence will
begin on the next cycle as shown. The RESET control line
may also be used to reinitialize the MPU system at any time
during its operation. This is accomplished by pulsing RESET
low for the duration of a minimum of three complete 42
cycles. The RESET pulse can be completely asynchronous

with the MPU system clock and will be recognized during 42

if setup time tpcs is met.

Interrupt Request (~Q) – This level sensitive input re-
quests that an interrupt sequence be generated within the
machine. The processor will wait until it completes the cur­rent instruction that is being executed before it recognizes
the request. At that time, if the interrupt mask bit in the Con­dition Code Register is not set, the machine will begin an in­terrupt sequence. The Index Register, Program Counter, Ac­cumulators, and Condition Code Register are stored away on
the stack. Next, the MPU will respond to the interrupt re­quest by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit ad­dress will be loaded that points to a vectoring address which
is located in memory locations FFF8 and FFF9. An address
loaded at these locations causes the MPU to branch to an in-

terrupt routine in memory. Interrupt timing is shown in

Figure 9.

Semiconductor Products Inc.

7

The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while HALT
is low.

The ~ has a high-impedance puilup device internal to

the chip; however, a 3 kQ external resistor to VCC should be
used for wire-OR and optimum control of interrupts.

Non-Maskable Interrupt (NMI) and Wait for Interrupt

(WAI) – The MCWCO is capable of handling two types of in­terrupts: maskable (~) as described earlier, and non­maskable (~) which is an edge sensitive input. IRQ is
maskable by the interrupt mask in the condition code register
while ~ is not maskable. The handling of these interrupts
by the M PU is the same except that each has its own vector
address. The behavior of the MPU when interrupted is
shown in Figure 9 which details the MPU response to an in­terruDt while the MPU is executina the control ~roaram. The
interrupt shown could be either ~Q or ~ and ca~ be asyn­chronous with respect to +2. The interrupt is shown going
low at time tpcs in cycle #1 which precedes the first cycle of
an instruction (OP code fetch). This instruction is not ex­ecuted but instead the Program Counter (PC), Index

Register (IX), Accumulators (ACCX), and the Condition

Code Register (CCR) are pushed onto the stack,

The Interrupt Mask bit is set to prevent further interrupts.

The address of the interrupt service routine is then fetched
fram FFFC. FFFD for an NMI interruDt and from FFF8, FFF9
for an ~’interrupt. Upon complet~on of the interrupt ser­vice routine, the execution of RTI will pull the PC, IX, ACCX,
and CCR off the stack; the Interrupt Mask bit is restored to
its condition prior to Interrupts (see Figure 10).

Figure 11 is a similar interrupt sequence, except in this
case, a WAIT instruction has been executed in prepara$$~
for the interrupt. This technique speeds up the M&U’”~
response to the interrupt because the stacking of

tbe~~~$.W,

ACCX, and the CCR is already done. While t~~$fM@ iS

waiting for the interrupt, Bus Available wilP&@+{Q?~hin­dicating the following states of the control lj~~Y~MA is

low,

and the Address Bus, R/~and Data B~~ ~~, ~{ in the high
impedance state. After the interrupt w-$* ISserviced as
previously described.

,.\,

.<

},it?~,,,::

A 3-10 kQ external resistor to V&*’&~&tild be used for wire-

OR and optimum control of igi~r~w~t~.

,*+$

..,,.

“$,’

..

MEMORY MAP.@R IMRRUPT VECTORS

~:.$

‘*, ,,$’

Vetior ,.., ;.

‘~’

MS

,,f*y

Description

FFFE

:,* E=3

Reset

FFFQ”J”

%FFD Non-Maskable Interrupt

E&.~\x}i,,$ FFFB

Software Interrupt

‘$,~aip”

~

—

Interrupt Request

Three-State Control (TSC) – When the level sensitive

Three-State Control (TSC) line is a logic “l”, the Address

Bus and the Rim line are placed in a high-impedance state.
VMA and BA are forced low when TSC= “1” to prevent
false reads or writes on any device enabled by VMA. It is
necessary to delay program execution while TSC is held
high. This is done by insuring that no transitions of 41 (or 42)
occur during this period. (Logic levels of the clacks are irrele­vant so long as they do not change). Since the MPU is a
dynamic device, the 01 clock can be stopped for a maximum

@

MOTOROLA

time PW@H without destroying data within the M PU. TSC
then can be used in a short Direct Memory Access (DMA)
application.

Figure 12 shows the effect of TSC on the MPU. TSC must

have its transitions at tTSE (three-state enable) while holding

+1 high and +2 low as shown, The Address Bus and Rl~

line will reach the high-impedance state at tTSD (three-state
delay), with VMA being forced low. In this exampl$~%the
Data Bus is also in the high-impedance state while,,~;~@&­ing held low since DBE= 42. At this point in ti@e~,$,’)~MA

transfer could occur on cycles #3 and #4. -+$~SC is

returned low, the MPU Address and R/~lfl&/&Mrn to the
bus. Because it is too late in cycle #5 to,,~cp~,~emory, this
cycle is dead and used for synchroni$~~w.i$~rogram execu-

tion resumes in cycle #6.

..>;.

.*’

.!~:l

.’~\k:\,

.:~:.3,~.:~’

‘1~$~

Valid Memory Address (VM&,~~$ This output indicates to
peripheral devices that the~@&.@~a~?daddress on the address
bus. In normal operation~<gti~, signal should be utilized for

enabling peripheral i~tf~f~w’ such as the PIA and ACiA.

.y;.%,,a:.~+~b~

This signal is not thr@T~te. One standard TTL load and
90 pF may be d~&ly dfiven by this active high signal.

~,.,,+$s:.:>

..?XL?*>’.~~’.

HALT - ~h”~$’~%is level sensitive input is in the low state,

all activik~~o?~~e machine will be halted. This input is level

-.:<.~.~~

sensitj,ve. +i.,,

l.ti~~ line provides an input

to the MPU to allow con-

{W,gf”Program execution by

an outside source. If HALT is

+..~.g@ the MPU will execute the instructions; if it is low, the

“*~PU will go to a halted or idle mode. A response signal, Bus

‘~+,’tv:a,::

“’t~, Available (BA) provides an indication of the current MPU

$’+

status. When BA is low, the MPU is in the process of ex­ecuting the control program; if BA is high, the MPU has

halted and all internal activity has stopped,

When BA is high, the Address Bus, Data Bus, and Rl~

line will be in a high-impedance state, effectively removing
the MPU from the system bus. VMA is forced low so that the
floating system bus will not activate any device on the bus
that is enabled by VMA.

While the MPU is halted, all program activity is stopped,

and if either an ~ or IRQ interrupt occurs, it will be latched
into the MPU and acted on as soon as the MPU is taken out
of the halted mode. If a RESET command occurs while the

MPU is halted, the following states occur: VMA= low,
BA= low, Data Bus= high impedance, Rl~= high (read

state), and the Address Bus will contain address FFFE as
long as RESET is low, As soon as the RESET line goes high,
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.

Figure 13 shows the timing relationships involved when
halting the MPU. The instruction illustrated is a one byte, 2
cycle instruction such as CLRA. When HALT goes low, the

MPU will halt after completing execution of the current in­struction. The transition of HALT must occur tpcs before
the trailing edge of @l of the last cycle of an instruction
(point A of Figure 13). HALT must not go low any time later
than the minmum tpcs specified.

The fetch of the OP code by the MPU is the first cycle of
the instruction. If HALT had not been low at Point A but
went low during 42 of that cycle, the MPU would have

halted after completion of the following instruction. BA will
go high by time tBA (bus available delay time) after the last
instruction cycle.

At this point in time, VMA is low and R/~,

Address Bus, and the Data Bus are in the high-impedance
state.

Semiconductor Products Inc.

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To debug programs it is advantageous to step through

Iinesare back on the bus. Asingle byte, 2 cycle instruction

programs instruction byinstruction .To do this, HALT must

such as LSRisused forth isexample also. During the first cy-

be brought high for one MPU cycle and then returned low as

cle, the instruction Y is fetched from address M+l. BA

shown at point B of Figure 13. Again, the transitions of

returns high at tBA on the last cycle of the instruction in-

HALT must occur tpcs before the trailing edge of $1. BA

dicating the MPU is off the bus. If instruction Y had been

will go low at tBA after the leading edge of the next @l, in-

three cycles, the width of the BA low time would have been

dicating that the Address Bus, Data Bus, VMA and Rl~

increased by one cycle.

FIGURE 10 – MPU FLOWCHART

f

Y

1 +BA

3

Y

●

I 1

1.

2

3

0

A

Reset is recognized at any position in the flowchart.
Instructions which affect the l-Bit act upon a on~bh buffer register,
“lTMP.” This has the effect of delaying any CLEARING of the l-Bit one
clock time. Setting the l-Bit, however, is not delayed.

See Tables 6-11 for details of Instruction Execution.

m

MOTOROLA Semiconductor Products Inc.

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