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MC54HC595AJ
Datasheet
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Motorola MC54HC595AJ, MC74HC595AN Datasheet


SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
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High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays — 50% Lower Quiescent Power — Improved Input Noise and Latchup Immunity
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12 13
SHIFT
CLOCK RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1 2 3
4 5 6 7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
VCC = PIN 16 GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT

PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT
Ceramic Plastic SOIC TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
MC54/74HC595A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750 500 450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260 300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0 0 0
1000
500 400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum High–Level Output Voltage, QA – Q
H
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low–Level Output Voltage, QA – Q
H
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
MC54/74HC595A
High–Speed CMOS Logic Data DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Continued)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
OH
Minimum High–Level Output Voltage, SQ
H
Vin = VIH or V
IL
II
out
I v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VILII
outI v
4.0 mA
II
out
Iv 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum Low–Level Output Voltage, SQ
H
Vin = VIH or V
IL
II
out
I v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VILII
outI v
4.0 mA
II
out
Iv 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
OZ
Maximum Three–State Leakage Current, QA – Q
H
Output in High–Impedance State Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND l
out
= 0 µA
6.0
4.0
40
160
µA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
4.5
6.0
6.0 30 35
4.8 24 28
4.0 20 24
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1 and 7)
2.0
4.5
6.0
140
28 24
175
35 30
210
42 36
ns
t
PHL
Maximum Propagation Delay, Reset to SQ
H
(Figures 2 and 7)
2.0
4.5
6.0
145
29 25
180
36 31
220
44 38
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Clock to QA – Q
H
(Figures 3 and 7)
2.0
4.5
6.0
140
28 24
175
35 30
210
42 36
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to QA – Q
H
(Figures 4 and 8)
2.0
4.5
6.0
150
30 26
190
38 33
225
45 38
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to QA – Q
H
(Figures 4 and 8)
2.0
4.5
6.0
135
27 23
170
34 29
205
41 35
ns
t
TLH
,
t
THL
Maximum Output Transition Time, QA – Q
H
(Figures 3 and 7)
2.0
4.5
6.0
60 12 10
75 15 13
90 18 15
ns
t
TLH
,
t
THL
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
2.0
4.5
6.0
75 15 13
95 19 16
110
22 19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
C
out
Maximum Three–State Output Capacitance (Output in High–Impedance State), QA – Q
H
—
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
300
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
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