MOTOROLA MC54HC573A, MC74HC573A Technical data

MC54/74HC573A

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal 3-State Noninverting

Transparent Latch

High±Performance Silicon±Gate CMOS

The MC54/74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HCT373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HC573A is the noninverting version of the HC563A.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 μA

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 218 FETs or 54.5 Equivalent Gates

LOGIC DIAGRAM

D0

2

19

Q0

3

18

D1

Q1

4

17

D2

Q2

DATA

5

16

NONINVERTING

D3

Q3

6

15

INPUTS

D4

Q4

OUTPUTS

7

14

D5

Q5

8

13

D6

Q6

9

12

D7

Q7

11

LATCH ENABLE

1

PIN 20 = VCC

OUTPUT ENABLE

PIN 10 = GND

Design Criteria

Value

Units

Internal Gate Count*

54.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

μW

Speed Power Product

0.0075

pJ

* Equivalent to a two±input NAND gate.

MC54/74HC573A

		J SUFFIX
	20	CERAMIC PACKAGE
		CASE 732±03
		1

		N SUFFIX
	20	PLASTIC PACKAGE
		CASE 738±03
		1

		DW SUFFIX
20	1	SOIC PACKAGE
		CASE 751D±04

	20		DT SUFFIX
		TSSOP PACKAGE
		1	CASE 948E±02
		ORDERING INFORMATION
		MC54HCXXXAJ	Ceramic
		MC74HCXXXAN	Plastic
		MC74HCXXXADW	SOIC
		MC74HCXXXADT	TSSOP

PIN ASSIGNMENT

OUTPUT		1	20	VCC
ENABLE
D0		2	19	Q0
D1		3	18	Q1
D2		4	17	Q2
D3		5	16	Q3
D4		6	15	Q4
D5		7	14	Q5
D6		8	13	Q6
D7		9	12	Q7
GND		10	11	LATCH
				ENABLE

FUNCTION TABLE

	Inputs		Output
Output	Latch
Enable	Enable	D	Q
L	H	H	H
L	H	L	L
L	L	X	No Change
H	X	X	Z

X = Don't Care

Z = High Impedance

10/96

Motorola, Inc. 1996

1

REV 7

MC54/74HC573A

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Current, per Pin	± 35	mA
ICC	DC Supply Current, VCC and GND Pins	± 75	mA
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
	SOIC Package²	500
	TSSOP Package²	450
Tstg	Storage Temperature	± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C
	(Plastic DIP, TSSOP or SOIC Package)	260
	(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC).

Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C

Ceramic DIP: ± 10 mW/_C from 100_ to 125_C

SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ±6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to	v _	v		_
Symbol	Parameter	Test Conditions	V	_			125		C	Unit
				25 C	85 C
VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5		1.5			V
	Voltage	|Iout| v 20 μA	3.0	2.1	2.1		2.1
			4.5	3.15	3.15		3.15
			6.0	4.2	4.2		4.2
VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5		0.5			V
	Voltage	|Iout| v 20 μA	3.0	0.9	0.9		0.9
			4.5	1.35	1.35		1.35
			6.0	1.8	1 8		1.8
VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9		1.9			V
	Voltage	|Iout| v 20 μA	4.5	4.4	4.4		4.4
			6.0	5.9	5.9		5.9
		Vin = VIH or VIL |Iout| ≤ 2.4mA	3.0	2.48	2.34		2.2
		|Iout| v 6.0 mA	4.5	3.98	3.84		3.7
		|Iout| v 7.8 mA	6.0	5.48	5.34		5.2

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA	2	High±Speed CMOS Logic Data
		DL129 Ð Rev 6

MC54/74HC573A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit
VOL	Maximum Low±Level Output	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.1	0.1	0.1	V
	Voltage	|Iout| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1
		Vin = VIH or VIL |Iout| ≤ 2.4mA	3.0	0.26	0.33	0.4
		|Iout| v 6.0 mA	4.5	0.26	0.33	0.4
		|Iout| v 7.8 mA	6.0	0.26	0.33	0.4
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
IOZ	Maximum Three±State Leakage	Output in High±Impedance State	6.0	± 0.5	± 5.0	± 10	μA
	Current	Vin = VIL or VIH
		Vout = VCC or GND
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4.0	40	160	μA
	Current (per Package)	IIoutI = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

			Guaranteed Limit
		VCC
			± 55 to	v _		v		_
Symbol	Parameter	V	_		C		125		C	Unit
			25 C	85
tPLH,	Maximum Propagation Delay, Input D to Q	2.0	150	190			225			ns
tPHL	(Figures 1 and 5)	3.0	100	140			180
		4.5	30	38			45
		6.0	26	33			38
tPLH,	Maximum Propagation Delay, Latch Enable to Q	2.0	160	200			240			ns
tPHL	(Figures 2 and 5)	3.0	105	145			190
		4.5	32	40			48
		6.0	27	34			41
tPLZ,	Maximum Propagation Delay, Output Enable to Q	2.0	150	190			225			ns
tPHZ	(Figures 3 and 6)	3.0	100	125			150
		4.5	30	38			45
		6.0	26	33			38
tPZL,	Maximum Propagation Delay, Output Enable to Q	2.0	150	190			225			ns
tPZH	(Figures 3 and 6)	3.0	100	125			150
		4.5	30	38			45
		6.0	26	33			38
tTLH,	Maximum Output Transition Time, Any Output	2.0	60	75			90			ns
tTHL	(Figures 1 and 5)	3.0	27	32			36
		4.5	12	15			18
		6.0	10	13			15
Cin	Maximum Input Capacitance		10	10			10			pF
Cout	Maximum Three±State Output Capacitance (Output in High±Impedance State)		15	15			15			pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

		Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Enabled Output)*	23	pF

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High±Speed CMOS Data Book (DL129/D).

High±Speed CMOS Logic Data

3

MOTOROLA

DL129 Ð Rev 6