Motorola MC54HC4353J, MC54HC4351J, MC74HC4353N, MC74HC4353DW, MC74HC4351DW Datasheet
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SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"
" !
High–Performance Silicon–Gate CMOS
The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS
technology to achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers control
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The Channel–Select inputs determine which one of the Analog Inputs/
Outputs is to be connected, by means of an analog switch, to the Common
Output/Input. The d ata at the Channel–Select inputs may be l atched by
using the active–low Latch Enable pin. When Latch Enable is high, the latch
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is
inactive, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with L STTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
For multiplexers/demultiplexers without latches, see the HC4051,
HC4052, and HC4053.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance than Metal–Gate Types
• Low Noise
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates
HC4353 — 186 FETs or 46.5 Equivalent Gates
PIN ASSIGNMENT
MC54/74HC4351
X5
X
NC
X6
X4
GND
V
EE
ENABLE 2
ENABLE 1
X7 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
X3
X0
X1
X2
V
CC
LATCH
ENABLE
C
B
NC
A
NC = NO CONNECTION
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
LOGIC DIAGRAM
MC54/74HC4351
Single–Pole, 8–Position Plus Common Off and Address Latch
FUNCTION TABLE
MC54/74HC4351
Control Inputs
Enable Select
ON
Channel
1 2 C B A
Channel
(LE = H)*
L
H
L
L
L
X0
LLHHLLLLLHX0
X1
LLHHLLLHHLX1X2LLHHLLHHLHX2
X3
LLHHLHHLHLX3
X4
LLHHHHLLLHX4
X5
LLHHHHLHHLX5
X6
LLHHHHHHLHX6
X7
LHHXHXHXHXX7
None
HXXLXXXXXXNone
None
X = don’t care
*When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
BLOCK DIAGRAM
MC54/74HC4353
Triple Single–Pole, Double–Position Plus Common Off and Address Latch
FUNCTION TABLE
Control Inputs
Enable Select
On
Channel
1 2 C B A
Channel
(LE = H)*
L
H
L
L
L
Z0
Y0
X0
LLHHLLLLLHZ0Z0Y0Y0X0
X1
LLHHLLLHHLZ0Z0Y0Y1X1X0LLHHLLHHLHZ0Z0Y1Y1X0
X1
LLHHLHHLHLZ0Z1Y1Y0X1
X0
LLHHHHLLLHZ1Z1Y0Y0X0
X1
LLHHHHLHHLZ1Z1Y0Y1X1
X0
LLHHHHHHLHZ1Z1Y1Y1X0
X1
LHHXHXHXH
X
None
X L X X X
None
X = Don’t Care
*When Latch Enable is low, the Channel Selection
is latched and the Channel Address Latch does not
change states.
MULTIPLEXER/
DEMULTIPLEXER
17
X0
18
X1
19
X2
16
X3
1
X4
6
X5
2
X6
5
X7
ANALOG
INPUTS/OUTPUTS
4
X
COMMON
OUTPUT/INPUT
CHANNEL
ADDRESS
LATCH
13
B
15
A
12
C
11
LATCH ENABLE
7
ENABLE 1
8
ENABLE 2
SWITCH
ENABLES
PIN 20 = V
CC
PIN 9 = V
EE
PIN 10 = GND
PINS 3, 14 = NC
CHANNEL–SELECT
INPUTS
Z0
Z1
NC
Y0
Y1
GND
V
EE
ENABLE 2
ENABLE 1
Z
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
X0
X1
X
Y
V
CC
LATCH
ENABLE
C
B
NC
A
PIN ASSIGNMENT
NC = NO CONNECTION
16
X0
18
X
CHANNEL
ADDRESS
LATCH
13
B
15
A
12
C
11
LATCH ENABLE
7
ENABLE 1
8
ENABLE 2
SWITCH
ENABLES
PIN 20 = V
CC
PIN 9 = V
EE
PIN 10 = GND
PINS 3, 14 = NC
CHANNEL–SELECT
INPUTS
17
X1
2
Y0
1
Y1
6
Z0
4
Z1
X SWITCH
Y SWITCH
Z SWITCH
19
Y
5
Z
COMMON
OUTPUT/INPUT
NOTE:
This device allows independent control of each switch. Channel–Select
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
(Ref. to VEE)
– 0.5 to + 7.0
– 0.5 to 14.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 7.0 to + 0.5
V
V
IS
Analog Input Voltage
VEE – 0.5
to VCC + 0.5
V
V
in
DC Input Voltage (Ref. to GND)
– 1.5 to VCC + 1.5
V
I
DC Current Into or Out of Any Pin
± 25
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for
10 Seconds (Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
(Ref. to VEE)
2.0
2.0
6.0
12.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 6.0
GND
V
V
IS
Analog Input Voltage
V
EEVCC
V
V
in
Digital Input Voltage (Ref. to GND)
GND
V
CC
V
VIO*
Static or Dynamic Voltage Across Switch
—
1.2
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time, VCC = 2.0 V
Channel Select or Enable VCC = 4.5 V
Inputs (Figure 9a) VCC = 6.0 V
0
0
0
1000
500
400
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V
EE
= GND, Except Where Noted
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
I
in
Maximum Input Leakage
Current, Channel–Select or
Enable Inputs
Vin = VCC or GND,
VEE = – 6.0 V
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Channel Select = VCC or GND
Enables = VCC or GND
VIS = VCC or GND VEE = GND
VIO = 0 V VEE = – 6.0
6.0
6.0
2
8
20
80
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
ranges indicated in the Recommended Operating Conditions.
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused Analog I/O pins may be left
open or terminated. See Applications Information.
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
– 55 to
25_C
v
85_Cv 125_C
Unit
R
on
Maximum “ON” Resistance
Vin = VIL or V
IH
VIS = VCC to V
EE
IS v 2.0 mA (Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
Ω
Vin = VIL or V
IH
VIS = VCC or VEE (Endpoints)
IS v 2.0 mA (Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or V
IH
VIS = 1/2 (VCC – VEE)
IS v 2.0 mA
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
I
off
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = VIL or V
IH
VIO = VCC – V
EE
Switch Off (Figure 3)
6.0
– 6.0
0.1
0.5
1.0
µA
Maximum Off–Channel Leakage
Current, Common Channel
HC4351
Vin = VIL or V
IH
VIO = VCC – V
EE
Switch Off (Figure 4)
6.0
– 6.0
0.2
2.0
4.0
HC4353
6.0
– 6.0
0.1
1.0
2.0
I
on
Maximum On–Channel Leakage
Current, Channel to Channel
HC4351
Vin = VIL or V
IH
Switch to Switch = VCC – V
EE
(Figure 5)
6.0
– 6.0
0.2
2.0
4.0
µA
HC4353
6.0
– 6.0
0.1
1.0
2.0
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Enable to Analog Output
(Figure 12)
2.0
4.5
6.0
325
65
55
410
82
70
485
97
82
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
C
l/O
Maximum Capacitance Analog I/O
ОООООООО
ОООООООО
ОООООООО
Enable 1 = VIH, Enable 2 = V
IL
—
35
35
35
pF
l/O
Common O/I: HC4351
HC4353
ОООООООО
ОООООООО
ОООООООО
IH
, Enable 2 = V
IL
—
130
50
130
50
130
50
Feedthrough
ОООООООО
ОООООООО
ОООООООО
—
1.0
1.0
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package) (Figure 14)*
45 (HC4351)
45 (HC4353)
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
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