Motorola MC54HC4051A, MC54HC4052A, MC74HC4053AN, MC74HC4051ADW, MC74HC4051ADT Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1997

10/97

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    

High–Performance Silicon–Gate CMOS

The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE).

The HC4051A, HC4052A and HC4053A are identical in pinout to the metal–gate MC14051AB, MC14052AB and MC14053AB. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.

The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs.

These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches.

For a multiplexer/demultiplexer with channel–select latches, see HC4351A.

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V

• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V

• Improved Linearity and Lower ON Resistance Than Metal–Gate

Counterparts

• Low Noise

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates

HC4052A — 168 FETs or 42 Equivalent Gates HC4053A — 156 FETs or 39 Equivalent Gates

LOGIC DIAGRAM

MC54/74HC4051A

Single–Pole, 8–Position Plus Common Off

X0

13

X1

14

X2

15

X3

12

X4

1

X5

5

X6

2

X7

4

A

11

B

10

C

9

ENABLE

6

MULTIPLEXER/

DEMUL TIPLEXER

X

3

ANALOG

INPUTS/

CHANNEL

INPUTS

PIN 16 = V

CC

PIN 7 = V

EE

PIN 8 = GND

COMMON OUTPUT/ INPUT

1516 14 13 12 11 10

21 34567

V

CC

9

8

X2 X1 X0 X3 A B C

X4 X6 X X7 X5 Enable VEEGND

Pinout: MC54/74HC4051A (Top View)

OUTPUTS

SELECT

This document contains information on a new product. Specifications and information herein are subject to change without notice.

L L L L H H H H X

L L H H L L H H X

L H L H L H L H X

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



FUNCTION TABLE – MC54/74HC4051A

Control Inputs

ON Channels

Enable

Select

CBA

X0 X1 X2 X3 X4 X5 X6 X7

NONE

L L L L L L L L H

X = Don’t Care

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

ORDERING INFORMATION

MC54HCXXXXAJ MC74HCXXXXAN MC74HCXXXXAD MC74HCXXXXADW MC74HCXXXXADT

Ceramic Plastic SOIC SOIC Wide TSSOP

1

16

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

DW SUFFIX

SOIC WIDE PACKAGE

CASE 751G–02

1

16

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

LOGIC DIAGRAM

MC74HC4052A

Double–Pole, 4–Position Plus Common Off

X0

12

X1

14

X2

15

X3

11

Y0

1

Y1

5

Y2

2

Y3

4

A

10

B

9

ENABLE

6

X SWITCH

Y SWITCH

X

13

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

PIN 16 = V

CC

PIN 7 = V

EE

PIN 8 = GND

COMMON OUTPUTS/INPUTS

L

L H H X

L H L H X

FUNCTION TABLE – MC74HC4052A

Control Inputs

ON Channels

Enable

Select

BA

X0 X1 X2 X3

L L L L H

X = Don’t Care

Pinout: MC74HC4052A (Top View)

1516 14 13 12 11 10

21 34567

V

CC

9

8

X2 X1 X X0 X3 A B

Y0 Y2 Y Y3 Y1 Enable VEEGND

Y

3

Y0 Y1 Y2 Y3

NONE

LOGIC DIAGRAM

MC54/74HC4053A

Triple Single–Pole, Double–Position Plus Common Off

X0

12

X1

13

A

11

B

10

C

9

ENABLE

6

X SWITCH

Y SWITCH

X

14

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

PIN 16 = V

CC

PIN 7 = V

EE

PIN 8 = GND

COMMON OUTPUTS/INPUTS

L L L L H H H H X

L L H H L L H H X

L H L H L H L H X

FUNCTION TABLE – MC54/74HC4053A

Control Inputs

ON Channels

Enable

Select

CBA

L L L L L L L L H

X = Don’t Care

Pinout: MC54/74HC4053A (Top View)

1516 14 13 12 11 10

21 34567

V

CC

9

8

Y X X1 X0 A B C

Y1 Y0 Z1 Z Z0 Enable VEEGND

Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1

Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1

X0 X1 X0 X1 X0 X1 X0 X1

NONE

Y0

2

Y1

1

Y

15

Z0

5

Z1

3

Z

4

Z SWITCH

NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X–Switch, Input B controls the Y–Switch and Input C controls the Z–Switch

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

Î

V

CC

ОООООООООООО

Î

Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

ÎÎÎÎ

Î

– 0.5 to + 7.0

– 0.5 to + 14.0

Î

V

EE

Negative DC Supply Voltage (Referenced to GND)

– 7.0 to + 5.0

V

Î

V

IS

ОООООООООООО

Î

Analog Input Voltage

ÎÎÎÎ

Î

VEE – 0.5 to

VCC + 0.5

Î

V

Î

V

in

ОООООООООООО

Î

Digital Input Voltage (Referenced to GND)

ÎÎÎÎ

Î

– 0.5 to VCC + 0.5

Î

V

Î

I

ОООООООООООО

Î

DC Current, Into or Out of Any Pin

ÎÎÎÎ

Î

± 25

Î

mA

Î

P

D

ОООООООООООО

Î

ОООООООООООО

Î

Power Dissipation in Still Air, Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎ

Î

ÎÎÎÎ

Î

750 500 450

Î

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

Ceramic DIP

ÎÎÎÎ

Î

260 300

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur .

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

Positive DC Supply Voltage (Referenced to GND)

(Referenced to VEE)

2.0

6.0

12.0

V

ÎÎ

Î

V

EE

ОООООООООООО

Î

Negative DC Supply Voltage, Output (Referenced to GND)

Î

– 6.0

Î

GND

Î

V

IS

Analog Input Voltage

V

EEVCC

V

in

Digital Input Voltage (Referenced to GND)

GND

V

CC

V

VIO*

Static or Dynamic Voltage Across Switch

1.2

V

T

A

Operating Temperature Range, All Package Types

– 55

+ 125

_

C

ÎÎ

Î

ÎÎ

Î

tr, t

f

ОООООООООООО

Î

ОООООООООООО

Î

Input Rise/Fall Time VCC = 2.0 V

(Channel Select or Enable Inputs) VCC = 3.0 V

VCC = 4.5 V VCC = 6.0 V

Î

0 0 0 0

Î

1000

600 500 400

Î

ns

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

DC CHARACTERISTICS — Digital Section (V oltages Referenced to GND) V

EE

= GND, Except Where Noted

V

Guaranteed Limit

Symbol Parameter Condition

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

V

IH

Minimum High–Level Input Voltage, Channel–Select or Enable Inputs

Ron = Per Spec 2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

IL

Maximum Low–Level Input Voltage, Channel–Select or Enable Inputs

Ron = Per Spec 2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

V

I

in

Maximum Input Leakage Current, Channel–Select or Enable Inputs

Vin = VCC or GND, VEE = – 6.0 V

6.0 ±0.1 ± 1.0 ± 1.0 µA

I

CC

Maximum Quiescent Supply Current (per Package)

Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = – 6.0

6.0

1 4

10 40

20 80

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

DC CHARACTERISTICS — Analog Section

Guaranteed Limit

Symbol Parameter Condition V

CCVEE

–55 to 25°C ≤85°C ≤125°C

Unit

R

on

Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to

VEE; IS ≤ 2.0 mA (Figures 1, 2)

4.5

6.0

0.0 – 4.5 – 6.0

190 120 100

240 150 125

280 170 140

Ω

Vin = VIL or VIH; VIS = VCC or

VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2)

4.5

6.0

0.0 – 4.5 – 6.0

150 100

80

190 125 100

230 140 115

∆R

on

Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package

Vin = VIL or VIH; VIS = 1/2 (VCC – VEE); IS ≤ 2.0 mA

4.5

6.0

0.0 – 4.5 – 6.0

30 12 10

35 15 12

40 18 14

Ω

I

off

Maximum Off–Channel Leakage Current, Any One Channel

Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 3)

6.0 – 6.0 0.1 0.5 1.0

µA

Maximum Off–Channel HC4051A Leakage Current, HC4052A Common Channel HC4053A

Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 4)

6.0

– 6.0 – 6.0 – 6.0

0.2

0.1

2.0

1.0

4.0

2.0

I

on

Maximum On–Channel HC4051A Leakage Current, HC4052A Channel–to–Channel HC4053A

Vin = VIL or VIH; Switch–to–Switch = VCC – VEE; (Figure 5)

6.0

– 6.0 – 6.0 – 6.0

0.2

0.1

2.0

1.0

4.0

2.0

µA

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

V

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay , Channel–Select to Analog Output (Figure 9)

2.0

4.5

6.0

370

74 63

465

93 79

550 110

94

ns

t

PLH

,

t

PHL

Maximum Propagation Delay , Analog Input to Analog Output (Figure 10)

2.0

4.5

6.0

60 12 10

75 15 13

90 18 15

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

2.0

4.5

6.0

290

58 49

364

73 62

430

86 73

ns

t

PZL

,

t

PZH

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

2.0

4.5

6.0

345

69 59

435

87 74

515 103

87

ns

C

in

Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF

C

I/O

Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051A

HC4052A HC4053A

130

80 50

130

80 50

130

80 50

Feedthrough 1.0 1.0 1.0

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V , VEE = 0 V

C

PD

Power Dissipation Capacitance (Figure 13)* HC4051A

HC4052A HC4053A

45 80 45

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Motorola MC54HC4051A, MC54HC4052A, MC74HC4053AN, MC74HC4051ADW, MC74HC4051ADT Datasheet

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