Motorola MC33410FTA Datasheet
DUAL CVSD/PLL
CORDLESS PHONE
SYSTEM
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
Device
Operating
Temperature
Package
ORDERING INFORMATION
XC33410FTA –40° to +85°C LQFP–48
SEMICONDUCTOR
TECHNICAL DATA
Order this document by MC33410/D
1
MOTOROLA RF/IF DEVICE DATA
The MC33410 Dual CVSD/Cordless Phone system is designed to fit the
requirements of a 900 MHz digital cordless telephone system. The device
contains a CVSD (Continuously Variable Slope Delta
Modulator/Demodulator) Encoder to digitize the speech for the RF
transmission, and a CVSD Decoder to reconstruct the received digital
speech from the RF receiver. Provisions are made to transmit and receive
data as well. Included are three PLLs (Phase–Locked Loops). Two are
intended for use with external VCOs and 64/65 or 128/129 dual modulus
prescalers, and can control the transmit and receive (LO1) frequencies for
the 900 MHz communication. The third PLL is configured as the 2nd local
oscillator (LO2), and is functional to 80 MHz. Also included are muting, audio
gain adjust (internal and external), low battery/carrier detect, and a wide
range for the PLL reference frequency. The power supply range is 2.7 to
5.5 V. A data only (non–voice) mode is also included.
• Two Complete CVSD Sections for Full Duplex Operation
• Two PLLs and an LO Suitable for a 900 MHz System
• Adjustable Detection for Low Battery or Carrier Signal (RSSI)
• Minimal External Components
• Encode Path Includes Adjustable Gain Amplifiers, Filters, Mute, CVSD
Encoder, Data Insert, and Scrambler
• Decoder Path Contains Data Slicer, Clock Recovery, Descrambler, Data
Detect, CVSD Decoder, Filters, Mute and Power Amplifier
• Data can be Transmitted During Voice Conversation with Minimal or No
Noticeable Audio Disruption
• Idle Channel Noise Control
• Independent Power Amplifier with Differential Outputs, Mute
• Selectable Frequency for Switched Capacitor Filters, CVSD Function,
PLLs, and the LO
• Reference Frequency Source can be a Crystal or System Clock
• Serial µP Port to Control Gain, Mute, Frequency Selection, Phase
Detector Gain, Power Down Modes, Idle Channel Control, Scrambler
Operation, Low Battery Detect, and Others
• Mode Available for Data Only Transmission (non–voice)
• Ambient T emperature Range: –40 to 85
_
C
• Power Supply Range: 2.7 to 5.5 V
• Power Down Modes for Power Conservation
• 48 Pin LQFP with 0.5 mm Lead Pitch
This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.
Motorola, Inc. 1998 Rev 0
MC33410
2
MOTOROLA RF/IF DEVICE DATA
Simplified Block Diagram
CVSD
Decoder
Anti–Alias
LPF
Gain
Adj.
Gain
Adj.
Mute
LP Filter
PLL
#1
Programmable
Counters
Dec.
Clock
CVSD
Encoder
VCO+
64/65
PreScaler
–1
Power
Amp
PLL
#2
VCO+
64/65
PreScaler
2nd
LO
LPF
T ank
MPU
Interface
MPU
Low
Batt
/CD
Idle
Channel
Data Det.
Register
SC
Encode
Clock
LO
Data
Register
Low
Battery/
CD
Status
Dec.
Clock
Descrambler
Clock
Recovery
Idle
Channel
Scrambler
Data
Slicer
Data
Out
Digital
Speech/
Data In
Digital
Speech/
Data Out
Analog
Speech
Analog
Speech
Ref
LP Filter
Mute
Mute
Ref.
Freq.
Ref
SC
SC
PRELIMINARY SPECIFICATIONS (Subject to change)
Parameter
Symbol Min Typ Max Units
Supply Voltage – 2.7 to 5.5 – V
Supply Current (All sections active) – 13 – mA
Remote Gain Adjust Range – 16 – dB
Receive Path Gain Control Range – 28.5 – dB
Output Current Capability (PAO+, PAO–) – ±5.0 – mA
Max. 2nd LO frequency – 80 – MHz
Phase Detector Charge Pump Output Current µA
High – ±400 –
Low – ±100 –
Digital Input Signal Amplitude to Data Slicer – >200 – mVpp
Operating Ambient Temperature – –40 to +85 – °C
NOTE: 1.Above specs represent design objectives, and are subject to change.
MC33410
3
MOTOROLA RF/IF DEVICE DATA
Mod Ctl
Mod Ctl
Figure 1. Typical Applications Circuit
SCF Clk
SPI
Rx Dig.
MP2
Gnd
LO2 Out
LO2 V
CC
LO2+
LO2–
LO2 Ctl
LO2 Gnd
LO2PD
LO2 Gnd
MCI
Gnd
Out
F
ref
Out
F
ref
In
Status
FRx MC FR
x
PLL
V
CC
Rx PD PLL
Gnd
Tx PD
PLL
V
CC
FTxFTx MC EN CLK Data
Dec.
Out
R
x
Audio
In
PAI
Battery
2nd LO
VCO
14b Ctr.
LO2 Phase
Detector
7b A’
Rx Phase
Detector
13b N’
64/65 PS
VCO
Tx Phase
Detector
12b Ref. Ctr.
MPU Serial
Interface
÷
2
6b SCF Ctr.
12
48
25
14
13
7b A13b N
Scrambler
Low Battery/CD
SPI
Tx Data
Register
LPF
CVSD
Encoder
÷
16
6b Enc. Ctr.
16
15
17
18
19
20
21
22
23
24
1110987654321
47
46
45
44
43
42
41
40
39
38
37
4b Idle
Chan Ctr.
Idle
Chan
Ctrl
Battery
Battery
Tx 1010
Generator
2627282930313233343536
÷
32
Enc
Clk
16x
Clk
Clock
Recovery
V
CC
Battery
V
CC
Battery
Input
To CVSD
Encoder
VB
Idle
Chan
Control
SMTH
LPF
Mute
LPF
Mute
VB
AALPF
LPF
VB
Mute
Rem. Gain
Adjust
SCF
Clk.
Ref
Idle
Channel
Detect
R
VB
R
Descrambler
16x
Clk
CD
CVSD
Decoder
Rx 1010
Generator
Gain
Adjust
SCF Clk.
Data
BG Ref.
V
CC
CD
Rx Data
Register
Data
Detect
Status
SPI
Data
Slicer
MP1
Clk
VB
R
x
Audio
Out
Gnd PAO– PAO+ V
CC
Enc.
Cap
Dec.
Cap
Vag
0.1
V
CC
Enc. Out
Tx Audio
Enc. In
Battery
MCO
Audio
Input
LPF
64/65 PS
VCOLPF
To
Microprocessor
V
CC
PLL Ref. Freq.
Ref.
Clk
SPI
Low
Battery
Carr. Det.
NOTE: Pin numbers are not firm and are not to be used for design–in purposes.
MC33410
4
MOTOROLA RF/IF DEVICE DATA
RECOMMENDED OPERATING CONDITIONS (Subject to change)
Parameter
Symbol Min Typ Max Units
Supply Voltage – 2.7 to 5.5 – V
CVSD Clock Rate – 32, 50, or
64
– kHz
Encoder in Signal Level (max) – 3.0 – V
pp
Peak Output Current at PAO+, PAO– – ±5.0 – mA
Reference Frequency Amplitude (F
ref
In) – >200 – mVpp
Rx Digital Input Signal Amplitude V
pp
Min – 0.20 –
Max – 0 to V
CC
–
Crystal or Reference Frequency at Pin 14 – 4.0 to
18.25
– MHz
Max. Input Frequency at FRx, FT
x
– TBD – MHz
LO2 VCO Control Voltage (Pin 44) – TBD – V
Max. 2nd LO Frequency – 80 – MHz
12 Bit Reference Counter Range (Note 1) – 3 to 4095 – –
13 Bit N Counter Range (Note 1) – 3 to 8191 – –
7 Bit A Counter Range (Note 1) –
with a 64/65 Modulus Prescaler – 0 to 63 –
with a 128/129 Modulus Prescaler – 0 to 127 –
14 Bit LO2 Counter Range (Note 1) – 12 to
16383
– –
6 Bit Counters (for SCF and Encode Clock) (Note 1) – 3 to 63 – –
Receive Path Gain Control Code Range (Note 1) – 6 to 25 – –
Operating Ambient Temperature – –40 to 85 – °C
NOTES: 1. Values specified are pure numbers to the base 10.
2.Above specs represent design objectives, and are subject to change.
PIN FUNCTION DESCRIPTION
Pin
Name
Description
1 FRx MC Modulus Control Output to the Rx 64/65 or 128/129 dual modulus prescaler.
2 FR
x
Input to the Rx PLL.
3 PLL V
CC
Supply pin for the Rx PLL section. Allowable range is 2.7 to 5.5 V .
4 Rx PD Phase detector charge pump output of the Rx PLL.
5 PLL Gnd Ground pin for the PLL sections.
6 Tx PD Phase detector charge pump output of the Tx PLL.
7 PLL V
CC
Supply pin for the Tx PLL section and the MPU Serial Interface section. Allowable range is 2.7 to 5.5 V .
8 FT
x
Input to the Tx PLL.
9 FTx MC Modulus Control Output to the Tx 64/65 or 128/129 dual modulus prescaler.
10 EN Enable input for the µP port. This signal latches in the register address and data.
11 CLK Clock input for the µP port. Maximum frequency is 2.0 MHz.
12 Data Bi–directional data line for the µP port. In Data Modem mode, this pin provides the recovered clock.
13 Status Logic output which indicates that a predetermined 16 or 24–bit code word has been detected in the Data
Detect register, and the following data word has been loaded into register 10. In Data Modem mode, this
pin provides the Transmit Data clock.
14, 15 F
ref
In,
F
ref
Out
A crystal, in the range of 4.0 to 18.25 MHz can be connected to these pins to provide the reference
frequency. If an external reference source is used, it is to be capacitively coupled to F
ref
In.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33410
5
MOTOROLA RF/IF DEVICE DATA
PIN FUNCTION DESCRIPTION (continued)
Description
Name
Pin
16 Low Battery/CD An open collector output. When low, indicates either the supply voltage (VCC) is low, or the carrier level is
above the threshold. This output is off when disabled.
17 Enc Out The digital output of the scrambler, which passes data from the CVSD encoder, or the Tx Data register, or
the Tx 1010 Generator. Source selection is done through the mP port.
18 V
CC
Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V . Internally
connected to Pins 27 and 37.
19 Enc In The analog input to the CVSD encoder. Max. input level is 3.0 Vpp.
20 Tx Audio Out Output of the transmit speech processing section.
21 Ground Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 30 and 40.
22 MCO Output of the microphone amplifier, and input to the filters. This output has rail–to–rail capability.
23 MCI Inverting input of the microphone amplifier. Gain and frequency response is set with external resistors and
capacitors.
24 Enc Cap This capacitor sets the time constant for the CVSD encoder. This pin is sensitive to leakage.
25 VAG Analog ground for the audio section and the CVSD encoder and decoder.
26 Dec Cap The capacitor sets the time constant for the CVSD decoder. This pin is sensitive to leakage.
27 V
CC
Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V . Internally
connected to Pins 18 and 37.
28, 29 PAO+, PAO– Differential outputs of the power amplifier stage for driving an earpiece or hybrid network. The gain and
frequency response are set with external resistors and capacitors.
30 Gnd Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 40.
31 PAI Input to the power amplifier stage. This pin is a summing node.
32 Rx Audio Output Output of the receive speech processing section.
33 VB The capacitor filters the internal 1.5 V reference voltage. If VB is adjusted, it may be monitored at this pin.
Max. load current is 10 mA.
34 Rx Audio In Input to the receive speech processing section.
35 Dec Out The analog output of the CVSD decoder.
36 MP1 As an output, provides the recovered Rx data, or the Data Detect output, or the data slicer output. Or it can
be set to a high impedance input (600 kW) for the carrier detect input signal. Selection is done through the
m
P port. See Table 6.
37 V
CC
Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V . Internally
connected to Pins 18 and 27.
38 Rx Digital Input The digital stream from the RF receiver is applied to the data slicer at this pin. Minimum amplitude is 200
mVpp. Hysteresis ≈50 mV .
39 MP2 As an output, this pin provides the recovered clock from the Clock Recovery block. As an input, the CVSD
decoder clock can be applied to this pin. Or this pin may be set to a disabled state. Selection is done
through the mP port. See Table 7. In Data Modem mode, the data to be transmitted is input to this pin.
40 Gnd Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 30.
41 LO2 Out Buffered output of the 2nd LO frequency. A pullup resistor is required.
42 LO2 V
CC
Supply pin for the 2nd LO. Allowable range is 2.7 to 5.5 V .
43, 45 LO2+, LO2– A tank circuit is connected to these pins for the 2nd LO.
44 LO2 Ctl The varactor control pin for the 2nd LO.
46 LO2 Gnd Ground for the 2nd LO section.
47 LO2 PD Phase detector charge pump output of the 2nd LO PLL.
48 LO2 Gnd Ground for the 2nd LO section.
NOTE: 1. All VCC pins must be within ±0.5 V of each other.
MC33410
6
MOTOROLA RF/IF DEVICE DATA
FUNCTIONAL DESCRIPTION
Note: In the following descriptions, control bits in the MPU
Serial Interface for the various functions will be identified by
register number and bit number. For example, bit 3/19
indicates bit 19 of register 3. Bits 5/14–11 indicates register 5,
bits 14 through 11. Please refer to Figure 1.
Transmit Speech Processing Section
This section is made up of the externally adjustable
microphone amplifier (Pins 22 to 23), internally adjustable
gain stage, two low pass filters, and a mute switch.
The gain of the microphone amplifier is set with external
resistors to receive the audio from the microphone (in the
handset), or from the hybrid (in the base unit), or from any
other audio source. The MCO output has rail–to–rail
capability, and the dc bias level is at VB (≈1.5 V).
The adjustable gain stage, referred to as the Remote
Gain Adjust, provides 5 levels of gain in 4.0 dB increments.
It is controlled with bits 6/15–11 as shown in Table 1.
Table 1. Remote Gain Adjust
Register 6
Bits 15–11 Gain
00001 –8.0 dB
00010 –4.0 dB
00100 0 dB
01000 +4.0 dB
10000 +8.0 dB
Other combinations for the 5 bits are invalid.
The Low Pass Filter after the gain stage is a switched
capacitor filter with a corner frequency at 5.0 kHz. The
subsequent smoothing low pass filter has a corner frequency
at 30 kHz, and is designed to filter out high frequency clock
noise from the previously mentioned switched capacitor filter.
The mute switch at Pin 20 will mute a minimum of 60 dB.
Bit 6/2 controls the mute.
CVSD Encoder/Idle Channel/Tx Data Register
The analog signals to be digitized are input at Pin 19 to the
CVSD Encoder. The output of the encoder will be the digital
equivalent of the audio, at the selected clock rate. Based on
the reference frequency, bits 4/23–18 are used to set the 6 Bit
Encoder Counter, in conjunction with the subsequent ÷16
divider, to set the CVSD Encoder frequency to 32, 50, or
64 kHz. Bits 3/16–15 will set the CVSD for proper operation
at the selected frequency, according to Table 2.
Table 2. CVSD Clock/Data Rates
Register 3
Bit 16 Bit 15 Clock/Data Rate
0 1 32 kHz
1 0 50 kHz
1 1 64 kHz
The Encoder’s minimum step size can be selected using
bits 2/22–21, according to Table 3.
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Table 3. Minimum Step Size
Encoder
Register 2
Bits 22, 21
Decoder
Register 1
Bits 22, 21
Step Size
00 00 No minimum
01 01 1.4 mV
10 10 5.6 mV
11 11 22.4 mV
The Tx 1010 Generator, when selected, provides an
alternating “1–0” pattern (a square wave at half the CVSD
clock rate) to the scrambler. This represents the lowest
amplitude analog signal, and can be used when it is desired
to send a quiet signal. Selection of this block can occur either
automatically , or intentionally, as follows:
a. The automatic selection occurs when the Idle Channel
Detector senses the average audio signal at Pin 19 is
below a threshold which is set with bits 5/17–15 (See
T able 4). Bits 5/14–11 select a time delay for the automatic
threshold detection to occur. The minimum delay is zero,
with these bits set to 0000. Changing the bits provides
delay in increments of 32 clock cycles (of the CVSD
Encoder clock). The maximum delay is 480 clock cycles,
(7.5 mS at 64 kHz). When the average audio signal at
Pin 19 increases above the threshold, the Tx 1010
Generator will be deselected with no delay. This automatic
switchover feature can be disabled with bit 7/2. Bit 5/21
indicates when an idle channel condition has been
detected. This output bit will be functional even when the
idle channel detector is disabled with bit 7/2. Bit 5/18 will
power down the Idle Channel Detect Circuit as a power
saving measure.
b. Bit 6/4 can be used to intentionally select the Tx 1010
Generator at any time.
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Table 4. Idle Channel Detection Threshold
ÁÁÁÁ
Register 5
Register 5
Bits 17–15
Threshold Bits 17–15 Threshold
000 –50 dBV 100 –60 dBV
001 –52.5 101 –62.5
010 –55 110 –65
011 –57.5 111 –67.5
The Tx Data Register is used for the transmission of data
between the handset and base units. The procedure is as
follows:
a. At the receiving unit: The code word (16 or 24 bits, set with
bit 7/11) identifying that a data transmission is occurring
must be loaded into the Tx Data Register (by loading
register 8). This is used to detect when a code word is sent
from the transmitting unit.
b. At the transmitting unit: The same code word as above is
loaded into register 8. It is automatically loaded into the T
x
Data Register.
c. The data word (16 or 24 bits, set with bit 7/12) is then loaded
into register 9.
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