MOTOROLA MC14584BFR2, MC14584BCP, MC14584BD, MC14584BDR2, MC14584BDT Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14584B/D

MC14584B

Hex Schmitt Trigger

The MC14584B Hex Schmitt Trigger is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity to “square up” slowly changing waveforms.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range

• Double Diode Protection on All Inputs

• Can Be Used to Replace MC14069UB

• For Greater Hysteresis, Use MC14106B which is Pin–for–Pin

Replacement for CD40106B and MM74Cl4

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

http://onsemi.com

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14584BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14
DT SUFFIX

CASE 948G

1

14

14584B

AWLYWW

14

584B

ALYW

1

14

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14584B

AWLYWW

Device Package Shipping

ORDERING INFORMATION

MC14584BCP PDIP–14 2000/Box
MC14584BD SOIC–14 55/Rail
MC14584BDR2 SOIC–14 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MC14584BDTEL TSSOP–14 2000/Tape & Reel

MC14584BDT TSSOP–14 96/Rail

MC14584BF SOEIAJ–14 See Note 1.
MC14584BFEL SOEIAJ–14 See Note 1.

MC14584B

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2

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 5

IN 5

OUT 6

IN 6

V

DD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

V

SS

OUT 3

IN 3

LOGIC DIAGRAM

13

11

9

5

3

1

12

10

8

6

4

2

V

DD

= PIN 14

V

SS

= PIN 7

EQIVALENT CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

MC14584B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= V

DD

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

Vin = 0 “1” Level V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

0.25

0.5

1.0

—
—
—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—
—
—

7.5
15
30

µAdc

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0
10
15

IT = (1.8 µA/kHz) f + I

DD

IT = (3.6 µA/kHz) f + I

DD

IT = (5.4 µA/kHz) f + I

DD

µAdc

Hysteresis Voltage VH

(7.)

5.0
10
15

0.27

0.36

0.77

1.0

1.3

1.7

0.25

0.3

0.6

0.6

0.7

1.1

1.0

1.2

1.5

0.21

0.25

0.50

1.0

1.2

1.4

Vdc

Threshold Voltage

Positive–Going

V

T+

5.0
10
15

1.9

3.4

5.2

3.5

7.0

10.6

1.8

3.3

5.2

2.7

5.3

8.0

3.4

6.9

10.5

1.7

3.2

5.2

3.4

6.9

10.5

Vdc

Negative–Going V

T–

5.0
10
15

1.6

3.0

4.5

3.3

6.7

9.7

1.6

3.0

4.6

2.1

4.6

6.9

3.2

6.7

9.8

1.5

3.0

4.7

3.2

6.7

9.9

Vdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

7. V

H

= VT+ – VT– (But maximum variation of VH is specified as less than V

T + max

– V

T – min

).