Motorola MC145750VFU Datasheet

MC145750MOTOROLA

1

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The MC145750 is a silicon gate HCMOS device designed to encode π/4–shift QPSK baseband signals. The device contains two 10–bit DACs for the I/Q signal, Root–Nyquist digital filtering, and burst rising and falling e dge processing for digital RF communication equipment. Primary applications for this device are in products that will be used in PHS (384 kbps) and PDC (42 kbps). It will perform up to 800 kbps data rate. It also contains PN511 random pattern generator and timing generator with PLL.

• Root–Nyquist Digital Filtering (Coefficient = 0.5)

• Burst Edge Processing Circuitry (Ramp–Up and –Down)

• Two 10–Bit DACs for I/Q Output

• Operating Voltage Range: 2.7 to 5.5 V

• PN511 Random Pattern Generator

• Conformance to RCR Standard for PHS, PDC

• Variable Data Transmission Rate up to 800 kbps (VDD = 5 V)

• Timing Generator with PLL

• QPSK Mode, Burst, and Continuous I/Q Signal Output is Performed

• Companion Device is MRFIC0001

PIN ASSIGNMENT

NC

CF

PCO

PB1

PLL

ECLK

DV

DD

DV

SS

DCLK

DS/STBY

TXD

MODE1

MODE0

TEST

NC

DRATE

QPSK

PB2NCNC

TB0

TB1

NC

TB7

BW/TB9

TNO/TB8

I

out

DAref2

DAref3

DAref

DAref1

Q

out

DAV

SS

DV

DD

NC

TB2

TB4

TB5

TB6

NC

MODE2

ERST/PDN

DAV

DD

TB3

DV

SS

NC

DAb

1

48

37

36

25

24

13

12

NC = NO CONNECTION

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MC145750/D

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SEMICONDUCTOR TECHNICAL DATA



VFU SUFFIX

PLASTIC VQFP

CASE 932

ORDERING INFORMATION

MC145750VFU VQFP

 Motorola, Inc. 1995

REV 2 10/95

MC145750 MOTOROLA 2

BLOCK DIAGRAM

PNO/TB8

TXD

DS/STBY

DCLK

PLL

ECLK

I

out

Q

out

BW/TB9

TEST TB7:0 M2:0 QPSK DRATE DAb DAref DAref3:1

PN PATTERN GENERATOR

TEST

CIRCUIT

π

/4–SHIFT

QPSK

ENCODER

INTERFACE

CIRCUIT

ROLL–OFF

FILTERS

10–BIT

DAC

10–BIT

DAC

DPLL

TIMING

GENERATOR

DVDDDV

SS

ERST

/PDN Cf PC0 PB1 PB2 DAV

DD

DAV

SS

I

Q

INPUT/OUTPUT TIMING RELATIONS

DS

(INPUT)

DCLK

(INPUT)

TXD

(INPUT)

BW

(OUTPUT)

I

out/Qout

(OUTPUT)

RAMP–UP

(TWO SYMBOL LENGTH)

100% OUTPUT SWING LEVEL

RAMP–DOWN

(TWO SYMBOL LENGTH)

FIRST SYMBOL

LAST SYMBOL

DON’T CARE

1 2 3 4 5 6 7 8 9

n – 1

n 1 2 3 11 14 15 16

9 10

n BIT

MC145750MOTOROLA

3

MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

DC Supply Voltage

V

DD

– 0.5 to + 7

V

DC Input Voltage

V

in

– 0.5 to VDD + 0.5

V

Power Dissipation

P

D

500

mW

Storage Temperature

T

stg

– 65 to +150

°C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

DC Supply Voltage V

DD

2.7 3.3 5.5 V

DC Input Voltage V

in

0 — V

DD

V

Operating Temperature Range T

A

– 20 25 85 °C

ELECTRICAL CHARACTERISTICS (T

A

= 25°C, TXD = L, Normal Mode)

Parameters

Symbol Condition Min Typ** Max Unit

DC Supply Current

I

dd1

ERST = L — 0.25 0.5

mA

VDD = 3 V

DRATE = L I

dd2

DS = L

— 5.0 6.0

DRATE = H I

dd3

— 1.5 1.8

DRATE = L I

dd4

DS = Burst Input*

— 5.0 6.0

DRATE = H I

dd5

— 1.5 1.8

DRATE = L I

dd6

DS = Continual Input

— 8.0 10.0

DRATE = H I

dd7

— 2.0 2.6

DC Supply Current

I

dd1

ERST = L — 0.5 3.0

mA

VDD = 5 V

DRATE = L I

dd2

DS = L

— 27.0 33.0

DRATE = H I

dd3

— 17.0 19.0

DRATE = L I

dd4

DS = Burst Input*

— 30.0 33.0

DRATE = H I

dd5

— 18.0 20.0

DRATE = L I

dd6

DS = Continual Input

— 33.0 37.0

DRATE = H I

dd7

— 18.0 20.0

*625 µs burst/5 ms period (DRATE = L) at DCLK = 384 kHz.

6.6 ms burst/20 ms period (DRATE = H) at DCLK = 42 kHz.

**Typical numbers are not guaranteed.

ANALOG CHARACTERISTICS (T

A

= 25°C)

Parameters

Symbol Condition Min Typ** Max Unit

Output Swing Level

VDD = 3 V

V

out

RL = k

Ω, TXD = L

500 550 600

mV p–p

I/Q Out

VDD = 5 V

Normal Mode

520 570 620

Output Swing Imbalance ∆V

out

– 0.5 0 0.5 dB

Output DC Level

VDD = 3 V

V

out

DS = L

800 820 840

mV

I/Q Out

VDD = 5 V 780 800 820

Output Swing Imbalance ∆V

DD

— — 20

Out–of–Band Noise Level VDD = 5 V V

in

600 kHz — – 50 —

dB

900 kHz — – 55 —

DC Output Resistance R

out

I

out/Qout

— 50 100 Ω

*DAref1 = H at VDD = 3 V, DAref3 = H at VDD = 5 V

**Typical numbers are not guaranteed.

MC145750 MOTOROLA 4

SWITCHING CHARACTERISTICS (T

A

= 25°C)

Parameters Symbol Condition Min Typ* Max Unit

Input Voltage

High–Level V

IH

VDD x 0.7 — —

V

Low–Level V

IL

— — VDD x 0.3

Output Voltage

High–Level V

OH

BW, PNO

VDD x 0.9 — —

Low–Level V

OL

— — VDD x 0.1

Data Set–Up Time t

su

TXD, DS, STBY 10 — —

ns

Data Hold Time t

h

TXD, DS, STBY 10 — —

Data Output Propagation Delay t

pd

BW, PNO — 1.5 3

µs

I/Q Output Propagation Delay T

D

I

out

, Q

out

— 4 6

Data Rate VDD = 3 V

DRATE = L — — 450

kbps

DRATE = H — — 55

VDD = 5 V

DRATE = L — — 800

DRATE = H — — 100 Clock Input Duty Cycle DCLK 45 50 55 % VCO Oscillation Frequency

VDD = 3 V f

VCO1

— — 20

MHz

VDD = 5 V f

VCO2

— — 32

* Typical numbers are not guaranteed.

Figure 1. Timing Diagram

DS

DCLK

TXD

BW

I

out/Qout

PNO

t

su

t

su

1/fclk

t

PD

t

h

t

su

t

h

t

PD

t

su

t

h

t

D

t

PD

t

D