Motorola MC145017P, MC74HCT573ADT, MC74HCT573ADW Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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High–Performance Silicon–Gate CMOS

The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high–impedance state. Thus, data may be latched even when the outputs are not enabled.

The HCT573A is identical in function to the HCT373A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HCT573A is the noninverting version of the HC563A.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 10 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 234 FETs or 58.5 Equivalent Gates

— Improved Propagation Delays — 50% Lower Quiescent Power

LOGIC DIAGRAM

D0 D1 D2

DATA

INPUTS

D3 D4

D5 D6 D7

LATCH ENABLE

OUTPUT ENABLE

Design Criteria

Internal Gate Count*

219 3 4 5 6 7 8 9

11 1

16 15

14 13

PIN 20 = V PIN 10 = GND

NONINVERTING

Q3 Q4

Q5 Q6 Q7

Value

58.5

OUTPUTS

Units

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

ORDERING INFORMATION

MC74HCTXXXAN MC74HCTXXXADW MC74HCTXXXADT

Plastic SOIC TSSOP

PIN ASSIGNMENT

OUTPUT

ENABLE

D0 D1 D2

D3 5 D4 D5 D6

GND

1 2

3 4

6 7 8

9 10

20 19

18 17 16 15 14 13 12

V Q0

Q1 Q2 Q3 Q4 Q5 Q6 Q7

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change

HXXZ

X = Don’t Care Z = High Impedance

Internal Gate Propagation Delay Internal Gate Power Dissipation

ОООООООО

Speed Power Product

*Equivalent to a two–input NAND gate.

10/96

 Motorola, Inc. 1996

1.5

5.0

ÎÎ

0.0075

µW

ÎÎ

REV 7

MC74HCT573A

Current

GND, Other Inputs

MAXIMUM RATINGS*

Symbol

I I

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

out

DC Input Current, per Pin

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air Plastic DIP†

ОООООООООООО

Storage Temperature

stg

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: –6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Vin, V

tr, t

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Symbol

ÎÎ

ÎÎÎОООООООÎООООООО

ÎÎ

∆I

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ООООООО

Minimum High–Level Input Voltage

Maximum Low–Level Input

ООООООО

Voltage Minimum High–Level Output

Voltage

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State

Leakage Current

ООООООО

Maximum Quiescent Supply

ООООООО

Current (per Package) Additional Quiescent Supply

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, TSSOP or SOIC Package)

Parameter

ООООООО

Test Conditions

= 0.1 V or VCC – 0.1 V

out

| v 20 µA

out

= 0.1 V or VCC – 0.1 V

out

ООООООО

| v 20 µA

out

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 6.0 mA

out

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 6.0 mA

out

Vin = VCC or GND Output in High–Impedance State

Vin = VIL or V

ООООООО

= VCC or GND

out

Vin = VCC or GND

ООООООО

v 0 µA

out

Vin = 2.4 V, Any One Input

out

= 0 µA

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 25 ± 50

750 500

ÎÎÎÎ

450

ÎÎÎÎ

– 65 to + 150

ÎÎÎÎ

260

Min

4.5 0

– 55

Max

5.5

+ 125

500

Unit

V V

V mA mA mA

Unit

ÎÎ

4.5

5.5

4.5

ÎÎ

5.5

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

4.5

5.5

ÎÎ

5.5

ÎÎ

5.5

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Guaranteed Limit

– 55 to

ÎÎ

25_C

ÎÎ

± 0.1 ± 0.5

ÎÎ

≥ – 55_C

2.0

0.8

4.4

5.4

3.98

0.1

0.26

4.0

2.9

ÎÎ

85_C

2.0

0.8

ÎÎ

0.8

4.4

5.4

ÎÎ

3.84

0.1

ÎÎ

0.33

± 1.0 ± 5.0

ÎÎ

25_C to 125_C

ÎÎ

2.4

out

125_C

2.0

0.8

4.4

5.4

3.7

0.1

0.4

± 1.0

± 10

160

) v VCC.

Unit

µA µA

µA

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

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