MC141800A is a CMOS LCD Driver which consists of 193 high voltage
LCD driving signals to drive 128 Segment and 65 Common display. It has
6800-series parallel, IIC serial interface and Serial Peripheral interface (SPI)
capability for operating with general MCU. Besides the general LCD driver
features, it has on chip LCD Smart Bias Divider circuit such that minimize
external component required in applications.
MC141800AT: TAB (Tape Automated Bonding)
MCC141800AZ: Gold Bump Die
•Single Supply Operation, 2.4 V - 3.5 V
•Maximum 16.5V LCD Driving Output Voltage
•Low Current Stand-by Mode (<1uA)
•On Chip Internal DC/DC Converter / External Power Supply
•Smart Bias Divider
•4X / 5X DC-DC Converter
•8 bit 6800-series Parallel Interface, 1 MHz IIC Serial Interface and
Serial Peripheral Interface (SPI)
•On chip Oscillator
•Graphic Mode Operation
•On Chip 128 x 65 Display Data RAM
•Master Clear RAM
•Low Power Icon Mode (128 icons, <25uA)
•Display Masks for Implementation of Blinking Effect
•1 to 65 Selectable Multiplex Ratio
•1:7 / 1:9 Bias Ratio
•Re-mapping of Row and Column Drivers
•16 level Internal Contrast Control
•External Contrast Control
•Built-in Temperature Compensation Circuit
•Selectable Display Waveform: Type B or Type C Waveform
•2V Icon Mode Display On
MC141800A
MC141800AT
TAB
MCC141800AZ
Gold bump die
ORDERING INFORMATION
MC141800AT70 mm TAB
MCC141800AZGold Bump Die
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
25mA
Operating Temperature-30 to +85˚C
Storage Temperature Range-65 to +150˚C
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage
higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that V
and V
in
range VSS < or = (Vin or V
be constrained to the
out
) < or = VDD. Reliability
out
of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left
open. This device may be light sensitive. Caution
should be taken to avoid exposure of this device to
* Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descrip-
any light source during normal operation. This
device is not radiation protected.
tion section.
VSS = AVSS = DVSS (DVSS = VSS of Digital circuit, AVSS = VSS of Analogue Circuit)
VDD = AVDD = DVDD (DVDD = VDD of Digital circuit, AVDD = VDD of Analogue Circuit)
ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, VDD=2.4 to 3.5V, TA=25˚C)
SymbolParameterTest ConditionMinTypMaxUnit
DV
AV
Logic Circuit Supply Voltage Range
DD
Voltage Generator Circuit Supply Voltage Range
DD
I
Access Mode Supply Current Drain
AC
(AVDD + DVDD Pins)
I
Display Mode Supply Current Drain
DP
(AVDD + DVDD Pins)
(Absolute value referenced to VSS)2.4
2.4
VDD=3.0V, Internal DC/DC Converter On, 5X DC/DC
Converter Enabled, R/W accessing, T
=1MHz,
cyc
Osc. Freq.=50KHz, Display On.
VDD=3.0V, Internal DC/DC Converter On, 5X Converter Enabled, R/W Halt, Osc. Freq.=50KHz, Display On.
AC ELECTRICAL CHARACTERISTICS (TA=25˚C, Voltage referenced to VSS, AVDD=DVDD=3V)
SymbolParameterTest ConditionMinTypMaxUnit
F
F
Oscillation Frequency of Display timing generator 60Hz Frame Frequency
OSC
Either External Clock Input or Internal Oscillator
Enabled
Frame FrequencyGraphic Display Mode, Normal Frequency Mode,
FRM
65 - 49 MUX
456055KHz
-
F
OSC
-
15 * MUX
Hz
OSCInternal Oscillation Frequency with different value
of feedback resistor
Graphic Display Mode, Half Frequency Mode,
65 - 49 MUX
Graphic Display Mode, Normal Frequency Mode,
48 - 33 MUX
Graphic Display Mode, Half Frequency Mode,
48 - 33 MUX
Graphic Display Mode, Normal Frequency Mode,
32 - 2 MUX
Graphic Display Mode, Half Frequency Mode,
32 -2 MUX
6-Phase Low Power Icon Mode, Normal Frequency
Mode
6-Phase Low Power Icon Mode, Half Frequency
Mode
4-Phase Low Power Icon Mode, Normal Frequency
Mode
4-Phase Low Power Icon Mode, Half Frequency
Mode
Internal Oscillator Enabled, VDD within operation
range
-
F
OSC
-
30 * MUX
-
F
OSC
-
23 * MUX
F
-
-
OSC
46 * MUX
F
OSC
-
-
30 * MUX
F
-
-
OSC
60 * MUX
F
OSC
-
-
960
-
F
OSC
-
1920
-
F
OSC
-
1024
-
F
OSC
-
2048
See Figure 1 for the relationship
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Oscillation
Frequency
(Hz)
280k
260k
90k
70k
50k
30k
10k
100k500k1.0M1.5M2.0M
Resistor Value between OSC1 and OSC2 (Ω)
Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value
MC141800AMOTOROLA
3–283
TABLE 3. Parallel Timing Characteristics (TA=-30 to 85˚C, DVDD=2.4 to 3.5V, VSS=0V)
SymbolParameterMinTypMaxUnit
t
cycle
t
t
DSW
t
DHW
t
DSR
t
DHR
t
ACC
PW
PW
t
AS
AH
EL
EH
t
R
t
F
Clock Cycle Time1000--ns
Address Setup Time90--ns
Address Hold Time60--ns
Write Data Setup Time210--ns
Write Data Hold Time75--ns
Read Data Setup Time250--ns
Read Data Hold Time75--ns
Access Time--250ns
Enable Low Pulse Width390--ns
Enable High Pulse Width390--ns
Rise Time--45ns
Fall Time--45ns
TABLE 4. IIC Serial Timing Characteristics (TA=-30 to 85˚C, DVDD=2.4 to 3.5V, VSS=0V)
100kHz400kHz1MHz
SymbolParameter
t
cycle
t
HSTART
t
t
t
SSTART
Clock Cycle Time10--2.5--1--µs
Start condition Hold Time4.0--0.6--0.3--µs
Data Hold Time500--300--150--ns
HD
Data Setup Time250--100--50--ns
SD
Start condition Setup Time (Only relevant for a
repeated Start condition)
t
SSTOP
t
IDLE
Stop condition Setup Time4.0--0.6--0.3--µs
t
Rise Time for data and clock pin--1000--300--150ns
R
t
Fall Time for data and clock pin--300--300--150ns
F
Idle Time before a new transmission can start4.7--1.3--0.6--µs
MinTypMaxMinTypMaxMinTypMax
4.7--0.6--0.3--µs
Unit
SDA
CLK
t
HSTART
t
cycle
()(
)
t
HD
t
F
t
t
R
SD
t
SSTART
()(
)
t
IDLE
t
SSTOP
Figure 3. IIC Serial Interface Timing Characteristics
MC141800AMOTOROLA
3–285
P
STOP
CONDITION
P
STOP
CONDITION
ACK
)
)
(
)
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
9
ACK
)
(
)
(
)
(
)
(
)
(
)
(
1 - 8
DATA
)
(
)
(
)
(
)
(
)
(
)
(
ACK
CR/W
D/
(A0)
9
1 - 8
ACK
ACK
DATA
ACK
CR/W
D/
(A0)
SDA
(From controller)
SDA
(From Driver)
A1
A2
Figure 4. IIC Serial Interface Input Protocol (Write Data to Driver)
ADDRESS
23456789
1
S
START
CONDITION
CLK
SDA
SDA
(From controller)
(From Driver)
A1
A2
ADDRESS
Figure 5. IIC Serial Interface Output Protocol (Read Data from Driver)
23456789
1
S
START
CONDITION
CLK
MC141800A
3–286
MOTOROLA
TABLE 5. SPI Timing Characteristics (TA=-30 to 85˚C, DVDD=2.4 to 3.5V, VSS=0V)
SymbolParameterMinTypMaxUnit
t
cycle
t
LEAD
t
LAG
t
DSW
t
DHW
t
DVR
t
DHR
t
ACC
t
DIS
t
CLKL
t
CLKH
t
R
t
F
Clock Cycle Time1000--ns
Enable Lead Time500--ns
Enable Lag Time500--ns
Write Data Setup Time100--ns
Write Data Hold Time100--ns
Read Data Valid Time--240ns
Read Data Hold Time10--ns
Access Time--120ns
Disable Time--240ns
Clock Low Time380--ns
Clock High Time380--ns
Rise Time--100ns
Fall Time--100ns
CE
CLK
Dout
Din
t
ACC
t
LEAD
t
CLKH
t
DSW
t
F
t
CLKL
t
cyc
t
DVR
MSB
t
DHW
MSB
Figure 6. SPI Timing Characteristics
)
()(
t
R
)
()(
)
()(
)
()(
t
)
()(
)
()(
DHR
t
LAG
LSB
LSB
t
DIS
MC141800AMOTOROLA
3–287
PIN DESCRIPTIONS
S/P (Serial / Parallel Interface)
This pin is an input pin. The pin is sampled out when reset to
determine what type of interface is desired. The S/P pin input HIGH
for serial interface while input LOW for parallel interface.
For internal oscillator mode, this is an output for the internal low
power RC oscillator circuit. For external oscillator mode, OSC2 will
be an input pin for external clock and no external resistor is needed.
D/C (Data / Command)
If parallel interface is selected, this input pin acknowledges the
LCD driver the input at D0-D7 is data or command. Input High for
data while input Low for command. If serial interface is selected, float
this pin.
CLK (Input Clock)
This pin is normal Low clock input. If parallel interface is selected,
data on D0-D7 are latched at the falling edge of CLK. If IIC serial
interface is selected, data on SDA is latched at the falling edge of
CLK. If SPI is selected, data on Din and Dout are latched at the falling edge of CLK.
RES (Reset)
A Low input pulse to this pin resets the internal status of the driver
(same as power on reset). The minimum pulse width is 10 µs.
CE (Chip Enable)
If parallel interface is selected, this input pin is used for chip
enable. If IIC serial interface is selected, leave this pin float and it will
be internally tied to VDD.
D0 - D7 (Data)
This bi-directional bus is used for data / command transferring. If
parallel interface is selected, D0 - D7 are connected directly to MCU
for data transfer. When serial interface is selected, D7 (IIC/SPI) is an
input pin to determine which type of serial interface is desired. The
IIC/SPI pin HIGH indicates IIC interface is used. The IIC/SPI pin
LOW indicates SPI is used.
When IIC serial interface is selected, D0 (SDA) is connected
directly to MCU for data transfer, D1 (A1) and D2 (A2) are used to
define the 2 bit programmable address. The address of this device is
0111xyab where x, y, a, b represent A2, A1, D/C and R/W respectively.
When SPI is selected, D3 (Din) is used to write data / command
from MCU to driver and D4 (Dout) is used to read data / command to
MCU from driver.
R/W (Read / Write)
If parallel interface is selected, this is an input pin. To read the display data RAM or the internal status (Busy / Idle), pull this pin High.
The R/W input Low indicates a write operation to the display data
RAM or to the internal setup registers. If serial interface is selected,
let this pin float.
OSC1 (Oscillator Input)
For internal oscillator mode, this is an input for the internal low
power RC oscillator circuit. In this mode, an external resistor of certain value should be connected between the OSC1 and OSC2 pins
for a range of internal operating frequencies (refer to Figure 1). For
external oscillator mode, OSC1 should be left open.
VLL6 - VLL2
Group of voltage level pins for driving the LCD panel. They can
either be connected to external driving circuit for external bias supply
or connected internally to built-in divider circuit if internal divider is
enable.
C1N and C1P, C2N and C2P, C3N and C3P
If Internal DC/DC Converter is enabled, a 0.1 µF capacitor is
required to connect these three pair of pins.
VR and V
trol) of VLL1 to VLL6. For adjusting the LCD driving voltage, it
requires a feedback resistor placed between VR and VF, a gain control resistor placed between VF and AVSS, a 10 µF capacitor placed
between VR and AVSS. (Refer to the Application Circuit)
COM0-COM63, COM64A and COM64B (Row Drivers)
0V during display off. COM64A and COM64B are icon lines with
same signal output so as to provide the flexibility to hav e the icon line
on top or bottom of panel, or both top and bottom of the panel.
COM64A/B also serves as the common driving signal in the icon
mode.
special commands to program it separately (e.g. Set Icon Mask,
Smart Icon Mode, Low Power Icon Mode)
SEG0-SEG127 (Column Drivers)
They output 0V during display off.
AVDD and AVSS
verter. AVSS is ground.
VCC
this pin to AVSS is required. It can also be an external bias input pin
if Internal DC/DC Converter is not used. Power is supplied to the
LCD Driving Level Selector and HV Buffer Cell with this pin. Normally, this pin is not intended to be a power supply to other component.
DVDD and DVSS
these two pins. DVDD is power and DVSS is ground.
F
This is a feedback path for the gain control (external contrast con-
These pins provide the row driving signal to LCD panel. Output is
COM64A/B is special design icon line (128 icons). There are some
These 128 pins provide LCD column driving signal to LCD panel.
AVDD is the positive supply to the LCD bias Internal DC/DC Con-
For using the Internal DC/DC Converter, a 0.1 µF capacitor from
Power is supplied to the digital control circuit of the driver using
MC141800A
3–288
MOTOROLA
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
Command Decoder and Command Interface
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/C pin. If D/C high, data is written to Graphic Display
Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is
interpreted as a Command.
Reset is of same function as Power ON Reset (POR). Once RES
received the reset pulse, all internal circuitry will back to its initial status. Refer to Command Description section for more information.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0D7), R/W, D/C, CE and the CLK. The R/W input High indicates a
read operation from the Graphic Display Data RAM (GDDRAM). R/W
input Low indicates a write operation to Display Data RAM or Internal
Command Registers depending on the status of D/C input. The CLK
input serves as data latch signal (clock). Refer to AC operation conditions and characteristics section for Parallel Interface Timing
Description.
MPU Serial IIC Interface
The IIC interface consists of two communication bus: data pin
SDA and clock pin CLK. The CLK input serves as data latch signal
(clock). Before communication begins, a start condition must be
setup on the bus by the controller. To establish a start condition, the
controller must pull the data pin low while the clock pin is high.
After the start condition has been established for t
eight-bit address should be sent. The six most significant bits of the
address (0111xy) are used to uniquely define devices on the bus, the
7th bit is used as a data / command control: if it is 0, then the signal
on SDA is interpreted as a command; if it is 1, then data SDA is written to GDDRAM. The least significant bit is a data direction read /
write control; if it is 0, then the controller writes data / command to the
driver; if it is 1, then the controller reads data / command from LCD
driver.
Data is transferred with the most significant bit first. Each byte has
to be followed by an acknowledge bit. The transmitter releases the
SDA high during the acknowledge clock pulse. The receiver has to
pull down the SDA during the acknowledge clock pulse.
To end communication, a stop condition should be set up on the
bus. A low to high transition of data pin while the clock pin is high
defines a stop condition. However, if a master still wishes to communicate on the bus, another start condition and address can be generated without a stop condition. Refer to AC operation conditions and
characteristics section for IIC Serial Interface Timing Description.
HSTART
, an
MPU Serial Peripheral Interface
The SPI consists of 4 communication bus: data input pin Din, data
output pin Dout, clock pin CLK and chip enable pin
input serves as data latch signal (clock).
Data is transferred serially with most significant bit first, least significant bit last. During the communication, the controller must input
Low CE before data transactions and must stay low for the rest of the
transaction. By default, the LCD driver will receive command from
MCU. If messages on the data pin are data rather than command,
MCU should send Data Direction command (0100100X0) to control
the data direction and then one more command to define the number
of data bytes will be read / write. After these two continuous commands are send, the following messages will be data rather than
command. For read operation (X0= 1), MCU reads a group of data
from LCD driver through Dout pin. For write operation (X0= 0), MCU
writes a group of data to the LCD driver through Din pin. Refer to AC
operation conditions and characteristics section for Serial Peripheral
Interface Timing Description.
CE. The CLK
MC141800AMOTOROLA
3–289
Column address 00H
Column address 7FH
Row 0
Row 63
Page 9
LSB
Page 1
MSB
LSB
Page 2
MSB
LSB
Page 8
MSB
LSBRow 64
Seg0
Note: The configuration in parentheses represent the remapping of Rows and Columns in 65 MUX mode
Com0
(Com63)
Com63
(Com0)
Com64 (icon)
Seg127
MC141800A
3–290
Figure 7. Graphic Display Data RAM (GDDRAM) Address Map
MOTOROLA
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern
to be displayed. The size of the RAM is determined by number of row
times the number of column (128x65 = 8320 bits). Figure 7 is a
description of the GDDRAM address map. For mechanical flexibility,
re-mapping on both Segment and Common outputs are provided.
Display Timing Generator
This module is an on chip low power RC oscillator circuitry (Figure 8). The oscillator frequency can be selected in the range of
15kHz to 250kHz by external resistor. One can enable the circuitry by
software command. For external clock provided, feed the clock to
OSC2 and leave OSC1 open.
Internal Oscillator selected
enable1enable
Oscillation Circuit
OSC1
Feedback for internal oscillator
For external CLK input
enable2
Figure 8. Oscillator Circuitry
LCD Driving Voltage Generator and Internal Regulator
This module generates the LCD voltage needed for display output.
It takes a single supply input and generate necessary bias voltages.
It consists of:
1. 4X and 5X DC-DC Converter
To generate the Vcc voltage. 4X DC-DC converter is used for LCD
panel which needs lower driving voltage for less power consumption. 5X DC-DC converter is used for LCD panel which needs
higher driving voltage.
2. Internal Regulator
Feedback gain control for initial LCD voltage. it can also be used
with external contrast control.
3. Smart Bias Divider
Divide the LCD display voltage (V
lator output. This is a low power consumption circuit which can
save the most display current compare with traditional resistor ladder method.
4. Contrast Control Block
Software control of 16 voltage levels of LCD voltage.
All blocks can be individually turned off if external voltage genera-
tor is employed
5. Bias Ratio Selection circuitry
Software control of 1/7 and 1/9 bias ratio to match the characteristic of LCD panel.
) from the Internal Regu-
LL2-VLL6
Oscillator enable
Buffer
MC141800A
OSC2
6. Self adjust temperature compensation circuitry
Provide 4 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control.
65 Bit Latch / 128 Bit Latch
A register carries the display signal information. First 65 bits are
Common driving signals and other 128 bits are Segment driving signals. Data will be input to the HV-buffer Cell for bumping up to the
required level.
Level Selector
Level Selector is a control of the display synchronization. Display
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell for output signal voltage pump.
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translates the low
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
External component
LCD Panel Driving Waveform
The following is an example of how the Common and Segment
drivers may be connected to a LCD panel. The waveforms shown in
Figure 9a, 9b and 9c illustrate the desired multiplex scheme.
In order to reduce the crosstalk effect, invert the polarities of the
pixel-driving waveforms every 2 or 4 or 8 or 65 lines according to the
selected waveforms. In the power-up state, the default waveform will
be type “B”.
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
SEG1
SEG2
SEG3
SEG0
SEG4
Figure 9a. LCD Display Example “0”
MC141800AMOTOROLA
3–291
COM0
COM1
SEG0
123456789
. . .
65
123456789
TIME SLOT
. . .
65 123456789
. . .
65 123456789
. . .
65
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
SEG1
VLL6
VLL5
VLL4
VLL3
VLL2
VLL1
M
Figure 9b. LCD Driving Signal from MC141800A (Waveform B)
Figure 9c. LCD Driving Signal from MC141800A (Waveform C with polarity inversion every 2 lines)
MC141800AMOTOROLA
3–293
Command Description
Set Display On / Off (Display Mode / Stand-by Mode)
The Display On command turns the LCD Common and Segment out-
puts on. This command starts the conversion of data in GDDRAM to
necessary waveforms on the Common and Segment driving outputs.
The on-chip bias generator is also turned on by this command. (Note:
“Oscillator On” command should be sent before “Display On” is
selected)
The Display Off command turn the display off and the states of the
LCD driver are as follow during display off:
1. All the Common and Segment outputs are fixed at V
2. The bias Internal DC/DC Converter is turned off.
3. The RAM and content of all registers are retained.
4. IC will accept new commands and data.
The Oscillator is not affected by this command.
Set GDDRAM Column Address
This command positions the address pointer on a column location.
The address can be set to location 00H-7FH (128 columns). The column address will be increased automatically after a read or write operation. Refer to “Address Increment Table” and command “Set GDDRAM
Page Address” for further information.
Set GDDRAM Page Address
This command positions the row address to 1 of 9 possible positions
in GDDRAM. Refer to figure 7.
Master Clear GDDRAM
This command is to clear the content of the Display Data RAM to
zero. Issue this command followed by a dummy write command. The
RAM for icon line will not be affected by this command.
Master Clear Icon
This command is a MASTER clear of the Icon Data RAM. After set-
ting the page pointer to icon page (page 9), the internal icon RAM data
will be set to Zero after the command is issued. Before using this command, set the page address to page 9 by the command “Set GDDRAM
Page Address”. A dummy write data is also needed after the “Master
Clear Icon” command to make the clear icon action effective.
Set Page Mask (Display Mask)
The following command will be written to the Page Mask Register.
Page Mask is an 8-bit register. Each bit represents one of the 8 pages:
page mask bit 0 represents Page 1, page mask bit 1 represents Page
2,...etc.
LL1
(VSS).
Set Display Frequency
In half display frequency mode, the display frame frequency will be
halved. Also, the operation frequency of analog circuitries will be halved
for power saving purpose.
Save / Restore Column Address
Save Column Address command saves a copy of the Column
Address of GDDRAM. Restore Column Address command restores the
copy obtained from the previous execution of saving column address.
This instruction is very useful for writing full graphics characters that are
larger than 8 pixels vertically.
Set Column Mapping
This instruction selects the mapping of Display Data RAM to Segment drivers for mechanical flexibility. There are 2 mappings to select:
1. Column 0 - Column 127 of GDDRAM mapped to Seg0-Seg127
respectively;
2. Column 0 - Column 127 of GDDRAM mapped to Seg127-Seg0
respectively.
COM64 will not be affected by this command. Detail information
please refer to section “Display Output Description”.
Set Row Mapping
This instruction selects the mapping of Display Data RAM to Common Drivers for mechanical flexibility. There are 2 selected mappings:
1. Row 0 - Row x of GDDRAM to Common 0 - Common x respectively;
2. Row 0 - Row x of GDDRAM to Common x - Common 0 respectively.
(x+2 is the multiplex ratio)
COM64 will not be affected by this command. See section “Display
Output Description” for related information.
Set MUX Ratio
This command is to select any a ratio from 2 to 65. Row 64 (icon line)
is not affected by this command and it would be turned on for normal
display. This command contain two commands bytes, the first byte
inform the driver that the second byte will be the no. of mux ratio.
e.g. second byte = 0H to turn on Row 0 and 64 (2 MUX)
second byte = 63H to turn on Row 0 to 64 (65 MUX)
The unused common pins output non-scanning signals.
Set Bias Ratio
This command sets the 1/7 bias or 1/9 bias for the divider output.
The selection should match the characteristic of LCD Panel.
Page Mask
When the Page Mask is enabled, the display of those pages, with
page mask bit set, will be cleared. Meanwhile, the data in the display
RAM is retained.
Icon Mask
When the Icon Mask is enabled, the display of the icons will be
cleared. Meanwhile, the data in the icon display RAM is retained.
Set Display Mode
This command switch the driver to full display mode or icon display
mode. In low power icon mode, only icons (driven by COM64) are displayed. Display on row 0 to row 63 will be disabled. The DC-DC converter and the Internal Regulator are off. All VCC, VLLs pins do not
have external bias voltage supply in the lo w pow er icon mode. In normal
display mode, COM0 to COM64 will be turned on.
MC141800A
3–294
Set Oscillator Disable / Enable
This command is used to either turn on / off Oscillator. For using
internal or external oscillator, this command should be executed. The
setting for this command is not affected by command “Set Display On/
Off”. See command “Ext/Int Oscillator” for more information.
Set Internal / External Oscillator
This command is used to select either internal or external oscillator.
When internal oscillator is selected, feedback resistor between OSC1
and OSC2 is needed. For external oscillation circuit, feed clock input
signal to OSC2 and leave OSC1 open.
Set Internal DC/DC Converter Enable
Use this command to select the Internal DC/DC Converter to generate the VCC from AVDD. Disable the Internal DC/DC Converter if external Vcc is provided.
MOTOROLA
Set 4X / 5X DC/DC Converter
This command selects the usage of 4X or 5X Converter when the
Internal DC/DC Converter is enabled.
Set Temperature Coefficient
A temperature gradient selector circuit controlled by two control bits
TC1 and TC2. This command can select 4 different LCD driving voltage
temperature coefficients to match various liquid crystal temperature
grades.
Increase / Decrease Contrast Level
If the internal contrast control is enabled, this command is used to
increase or decrease the contrast level within the 16 contrast levels.
The contrast level starts from lowest value after POR.
Set Contrast Level
This command is to select one of the 16 contrast levels when internal
contrast control circuitry is in use. After power-on reset, the contrast
level is lowest.
Set Internal Regulator On/Off
Choose bit option 0 to disable the on chip Internal Regulator. Choose
bit option 1 to enables Internal Regulator which consists of the internal
contrast control circuits.
Set Smart Bias Divider On/Off
If the Smart Bias Divider is disabled, external bias can be used for
V
LL6
to V
If the Smart Bias Divider is enabled, the internal circuit will
LL2.
generated the 1:7 or 1:9 bias driving voltage.
End of Command
This command is used as extra write end command follows the last
byte of data / command written. This command is not available if serial
mode is selected.
Set Internal Contrast Control Enable
This command is used to adjust the delta voltage of the bias voltages. With bit option = 1, the software selection for delta bias voltage
control is enabled. With bit option = 0, internal contrast control is disabled.
COMMAND TABLE
Bit PatternCommandComment
0000X3X2X1X
0001X3X2X1X
0010000X
0010001X
0010010X
0010100X
0010101X
0010110X
0010111X
0
0
0
0
0
0
0
0
0
Set GDDRAM Page AddressSet GDDRAM Page Address using X3X2X1X0 as address bits.
Set Contrast LevelWith R/W pin input low, set one of the 16 available values to the
internal contrast register, using X3X2X1X0 as data bits.
The contrast register is reset to 0000 during POR.
Set 4X / 5X DC-DC ConverterX0=0: enable 4X Converter (POR)
X0=1: enable 5X Converter
Set Segment MappingX0=0: Col0 to Seg0 (POR)
X0=1: Col0 to Seg127
Set Common MappingX0=0: Row0 to Com0 (POR)
X0=1: Row0 to Com63
Set Display on/offX0=0: display off (POR)
X0=1: display on
Set Internal DC/DC Converter On/OffX0=0: Internal DC/DC Converter Off (POR)
X0=1: Internal DC/DC Converter On
Set Internal Regulator On/OffX0=0: Internal Regulator Off(POR)
X0=1: Internal Regulator On
Set Smart Bias Divider On/OffX0=0: Smart Bias Divider Off (POR)
X0=1: Smart Bias Divider On
When an external bias network is preferred, the Smart Bias
Divider should be disabled.
Set Smart Icon Mode
This command is to set 4-Phase or 6-Phase smart icon modes which
for lower VDD or higher Von of panel. Refer to Smart Icon Mode Output
Description for detail.
Set Display Waveform Type
This command will select the number of lines for the polarity inversion of the driving waveform. Four types of waveform types are available. Refer to Figure 9.
Set Data Direction
This command is used in SPI mode only. It will be two continuous
commands, the first byte control the data direction and inform the LCD
driver the second byte will be number of data bytes will be read / write.
After these two commands sending out, the following messages will be
data.
MC141800AMOTOROLA
3–295
COMMAND TABLE
Bit PatternCommandComment
0011000X
0011001X
0011010X
0
0
0
00110110Master Clear GDDRAMMaster clear GDDRAM (64 x 128 bits), row 64 (icon line) will not
00110111Master Clear IconsMaster Clear of Icons
0011100X
0011101X
0
0
00111100End of CommandWrite command to identify end of data frame
0011111X
0
01000000Set Multiplex Rationext command will define no. of MUX, 00X5X4X3X2X1X
01000001Set Page Masknext command will be written to page mask register
0100010X
0100011X
0100100X
0100101X
0100110X
0
0
0
0
0
01010100Reservednext command will define Smart Divider value, 000X4X3X2X1X
0101001X
011001X1X
0110100X
011011X1X
0111000X
0
0
0
0
0
Set Internal Contrast Control On/OffX0=0: Internal Contrast Control Off(POR)
X0=1: Internal Contrast Control On
Internal contrast circuits can be disabled if external contrast circuits is preferred.
Set Display FrequencyX0=0 : normal display frequency (POR)
X0=1 : half display frequency
Save/Restore GDDRAM Column
Address
X0=0 : restore address
X0=1 : save address
be cleared
Set Bias RatioX0=0 : bias = 1 : 9 (POR)
X0=1 : bias = 1 : 7
ReservedX0=0 : Normal Operation (POR)
X0=1 : Test Mode 1 Select
(Note : Make sure to set X0=0 during application)
Set Display ModeX0=0 : low power icon display mode
X0=1 : normal display mode (POR)
no. of mux=00111111 upon POR (65 MUX)
0
page mask register=0 upon POR
Page MaskX0=0 : disable page mask (POR)
X0=1 : enable page mask
Icon MaskX0=0 : disable icon mask (POR)
X0=1 : enable icon mask
Set Data Direction
(for SPI mode only)
X0=0 : Write Data (POR)
X0=1 : Read Data
next command will define the total number of data bytes will be
read / write
e.g. no. of data bytes = 01111111 for 128 bytes
ReservedX0=0 : Select Switch Resistor as HV divider (POR)
X0=1 : Select Buffer as HV dividier
ReservedX0=0 : Select 500ohm in switch resistor divider (POR)
X0=1 : Select 1kohm in switch resistor divider
ReservedX0=0 : Use diode approach for temperature compensation (POR)
X0=1 : Use band gap technique for temperature compensation
Set Display Waveform TypeX1X0=00 : Waveform Type B (POR)
X1X0=01 : Waveform Type C with polarity inversion every 8 lines
X1X0=10 : Waveform Type C with polarity inversion every 4 lines
X1X0=11 : Waveform Type C with polarity inversion every 2 lines
Set Smart Icon ModeX0=1 : 4-Phase Smart Icon
X0=0 : 6-Phase Smart Icon (POR)
Set Temperature CoefficientX1X0=: 0.00% (POR)
X1X0=: -0.18%
X1X0=: -0.22%
X1X0=: -0.35%
Increase / Decrease Contrast LevelX0=0: Decrease by one level
X0=1: Increase by one level
(Note: increment/decrement wraps round among the 16 contrast
levels. Start at the lowest level when POR.
0
MC141800A
3–296
MOTOROLA
COMMAND TABLE
Bit PatternCommandComment
0111011X
0111101X
0111111X
1X6X5X4X3X2X1X
0
0
0
0
ReservedX0=0: Normal Operation (POR)
X0=1: Test Mode 2 Select
(Note: Make sure to set X0=0 during application)
Set Internal / External OscillatorX0=0: Internal oscillator (POR)
X0=1: External oscillator.
For internal oscillator place a resistor between OSC1 and OSC2.
For external oscillator mode, feed clock input to OSC2.
Set Oscillator On/OffX0=0: oscillator Off (POR)
X0=1: oscillator On.
This is the master control for oscillator circuitry. This command
should be issued after the “Set Internal / External Oscillator” command.
Set GDDRAM Column AddressSet GDDRAM Column Address.
Use X6X5X4X3X2X1X0 as address bits.
Data Read / Write
To read data from the GDDRAM, input High to R/W pin and D/C pin in parallel mode or pull high at the 7th and 8th bit of the address in IIC
serial mode or send Data Direction command 01001001 in SPI mode. Data is valid at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically.
To write data to the GDDRAM, input Low to R/W pin and High to D/C pin in parallel mode or pull low 7th bit and high 8th bit of the address in
IIC serial mode or send Data Direction command 01001000 in SPI mode. Data is latched at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically. If parallel interface is selected, End of command should be followed after all data are
send out.
No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands
Required for R/W Actions on RAM” Table)
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content
whether the target RAM content is being displayed.
MC141800AMOTOROLA
3–297
Display Output Description
This is an example of output pattern on the LCD panel. Figure 10b and 10c are data map of GDDRAM and the output pattern on the LCD
Figure 10c. Examples of LCD display with different command enabled
MOTOROLA
Power Up Sequence (Commands Required)
Command RequiredPOR StatusRemarks
Set Display Frequency
Set Oscillator Enable
Set MUX Ratio
Set Bias Ratio
Set Internal DC/DC Converter
Set Internal Regulator On
Set Temperature Coefficient
Set Internal Contrast Control On
Set Contrast Level
Set Smart Bias Divider On
Set Segment Mapping
Set Common Mapping
Set Display On
Normal
Disable
65 MUX
1/9 bias
4X Converter
Off
TC=0%
Off
Contrast Level = 0
Off
Seg. 0 = Col. 0
Com. 0 = Row 0
Off
*1
*1
*1
*1
*1
*1
*1, *3
*1, *3
*1, *2, *3
*1
Smart Icon Mode Output Description
Remarks:
*1 -- Required only if desired status differ from POR.
*2 -- Effective only if Internal Contrast Control is enabled.
*3 -- Effective only if Internal Regulator is enabled.
There are two driving schemes of Smart Icon Mode for panel with different V
1) 4 - Phase Smart Icon: 1/4 ~ 3/4
V
> VDD * sqrt (1/4)
off
V
< VDD * sqrt (3/4)
on
2) 6 - Phase Smart Icon: 1/6 ~ 3/6
V
> VDD * sqrt (1/6)
off
V
< VDD * sqrt (3/6)
on
COM (non icon)
COM64(icon)
SEG(on)
SEG(off)
Figure 11a. LCD Driving Signal for 4 - Phase Smart Icon Mode
COM (non icon)
COM64(icon)
SEG(on)
SEG(off)
on/Voff
or VDD:
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
Figure 11b. LCD Driving Signal for 6 - Phase Smart Icon Mode
MC141800AMOTOROLA
3–299
Application Circuit:
All Internal Analog Circuitry disabled at IIC Serial mode operation
CMOS
MPU/MCU
SCL
SDA
EPROM
R
RAM
V
DD
V
R
DD
0.1µF
DVSS DVDD
CLK
D0/SDA
RES
D7/IIC/SPI
S/P
DV
DD
R3
AV
DD
V
CC
0.1µF
AVDD
AVSS
VLL2 VLL3
VLL4 VLL5 VLL6VCC
D1/A1
D2/A2
IIC Address
COM0 to
MC141800A
COM64
T o LCD
Panel
SEG0 to
SEG127
OSC1OSC2
VRVFC3P C3N
C2P C2N
C1P C1N
MC141800A
3–300
Remark:
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enable.
4. R/W, CE, D/C and D3-D6 can be open for IIC serial mode.
5. D1/A1 and D2/A2 should be at predefined state for device identification.
t
6. R is pull up resistance, R <
2 * C
r
(R = 300 ohm for 1MHz, assume C
bus
= 200pF)
bus
MOTOROLA
All Internal Analog Circuitry enabled at IIC Serial mode operation
CMOS
MPU/MCU
SCL
SDA
EPROM
DD
AV
DD
0.1µF
DV
0.1µF
0.1µF
V
DVSS DVDD
DD
R
R
AVDD
AVSS
CLK
D0/SDA
RES
V
DD
D7/IIC/SPI
S/
P
R3
VCC
MC141800A
VLL2
VRVFC3P C3NOSC1OSC2
VLL3
0.1µF
VLL4
VLL5
C2P C2N
0.1µF
VLL6
D1/A1
D2/A2
COM0 to
COM64
SEG0 to
SEG127
C1P C1N
0.1µF
IIC Address
T o LCD
Panel
RAM
Remark:
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3. RES should be at a known state.
4. R/W, CE, D/C and D3-D6 can be open for IIC serial mode.
5. D1/A1 and D2/A2 should be at predefined state for device identification.
t
6. R is pull up resistance, R <
2 * C
r
(R = 300 ohm for 1MHz, assume C
bus
bus
= 200pF)
MC141800AMOTOROLA
3–301
All Internal Analog Circuitry disabled at SPI Serial mode operation
CMOS
MPU/MCU
SCK
MOSI
MISO
EPROM
RAM
RES
CE
CLK
D3/Din
D4/Dout
D7/IIC/SPI
V
DD
0.1µF
DVSS DVDD
S/P
DV
DD
R3
AV
DD
0.1µF
AVDD
AVSS
OSC1OSC2
VLL2 VLL3
MC141800A
VRVFC3P C3N
VLL4 VLL5 VLL6VCC
C2P C2N
C1P C1N
V
COM0 to
COM64
SEG0 to
SEG127
CC
T o LCD
Panel
MC141800A
3–302
Remark:
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enable.
4. R/W, D/C, D0-2 and D5-6 can be open for SPI serial mode.
MOTOROLA
All Internal Analog Circuitry enabled at SPI Serial mode operation
CMOS
MPU/MCU
SCK
MOSI
MISO
EPROM
RAM
RES
CE
CLK
D3/Din
D4/Dout
D7/IIC/SPI
V
DD
0.1µF
DVSS DVDD
S/P
DV
DD
R3
AV
DD
0.1µF
0.1µF
AVDD
AVSS
VCC
VLL2
VLL3
VLL4
VLL5
VLL6
COM0 to
MC141800A
COM64
T o LCD
Panel
SEG0 to
SEG127
OSC1OSC2
VRVFC3P C3N
0.1µF
C2P C2N
0.1µF
C1P C1N
0.1µF
Remark:
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3
. RES should be at a known state.
4. R/W, D/C, D0-2 and D5-6 can be open for SPI serial mode.
MC141800AMOTOROLA
3–303
All Internal Analog Circuitry disabled at Parallel mode operation
CMOS
MPU/MCU
with
Parallel
Interface
EPROM
RAM
DVSS DVDD
RES
CE
D/C
R/W
CLK
D0 .. D7
S/P
0.1µF
DV
DD
R3
AV
DD
0.1µF
AVDD
AVSS
OSC1OSC2
VLL2 VLL3
MC141800A
VRVFC3P C3N
VLL4 VLL5 VLL6VCC
C2P C2N
C1P C1N
V
COM0 to
COM64
SEG0 to
SEG127
CC
T o LCD
Panel
MC141800A
3–304
Remark:
1. R3 can be omitted for external oscillator.
2. RES should be at a known state.
3. VLL2 - VLL6 can be left open for internal divider is enable.
MOTOROLA
All Internal Analog Circuitry enabled at Parallel mode operation
CMOS
MPU/MCU
with
Parallel
Interface
EPROM
RAM
DVSS DVDD
RES
CE
D/C
R/W
CLK
D0 .. D7
S/P
0.1µF
DV
DD
R3
AV
DD
0.1µF
0.1µF
AVDD
OSC1OSC2
AVSS
VCC
VLL2
MC141800A
VRVFC3P C3N
0.1µF
VLL3
VLL4
C2P C2N
0.1µF
VLL5
C1P C1N
0.1µF
VLL6
COM0 to
COM64
SEG0 to
SEG127
T o LCD
Panel
Remark:
1. R3 can be omitted for external oscillator.
2. VR and VF can be left open for Internal Regulator disable and Contrast Disable.
3
. RES should be at a known state.
MC141800AMOTOROLA
3–305
PACKAGE DIMENSIONS
MC141800AT
TAB PACKAGE DIMENSION - 1
(DO NOT SCALE THIS DRAWING)
MC141800A
3–306
Reference: 98ASL00269AIssue “0” released on 11 Feb 97
MOTOROLA
PACKAGE DIMENSIONS
MC141800AT
TAB PACKAGE DIMENSION - 2
(DO NOT SCALE THIS DRAWING)
Reference: 98ASL00269AIssue “0” released on 11 Feb 97
Note :*Power and ground die pads should be bonded correspondingly in COG application
Die Pad 15 - 33, 43, 45, 47 -54, 64, 66, 68, 70, 72 - 73, 76, 78 and 82 - 87 are multiple pads of critical signal
(Basically, these are D0, CLK, DVDD, DVSS, AVDD, AVSS, VCC and VLL2-VLL6 which special design for COG)