Motorola MC14599BCL, MC14599BCP, MC14099BCL, MC14099BCP, MC14099BDW Datasheet

MOTOROLA CMOS LOGIC DATAMC14099B MC14599B

246

  

The MC14099B and MC14599B are 8–bit addressable latches. Data is entered in serial form when the appropriate latch is addressed (via address pins A0, A1, A2) and write disable is in the low state. Chip enable must be high for w riting into MC14599B. F or the MC14599B the data pin is a bidirectional data port and for the MC14099B the input is a unidirectional write only port. The Write/Read

line controls this port in the MC14599B.

The d ata is p resented in p arallel a t the output of t he eight latches independently of the state of Write Disable, Write/Read

or Chip Enable.

A Master Reset capability is available on both parts.

• Serial Data Input

• Parallel Output

• Master Reset

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range

• MC14099B pin for pin compatible with CD4099B

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 18.0

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

Iin, I

out

Input or Output Current (DC or Transient), per Pin

± 10

Power Dissipation, per Package†

500

stg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14099B MC14599B

125

WRITE

DISABLE

DATA

RESET

DATA

RESET

WRITE

DISABLE

WRITE/ READ

PIN ASSIGNMENT

CHIP ENABLE

WRITE/READ

WRITE DISABLE

DATA

A0 A1 A2

RESET

4 3

5 6 7

DECODER

11 12 13 14 15 16 17 1

LATCHES

DECODER

5 6 7

WRITE DISABLE

DATA

A0 A1 A2

RESET

4 3

VDD = 18

VSS = 9

VDD = 16

VSS = 8

9 10 11 12 13 14 15



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 0 1/94



  

 

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14099BCP Plastic MC14099BCL Ceramic MC14099BDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

L SUFFIX

CERAMIC CASE 726

ORDERING INFORMATION

MC14599BCP Plastic MC14599BCL Ceramic

P SUFFIX

PLASTIC

CASE 707

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained

to the range VSS v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

TA = – 55° to 125°C for all packages.

MOTOROLA CMOS LOGIC DATA

247

MC14099B MC14599B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2

– 0.88

– 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

—

5.0

7.5

—

ÎÎÎ

—

Input Capacitance

MC14599B — Data (pin 3) (Vin = 0)

—

22.5

—

ÎÎÎ

—

Quiescent Current

(Per Package)

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

5.0 10 15

IT = (1.5 µA/kHz) f + I

IT = (3.0 µA/kHz) f + I

IT = (4.5 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MOTOROLA CMOS LOGIC DATAMC14099B MC14599B

248

SWITCHING CHARACTERISTICS* (C

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

Symbol

Vdc

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

TLH

, t

THL

= (1.35 ns/pF) CL + 32 ns

TLH

, t

THL

= (0.6 ns/pF) CL + 20 ns

TLH

, t

THL

= (0.4 ns/pF) CL + 20 ns

ÎÎÎÎ

TLH

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

Propagation Delay Time

Data to Output Q

ÎÎÎÎ

PHL

PLH

5.0 10 15

ÎÎÎÎ

— — —

200

75 50

400 150 100

Write Disable to Output Q

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

200

80 60

400 160 120

Reset to Output Q

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

175

80 65

350 160 130

CE to Output Q (MC14599B only)

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

225 100

450 200 150

Propagation Delay Time, MC14599B only

Chip Enable, Write/Read

to Data

ÎÎÎÎ

PHL

PLH

5.0 10 15

ÎÎÎÎ

— — —

200

80 65

400 160 130

Address to Data

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

200

90 75

400 180 150

Pulse Widths

Reset

ÎÎÎÎ

w(H)

w(L)

5.0 10 15

ÎÎÎÎ

150

75 50

75 40 25

— — —

Write Disable

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

320 160 120

160

80 60

— — —

Set Up Time

Data to Write Disable

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

100

50 35

50 25 20

— — —

Hold Time

Write Disable to Data

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

150

75 50

75 40 25

— — —

Set Up Time

Address to Write Disable

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

100

80 40

45 30 10

— — —

Removal Time

Write Disable to Address

ÎÎÎÎ

rem

5.0 10 15

ÎÎÎÎ

0 0 0

– 80 – 40 – 40

— — —

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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