Motorola MC14077BD, MC14077BCL, MC14070BCL, MC14070BCP, MC14070BD Datasheet
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MOTOROLA CMOS LOGIC DATA
1
MC14070B MC14077B
Quad Exclusive “OR” and “NOR” Gates
The M C14070B q uad exclusive OR gate and the MC14077B q uad
exclusive NOR gate are constructed with MOS P–channel and N–channel
enhancement m ode devices i n a single monolithic structure. T hese
complementary M OS logic gates find p rimary use w here low power
dissipation and/or high noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• MC14070B — Replacement for CD4030B and CD4070B Types
• MC14077B — Replacement for CD4077B Type
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Figure 1. Power Dissipation Test Circuit and Waveform
V
DD
V
in
C
L
*
I
DD
20 ns 20 ns
V
DD
V
SS
90%
50%
10%
V
in
1/f
50% DUTY CYCLE
*Inverted output on MC14077B only.
Figure 2. Switching Time Test Circuit and Waveforms
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
OUT
C
OUT
D
IN 1
D
IN 2
D
V
DD
IN 1
C
IN 2
C
OUT
B
OUT
A
IN 2
A
IN 1
A
V
SS
IN 2
B
IN 1
B
V
DD
C
L
20 ns
V
SS
V
SS
90%
OUTPUT
#
*
20 ns
V
OH
V
OL
V
DD
t
THL
t
TLH
50%
10%
90%
50%
10%
t
PLH
t
PHL
INPUT
*Inverted output on MC14077B only.
PULSE
GENERATOR
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
MC14070B
QUAD Exclusive OR
Gate
MC14077B
QUAD Exclusive NOR
Gate
13
11
12
9
8
6
5
2
1
10
4
3
13
12
9
8
6
5
2
1
11
10
4
3
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
MOTOROLA CMOS LOGIC DATAMC14070B MC14077B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (0.3 µA/kHz) f + I
DD
IT = (0.6 µA/kHz) f + I
DD
IT = (0.9 µA/kHz) f + I
DD
µAdc
Output Rise and Fall Times**
(CL = 50 pF)
t
TLH
, t
THL
= (1.35 ns/pF) CL + 33 ns
t
TLH
, t
THL
= (0.60 ns/pF) CL + 20 ns
t
TLH
, t
THL
= (0.40 ns/pF) CL + 20 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
—
—
—
—
—
—
100
50
40
200
100
80
—
—
—
—
—
—
ns
Propagation Delay Times**
(CL = 50 pF)
t
PLH
, t
PHL
= (0.90 ns/pF) CL + 130ns
t
PLH
, t
PHL
= (0.36 ns/pF) CL + 57 ns
t
PLH
, t
PHL
= (0.26 ns/pF) CL + 37 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
—
—
—
—
—
—
175
75
55
350
150
110
—
—
—
—
—
—
ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
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