MOTOROLA MC14069UBFEL, MC14069UBFL1, MC14069UBFL2, MC14069UBFR1, MC14069UBD Datasheet

...

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14069UB/D

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

• Triple Diode Protection on All Inputs

• Pin–for–Pin Replacement for CD4069UB

• Meets JEDEC UB Specifications

MAXIMUM RATINGS (Voltages Referenced to V

) (Note 2.)

Symbol

Parameter Value Unit

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

Power Dissipation,

per Package (Note 3.)

500 mW

Ambient Temperature Range –55 to +125 °C

stg

Storage Temperature Range –65 to +150 °C

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained

to the range V

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

http://onsemi.com

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14069UBCP PDIP–14 2000/Box MC14069UBD SOIC–14

2750/Box MC14069UBDR2 SOIC–14 2500/Tape & Reel MC14069UBDT TSSOP–14

MC14069UBF SOEIAJ–14

96/Rail

See Note 1.

MARKING

DIAGRAMS

PDIP–14

P SUFFIX

CASE 646

MC14069UBCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

TSSOP–14 DT SUFFIX

CASE 948G

14069U

AWLYWW

069U

ALYW

SOEIAJ–14

F SUFFIX

CASE 965

MC14069U

AWLYWW

MC14069UBFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local ON Semiconductor representative.

MC14069UBDTR2 TSSOP–14 2500/Tape & Reel

MC14069UBDTEL TSSOP–14 2000/Tape & Reel

MC14069UB

http://onsemi.com

PIN ASSIGNMENT

105

OUT 5

IN 5

OUT 6

IN 6

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

OUT 3

IN 3

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

LOGIC DIAGRAM

= PIN 14

= PIN 7

OUTPUTINPUT*

*Double diode protection on all

inputs not shown.

Figure 1. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VSS7

INPUT

OUTPUT

20 ns 20 ns

THL

TLH

OUTPUT

INPUT

PHL

PLH

90% 50% 10%

MC14069UB

http://onsemi.com

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

Symbo

– 55_C

25_C

125_C

Characteristic

Symbo

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ООООООООО

Output Voltage “0” Level

= V

5.0 10 15

— — —

0.05

ÎÎ

— — —

0 0 0

ÎÎ

0.05

— — —

0.05

Vdc

ООООООООО

Vin = 0 “1” Level

5.0 10 15

4.95

9.95

14.95

— — —

ÎÎ

4.95

9.95

14.95

5.0 10 15

ÎÎ

— — —

4.95

9.95

14.95

— — —

Vdc

ООООООООО

Input Voltage “0” Level

= 4.5 Vdc)

= 9.0 Vdc)

= 13.5 Vdc)

5.0 10 15

— — —

1.0

2.0

2.5

ÎÎ

— — —

2.25

4.50

6.75

ÎÎ

1.0

2.0

2.5

— — —

1.0

2.0

2.5

Vdc

ООООООООО

“1” Level

= 0.5 Vdc)

= 1.0 Vdc)

= 1.5 Vdc)

5.0 10 15

4.0

8.0

12.5

— — —

ÎÎ

4.0

8.0

12.5

2.75

5.50

8.25

ÎÎ

— — —

4.0

8.0

12.5

— — —

Vdc

ООООООООО

Output Drive Current

= 2.5 Vdc) Source

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

ÎÎ

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

ÎÎ

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

ООООООООО

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

5.0 10 15

0.64

1.6

4.2

— — —

ÎÎ

0.51

1.3

3.4

0.88

2.25

8.8

ÎÎ

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ООООООООО

Input Capacitance

= 0)

—

ÎÎ

—

5.0

ÎÎ

7.5

—

ООООООООО

Quiescent Current

(Per Package)

5.0 10 15

— — —

0.25

0.5

1.0

ÎÎ

— — —

0.0005

0.0010

0.0015

ÎÎ

0.25

0.5

1.0

— — —

7.5 15 30

µAdc

ООООООООО

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent, Per Gate) (C

= 50 pF)

5.0 10 15

ООООООООООООООО

IT = (0.3 µA/kHz) f + IDD/6 I

= (0.6 µA/kHz) f + IDD/6

= (0.9 µA/kHz) f + IDD/6

µAdc

ООООООООО

Output Rise and Fall Times

(5.)

(CL = 50 pF)

TLH

, t

THL

= (1.35 ns/pF) C

+ 33 ns

TLH

, t

THL

= (0.60 ns/pF) C

+ 20 ns

TLH

, t

THL

= (0.40 ns/pF) C

+ 20 ns

TLH

THL

5.0 10 15

— — —

ÎÎ

— — —

100

50 40

ÎÎ

200 100

— — —

ООООООООО

Propagation Delay Times

(5.)

(CL = 50 pF)

PLH

, t

PHL

= (0.90 ns/pF) CL + 20 ns

PLH

, t

PHL

= (0.36 ns/pF) CL + 22 ns

PLH

, t

PHL

= (0.26 ns/pF) CL + 17 ns

PLH

PHL

5.0 10 15

— — —

ÎÎ

— — —

65 40 30

ÎÎ

125

75 55

— — —

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

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