MOTOROLA MC14042BDR2, MC14042BCP, MC14042BD, MC14042BF, MC14042BFEL Datasheet

MC14042B

Quad Transparent Latch

The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q

during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.

• Buffered Data Inputs

• Common Clock

• Clock Polarity Control

• Q and Q Outputs

• Double Diode Input Protection

• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

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PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

MARKING

DIAGRAMS

MC14042BCP

AWLYYWW

14042B

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

Vin, V

Iin, I

stg

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

Ambient Temperature Range –55 to +125 °C

Storage Temperature Range –65 to +150 °C Lead Temperature

or VDD). Unused outputs must be left open.

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

should be constrained

out

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14042B

AWLYWW

ORDERING INFORMATION

Device Package Shipping

MC14042BCP PDIP–16 2000/Box MC14042BD SOIC–16 2400/Box MC14042BDR2 SOIC–16 2500/Tape & Reel MC14042BF SOEIAJ–16 See Note 1. MC14042BFEL SOEIAJ–16 See Note 1. MC14042BFR1 SOEIAJ–16 See Note 1. MC14042BFR2 SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14042B/D

MC14042B

PIN ASSIGNMENT

Q3 Q0 Q0 D0

CLOCK

POLARITY

1 2 3 4

6 7 8

16 15 14 13 125 11 10

TRUTH TABLE

Clock Polarity Q

0 0 Data 1 0 Latch 1 1 Data 0 1 Latch

LOGIC DIAGRAM

Q D3 D2

2 Q2 Q1 Q1

CLOCK

POLARITY

= PIN 16

= PIN 8

LATCH

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MC14042B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

Output Voltage “0” Level

= VDD or 0

ОООООООО

“1” Level

= 0 or V

ОООООООО

Input Voltage “0” Level

ОООООООО

Output Drive Current

ОООООООО

= 4.5 or 0.5 Vdc) = 9.0 or 1.0 Vdc) = 13.5 or 1.5 Vdc)

“1” Level = 0.5 or 4.5 Vdc) = 1.0 or 9.0 Vdc) = 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source = 4.6 Vdc) = 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

ОООООООО

= 1.5 Vdc)

Input Current Input Capacitance

ОООООООО

= 0)

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

= 50 pF on all outputs all

ОООООООО

buffers switching)

(5.) (6.)

Symbol

ÎÎ

Vdc

5.0 10

5.0

5.0 10

15 15

—

5.0 10

5.0

10 15

Min

— —

—

4.95

9.95

14.95

— —

—

3.5

7.0

– 3.0

– 0.64

– 1.6

– 4.2

0.64

1.6

4.2 — —

— —

—

ООООООООООООООО

– 55_C

)

Max

0.05

1.5

3.0

4.0

± 0.1

1.0

2.0

4.0

25_C

Min

— —

ÎÎ

—

— — —

4.95

9.95

ÎÎ

14.95

ÎÎ

— —

ÎÎ

—

ÎÎ

— — —

— — — —

— — —

3.5

7.0

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4 —

—

ÎÎ

— —

ÎÎ

— IT = (1.0 µA/kHz) f + I

IT = (2.0 µA/kHz) f + I IT = (3.0 µA/kHz) f + I

(4.)

Typ

0 0

5.0 10

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

0.88

2.25

8.8

±0.00001

5.0

0.002

0.004

0.006

Max

0.05

ÎÎ

0.05 —

—

ÎÎ

—

ÎÎ

1.5

3.0

ÎÎ

4.0

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

—

ÎÎ

—

± 0.1

7.5

ÎÎ

1.0

2.0

ÎÎ

4.0

DD DD DD

Min

— —

—

4.95

9.95

14.95

— —

—

3.5

7.0

– 1.7

– 0.36

– 0.9

– 2.4

0.36

0.9

2.4 — —

— —

—

125_C

Max

0.05

± 1.0

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

30 60

120

Unit

Vdc

mAdc

µAdc

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