MOTOROLA MC14029BD, MC14029BDR2, MC14029BF, MC14029BFEL, MC14029BCP Datasheet

MC14029B

Binary/Decade Up/Down Counter

The MC14029B Binary/Decade up/down counter is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide toggle flip–flop capability. The counter can be used in either Binary or BCD operation. This complementary MOS counter finds primary use in up/down and difference counting and frequency synthesizer applications where low power dissipation and/or high noise immunity is desired. It is also useful in A/D and D/A conversion and for magnitude and sign generation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going

Edge of Clock

• Asynchronous Preset Enable Operation

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

• Pin for Pin Replacement for CD4029B

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

Vin, V

Iin, I

stg

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation,

per Package (Note 3.) Ambient Temperature Range –55 to +125 °C Storage Temperature Range –65 to +150 °C Lead Temperature

(8–Second Soldering)

v (Vin or V

or VDD). Unused outputs must be left open.

) v VDD.

out

) (Note 2.)

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

should be constrained

out

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MARKING

DIAGRAMS

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

MC14029BCP

AWLYYWW

14029B

AWLYWW

MC14029B

AWLYWW

ORDERING INFORMATION

Device Package Shipping

MC14029BCP PDIP–16 2000/Box MC14029BD SOIC–16 2400/Box MC14029BDR2 SOIC–16 2500/Tape & Reel MC14029BF SOEIAJ–16 See Note 1. MC14029BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14029B/D

MC14029B

PIN ASSIGNMENT

TRUTH TABLE

Preset

Carry In Up/Down

Enable

Action

1 X 0 No Count 0 1 0 Count Up 0 0 0 Count Down X X 1 Preset

X = Don’t Care

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

– 55_C

Min

— —

—

4.95

9.95

14.95

—

— —

3.5

7.0 11

– 3.0

– 0.64

– 1.6

– 4.2

0.64

1.6

4.2

— —

—

— —

ООООООООООООООО

Characteristic

Output Voltage “0” Level

= VDD or 0

ОООООООО

= 0 or V

ОООООООО

“1” Level

Input Voltage “0” Level

= 4.5 or 0.5 Vdc)

ОООООООО

= 9.0 or 1.0 Vdc)

= 13.5 or 1.5 Vdc)

ОООООООО

“1” Level

= 0.5 or 4.5 Vdc)

ОООООООО

= 1.0 or 9.0 Vdc)

= 1.5 or 13.5 Vdc)

ОООООООО

Output Drive Current

= 2.5 Vdc) Source

ОООООООО

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

Input Current Input Capacitance

= 0)

Quiescent Current

ОООООООО

(Per Package)

ОООООООО

Total Supply Current

(Dynamic plus Quiescent,

ОООООООО

Per Package)

= 50 pF on all outputs, all

ОООООООО

buffers switching)

(5.) (6.)

Symbol

ÎÎ

V Vdc

5.0 10

5.0

10 15

5.0

10 15

5.0

10 15

5.0

5.0 10

5.0

10 15

15 —

5.0

10 15

5.0 10

)

Max

0.05

1.5

3.0

4.0

± 0.1

5.0

— — —

— — — —

— — —

—

10 20

25_C

Min

— —

ÎÎ

—

4.95

ÎÎ

9.95

14.95

ÎÎ

—

ÎÎ

— —

ÎÎ

3.5

ÎÎ

7.0 11

ÎÎ

– 2.4

ÎÎ

– 0.51

– 1.3

ÎÎ

– 3.4

0.51

ÎÎ

1.3

3.4

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

(4.)

Typ

0 0

5.0

10 15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88 – 2.25

– 8.8

0.88

2.25

8.8

±0.00001

5.0

0.005

0.010

0.015

IT = (0.58 µA/kHz) f + I IT = (1.20 µA/kHz) f + I IT = (1.70 µA/kHz) f + I

PE Q3

P3 P0

out

ÎÎ

1 2 3 4

6 7 8

Max

0.05

0.05 —

— —

1.5

3.0

4.0

— — —

— — — —

— — —

± 0.1

7.5

5.0 10 20

DD DD DD

16 15 14 13 125 11 10

Min

— —

—

4.95

9.95

14.95

—

— —

3.5

7.0 11

– 1.7

– 0.36

– 0.9

– 2.4

0.36

0.9

2.4

— —

—

— —

CLK Q2 P2

P1 Q1 U/D B/D

125_C

Max

0.05

± 1.0

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

150 300 600

Unit

Vdc

mAdc

µAdc

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MC14029B

SWITCHING CHARACTERISTICS

(7.)

= 50 pF, T

= 25_C)

All Types

Characteristic

Output Rise and Fall Time

, t

TLH

ООООООООООООО

TLH

ООООООООООООО

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time

Clk to Q

ООООООООООООО

Clock Pulse Width

ООООООООООООО

PLH

Clk to C

PLH

Cin to C

PLH

PE to Q

PLH

PE to C

PLH

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1.7 ns/pF) CL + 95 ns

PHL

, t

= (0.66 ns/pF) CL + 47 ns

PHL

, t

= (0.5 ns/pF) CL + 35 ns

PHL

, t

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

out

, t

= (1. 7 ns/pF) CL + 465 ns

PHL

, t

= (0.66 ns/pF) CL + 192 ns

PHL

, t

= (0.5 ns/pF) CL + 125 ns

PHL

Clock Pulse Frequency

ООООООООООООО

Preset Removal Time The Preset Signal must be low prior to a positive–going

ООООООООООООО

transition of the clock. Clock Rise and Fall Time

ООООООООООООО

Carry In Setup Time

ООООООООООООО

Up/Down Setup Time

ООООООООООООО

Binary/Decade Setup Time

ООООООООООООО

Preset Enable Pulse Width

ООООООООООООО

Symbol

TLH

THL

ÎÎÎ

PLH

PHL

ÎÎÎ

PLH

ÎÎÎ

PHL

ÎÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

5.0 10

ÎÎ

PLH

ÎÎÎ

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

PLH

ÎÎÎ

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

PLH

ÎÎÎ

PHL

ÎÎÎ

ÎÎ

5.0 10

ÎÎ

W(cl)

ÎÎÎ

rem

ÎÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

5.0 10

ÎÎ

r(cl)

ÎÎÎ

f(cl)

ÎÎÎ

5.0

ÎÎ

1 5

ÎÎ

5.0 10

ÎÎ

5.0

ÎÎÎÎÎÎ

ÎÎÎ

10 15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎÎ

ÎÎ

Min

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

180

ÎÎ

80 60

ÎÎ

— —

ÎÎ

—

160

ÎÎ

60 —

ÎÎ

— —

ÎÎ

150

ÎÎ

340 140

ÎÎ

100 320

ÎÎ

140 100

ÎÎ

130

ÎÎ

(8.)

Typ

100

ÎÎ

50 40

ÎÎ

200 100

ÎÎ

250 130

ÎÎ

175

ÎÎ

235 100

ÎÎ

320 145

ÎÎ

105

ÎÎ

40 30

ÎÎ

4.0

8.0

ÎÎ

10 80

ÎÎ

30 —

ÎÎ

— —

ÎÎ

75 30

ÎÎ

170

ÎÎ

160

ÎÎ

70 50

ÎÎ

65 35

ÎÎ

Max

200

ÎÎ

100

ÎÎ

400 200

ÎÎ

180

ÎÎ

500 260

ÎÎ

190

ÎÎ

360 120

ÎÎ

100

ÎÎ

470 200

ÎÎ

160

ÎÎ

640 290

ÎÎ

210

—

ÎÎ

— —

ÎÎ

2.0

4.0

ÎÎ

5.0 —

—

ÎÎ

— 15

ÎÎ

5 4

ÎÎ

— —

ÎÎ

— —

—

ÎÎ

— —

ÎÎ

— —

ÎÎ

— —

ÎÎ

—

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

MHz

µs

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