Motorola MC14024BCL, MC14024BCP, MC14024BD Datasheet

MOTOROLA CMOS LOGIC DATAMC14024B

100

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The MC14024B is a 7–stage ripple counter with short propagation delays and high m aximum c lock rates. T he Reset input has standard n oise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered.

• Diode Protection on All Inputs

• Output Transitions Occur on the Falling Edge of the Clock Pulse

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4024B

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 18.0

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

lin, l

out

Input or Output Current (DC or Transient), per Pin

± 10

Power Dissipation, per Package†

500

stg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

LOGIC DIAGRAM

CLOCK

RESET

Q3 = PIN 9 Q4 = PIN 6 Q5 = PIN 5

C Q

R Q

C Q

R Q

C Q

R Q

C Q

R Q



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94

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L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

105

RESET

CLOCK

PIN ASSIGNMENT

VDD = PIN 14

VSS = PIN 7

NC = NO CONNECTION

MOTOROLA CMOS LOGIC DATA

101

MC14024B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

Vin = 0 or V

“1” Level

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

Input Voltage

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

(VO = 0.5 or 4.5 Vdc)

“1” Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

—

5.0

7.5

—

ÎÎÎ

—

Quiescent Current

(Per Package)

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

5.0 10 15

IT = (0.31 µA/kHz) f + I

IT = (0.60 µA/kHz) f + I

IT = (1.89 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATAMC14024B

102

SWITCHING CHARACTERISTICS* (C

= 50 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ

TLH

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

Propagation Delay Time

Clock to Q1

PLH

, t

PHL

= (1.7 ns/pF) CL + 295 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 117 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 85 ns

Clock to Q7

PLH

, t

PHL

= (1.7 ns/pF) CL + 915 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 367 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 275 ns

Reset to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 415 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 217 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 155 ns

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

380 150

110

1000

400 300

500 250 180

600 230 175

2000

750 565

800 400 300

Clock Pulse Width

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

500 165 125

200

60 40

— — —

Reset Pulse Width

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

600 350 260

375 200 150

— — —

Reset Removal Time

ÎÎÎÎ

rem

5.0 10 15

ÎÎÎÎ

625 190 145

250

75 50

— — —

Clock Input Rise and Fall Time

ÎÎÎÎ

TLH

, t

THL

5.0 10 15

ÎÎÎÎ

— — —

1.0

8.0

200

s ms µs

Input Pulse Frequency

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

2.5

8.0 12

1.0

3.0

4.0

MHz

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

TRUTH TABLE

Clock Reset State

0 0 No Change 0 1 All Outputs Low 1 0 No Change 1 1 All Outputs Low

0 No Change 1 All Outputs Low 0 Advance One Count 1 All Outputs Low

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