MOTOROLA MC14020BFEL, MC14020BFL1, MC14020BFL2, MC14020BFR1, MC14020BD Datasheet

...

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14020B/D

MC14020B

14-Bit Binary Counter

The MC14020B 14–stage binary counter is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 14 stages of ripple–carry binary counter. The device advances the count on the negative–going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency–dividing circuits.

• Fully Static Operation

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Buffered Outputs Available from stages 1 and 4 thru 14

• Common Reset Line

• Pin–for–Pin Replacement for CD4020B

MAXIMUM RATINGS (Voltages Referenced to V

) (Note NO TAG)

Symbol

Parameter Value Unit

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

Power Dissipation,

per Package (Note NO TAG)

500 mW

Ambient Temperature Range –55 to +125 °C

stg

Storage Temperature Range –65 to +150 °C

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

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A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14020BCP PDIP–16 2000/Box MC14020BD SOIC–16 48/Rail MC14020BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

MARKING

DIAGRAMS

PDIP–16

P SUFFIX

CASE 648

MC14020BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

14020B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

MC14020B

AWLYWW

TSSOP–16 DT SUFFIX

CASE 948F

020B

ALYW

MC14020BDT TSSOP–16 96/Rail MC14020BF SOEIAJ–16 See Note 1. MC14020BFEL SOEIAJ–16 See Note 1.

MC14020B

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TRUTH TABLE

Clock Reset Output State

0 No Change 0 Advance to Next State

X 1 All Outputs are Low

X = Don’t Care

LOGIC DIAGRAM

CLOCK

RESET

Q1 Q4 Q5 Q12 Q13 Q14

975 123

CCQ

Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 13

Q9 = PIN 12 Q10 = PIN 14 Q11 = PIN 15

= PIN 16

= PIN 8

PIN ASSIGNMENT

125

Q10

Q11

Q14

Q13

Q12

MC14020B

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Output Voltage “0” Level

= VDD or 0

ÎÎ

5.0 10 15

— — —

0.05

ÎÎ

— — —

0 0 0

ÎÎ

0.05

— — —

0.05

Vdc

ОООООООО

“1” Level

= 0 or V

ÎÎ

5.0 10 15

4.95

9.95

14.95

— — —

ÎÎ

4.95

9.95

14.95

5.0 10 15

ÎÎ

— — —

4.95

9.95

14.95

— — —

Vdc

ОООООООО

Input Voltage “0” Level

= 4.5 or 0.5 Vdc)

= 9.0 or 1.0 Vdc)

= 13.5 or 1.5 Vdc)

ÎÎ

5.0 10 15

— — —

1.5

3.0

4.0

ÎÎ

— — —

2.25

4.50

6.75

ÎÎ

1.5

3.0

4.0

— — —

1.5

3.0

4.0

Vdc

ОООООООО

“1” Level

= 0.5 or 4.5 Vdc)

= 1.0 or 9.0 Vdc)

= 1.5 or 13.5 Vdc)

ÎÎ

5.0 10 15

3.5

7.0 11

— — —

ÎÎ

3.5

7.0 11

2.75

5.50

8.25

ÎÎ

— — —

3.5

7.0 11

— — —

Vdc

ОООООООО

Output Drive Current

= 2.5 Vdc) Source

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

ÎÎ

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

ÎÎ

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

ÎÎ

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

ОООООООО

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

ÎÎ

5.0 10 15

0.64

1.6

4.2

— — —

ÎÎ

0.51

1.3

3.4

0.88

2.25

8.8

ÎÎ

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ОООООООО

Input Capacitance

= 0)

ÎÎ

—

ÎÎ

—

5.0

ÎÎ

7.5

—

ОООООООО

Quiescent Current

(Per Package)

ÎÎ

5.0 10 15

— — —

5.0 10 20

ÎÎ

— — —

0.005

0.010

0.015

ÎÎ

5.0 10 20

— — —

150 300 600

µAdc

ОООООООО

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent, Per Package) (C

= 50 pF on all outputs, all

buffers switching)

ÎÎ

5.0 10 15

ООООООООООООООО

IT = (0.42 µA/kHz)f + I

IT = (0.85 µA/kHz)f + I

IT = (1.43 µA/kHz)f + I

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

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