The MC13158 is a wideband IF subsystem that is designed for high
performance data and analog applications. Excellent high frequency
performance is achieved, with low cost, through the use of Motorola’s
MOSAIC 1.5 RF bipolar process. The MC13158 has an on–board
grounded collector VCO transistor that may be used with a fundamental or
overtone crystal in single channel operation or with a PLL in multi–channel
operation. The mixer is useful to 500 MHz and may be used in a balanced
differential or single ended configuration. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is derived by
summing the output of both IF sections. A precision data shaper has an Off
function to shut the output off to save current. An enable control is provided
to power down the IC for power management in battery operated
applications.
Applications include DECT , wideband wireless data links for personal and
portable laptop computers and other battery operated radio systems which
utilize GFSK, FSK or FM modulation.
• Designed for DECT Applications
• 1.8 to 6.0 Vdc Operating Voltage
• Low Power Consumption in Active and Standby Mode
• Greater than 600 kHz Detector Bandwidth
• Data Slicer with Special Off Function
• Enable Function for Power Down of Battery Operated Systems
• RSSI Dynamic Range of 80 dB Minimum
• Low External Component Count
WIDEBAND FM IF
SUBSYSTEM FOR DECT
AND DIGITAL APPLICATIONS
SEMICONDUCTOR
TECHNICAL DATA
32
1
FTB SUFFIX
PLASTIC PACKAGE
CASE 873
(Thin QFP)
ORDERING INFORMATION
Operating
Device
MC13158FTBTA = – 40 to +85°CTQFP–32
Temperature Range
Package
Mix Out
V
CC1
IF In
IF Dec1
IF Dec2
IF Out
V
CC2
Lim In
Representative Block Diagram
Osc
N/C
11
N/C
Osc
Emit
MC13158
Data
Slicer
5.0 p
12
Lim
Out
Base
13
Quad
Mix
Mix
In1
In2
1
2
3
4
5
6
7
8
IF Amp
LIM
Amp
10
9
Lim
Lim
Dec2
Dec1
This device contains 234 active transistors.
N/C
14
N/C
EE1
15
Det
Gain
EnableV
Bias
V
2532313029282726
16
EE2
24
23
22
21
20
19
18
17
RSSI
RSSI Buf
DS Gnd
DS Out
DS In2
DS “off”
DS In1
Det Out
MOTOROLA ANALOG IC DEVICE DATA
Motorola, Inc. 1996Rev 1
1
MC13158
MAXIMUM RATINGS
RatingPinSymbolValueUnit
Power Supply Voltage16, 26V
Junction TemperatureT
Storage Temperature RangeT
NOTE: 1.Devices should not be operated at or outside these values. The “Recommended Operating
Conditions” provide for actual device operation.
S(max)
JMAX
stg
6.5Vdc
+150°C
–65 to +150°C
RECOMMENDED OPERATING CONDITIONS (V
Rating
Power Supply Voltage2, 7V
TA = 25°C
–40°C ≤ TA≤ 85°C16, 26
Input Frequency31, 32F
Ambient Temperature RangeT
Input Signal Level31, 32V
DC ELECTRICAL CHARACTERISTICS (T
Characteristic
Total Drain CurrentVS = 2.0 Vdc16, 26I
DATA SLICER (Input Voltage Referenced to VEE; VS = 3.0 Vdc; No Input Signal)
Output Current; V18 LO;V19 = V
Data Slicer Enabled (DS “on”)V18 < V
Output Current; V18 HI;V19 = V
Data Slicer Enabled (DS “on”)V18 > V
Output Current;V19 = V
Data Slicer Disabled (DS “off”)V20 = VS/2
= 25°C; VS = 3.0 Vdc; No Input Signal; See Figure 1.)
A
ConditionPinSymbolMinTypMaxUnit
VS = 3.0 Vdc3.55.78.5
VS = 6.0 Vdc3.56.09.5
See Figure 2
The MC13158 is a low power single conversion wideband
FM receiver incorporating a split IF . This device is designated
for use as the backend in digital FM systems such as Digital
European Cordless Telephone (DECT) and wideband data
links with data rates up to 2.0 Mbps. It contains a mixer,
oscillator, Received Signal Strength Indicator (RSSI), IF
amplifier, limiting IF, quadrature detector, power down or
enable function, and a data slicer with output off function.
Further details are covered in the Pin Function Description
which shows the equivalent internal circuit and external
circuit requirements.
Current Regulation/Enable
Temperature compensating voltage independent current
regulators which are controlled by the enable pin (Pin 25)
where “low” powers up and “high” powers down the entire
circuit.
Mixer
The mixer is a double–balanced four quadrant multiplier
and is designed to work up to 500 MHz. It can be used in
differential or in single ended mode by connecting the other
input to the positive supply rail. The linear gain of the mixer is
approximately 22 dB at 100 mVrms LO drive level. The mixer
gain and noise figure have been emphasized at the expense
of intermodulation performance. RSSI measurements are
added in the mixer to extend the range to higher signal levels.
The single–ended parallel equivalent input impedance of the
mixer is Rp ~ 1.0 kΩ and Cp ~ 2.0 pF. The buffered output of
the mixer is internally loaded resulting in an output
impedance of 330 Ω.
Local Oscillator
The on–chip transistor operates with crystal and LC
resonant elements up to 220 MHz. Series resonant, overtone
crystals are used to achieve excellent local oscillator stability .
Third overtone crystals are used through about 65 to 70 MHz.
Operation from 70 MHz up to 180 MHz is feasible using the
on–chip transistor with a 5th or 7th overtone crystal. To
enhance operation using an overtone crystal, the internal
transistor bias is increased by adding an external resistor
from Pin 29 to VEE; however, with an external resistor the
oscillator stays on during power down. Typically, –10 dBm of
local oscillator drive is needed to adequately drive the mixer.
With an external oscillator source, the IC can be operated up
to 500 MHz.
RSSI
The received signal strength indicator (RSSI) output is a
current proportional to the log of the received signal
amplitude. The RSSI current output is derived by summing
the currents from the mixer, IF and limiting amplifier stages.
An increase in RSSI dynamic range, particularly at higher
input signal levels is achieved. The RSSI circuit is designed
to provide typically 85 dB of dynamic range with temperature
compensation.
Linearity of the RSSI is optimized by using external
ceramic bandpass filters which have an insertion loss of
4.0 dB and 330 Ω source and load impedance. For higher
data rates used in DECT and related applications, LC
bandpass filtering is necessary to acquire the desired
bandpass response; however, the RSSI linearity will require
the same insertion loss.
RSSI Buffer
The RSSI output current creates a voltage across an
external resistor. A unity voltage–gain amplifier is used to
buffer this voltage. The output of this buffer has an active
pull–up but no pull–down, so it can also be used as a peak
detector. The negative slew rate is determined by external
capacitance and resistance to the negative supply .
IF Amplifier
The first IF amplifier section is composed of three
differential stages with the second and third stages
contributing to the RSSI. This section has internal DC
feedback and external input decoupling for improved
symmetry and stability. The total gain of the IF amplifier block
is approximately 40 dB at 10.7 MHz.
The fixed internal input impedance is 330 Ω. When using
ceramic filters requiring source and loss impedances of
330 Ω, no external matching is necessary. Overall RSSI
linearity is dependent on having total midband attenuation of
10 dB (4.0 dB insertion loss plus 6.0 dB impedance matching
loss) for the filter. The output of the IF amplifier is buffered
and the impedance is 330 Ω.
Limiter
The limiter section is similar to the IF amplifier section
except that five differential stages are used. The fixed internal
input impedance is 330 Ω. The total gain of the limiting
amplifier section is approximately 70 dB. This IF limiting
amplifier section internally drives the quadrature detector
section and it is also brought out on Pin 12.
Quadrature Detector
The quadrature detector is a doubly balanced four
quadrant multiplier with an internal 5.0 pF quadrature
capacitor between Pins 12 and 13. An external capacitor may
be added between these pins to increase the IF signal to the
external parallel RLC resonant circuit that provides the
90 degree phase shift and drives the quadrature detector. A
single pin (Pin 13) provides for the external LC parallel
resonant network and the internal connection to the
quadrature detector.
Internal low pass filter capacitors have been selected to
control the bandwidth of the detector. The recovered signal is
brought out by the inverting amplifier buffer. An external
feedback resistor from the output (Pin 17) to the input of the
inverting amplifier (Pin 15) controls the output amplitude; it is
combined with another external resistor from the input to the
negative supply (Pin 16) to set the output dc level. For a
resistor ratio of 1, the DC level at the detector output is
2.0 VBE (see Figure 12). A small capacitor C17 across the
first resistor (from Pin 17 to 15) can be used to reduce the
bandwidth.
Data Slicer
The data slicer is a comparator that is designed to square
up the data signal. Across the data slicer inputs (Pins 18
and 20) are back to back diodes.
6
MOTOROLA ANALOG IC DEVICE DATA
MC13158
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Out
Á
Á
Á
Á
Á
Oscillator, and IF Amplifer. The operating
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
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Á
The recovered data signal from the quadrature detector
can be DC coupled to the data slicer DS IN1 (Pin 18). In the
application circuit shown in Figure 1 it will be centered at
2.0 VBE and allowed to swing ± VBE. A capacitor is placed
from DS IN2 (Pin 20) to VEE. The size of this capacitor and
the nature of the data signal determine how faithfully the data
slicer shapes up the recovered signal. The time constant is
short for large peak to peak voltage swings or when there is
a change in DC level at the detector output. For small signal
or for continuous bits of the same polarity which drift close to
the threshold voltage, the time constant is longer.
PIN FUNCTION DESCRIPTION
Pin
1
ÁÁ
ÁÁ
ÁÁ
2
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
3
ÁÁ
ÁÁ
ÁÁ
ÁÁ
4
Symbol
Mix
Out
ÁÁÁ
ÁÁÁ
ÁÁÁ
V
CC1
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
IF
In
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
IF
Internal Equivalent Circuit
26
2
V
V
CC1
EE1
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2
V
БББББББББББББ
CC1
БББББББББББББ
5
БББББББББББББ
IF Dec2
БББББББББББББ
330
Dec1
ÁÁ
5
ÁÁ
ÁÁ
ÁÁ
ÁÁÁ
IF
ÁÁÁ
Dec2
ÁÁÁ
ÁÁÁ
БББББББББББББ
БББББББББББББ
26
БББББББББББББ
V
EE1
БББББББББББББ
IF In
3
IF Dec1
A unique feature of the data slicer is that the inverting
switching stages in the comparator are supplied through the
emitter pin of the output transistor (Pin 22 – DS Gnd) to V
rather than internally to VEE. This is provided in order to
reduce switching feedback to the front end. A control pin is
provided to shut the data slicer output off (DS “off” – Pin 19).
With DS “off” pin at VCC the data slicer output is shut off by
shutting down the base drive to the output transistor. When a
channel is being monitored to make an RSSI measurement,
but not to collect data, the data output may be shut off to save
current.
Description/External Circuit Requirements
Mixer Output
The mixer output impedance is 330 Ω; it
ББББББББББББ
matches to 10.7 MHz ceramic filters with
330 Ω input impedance.
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Mix
1
Supply V oltage (V
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This pin is the VCC pin for the Mixer, Local
supply voltage range is from 1.8 Vdc to
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5.0 Vdc. In the PCB layout, the VCC trace
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must be kept as wide as possible to minimize
inductive reactances along the trace; it is best
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to have it completely fill around the surface
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mount components and traces on the circuit
side of the PCB.
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CC1
)
IF Input
The input impedance at Pin 3 is 330 Ω. It
ББББББББББББ
64 k
64 k
matches the 330 Ω load impedance of a
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10.7 MHz ceramic filter. Thus, no external
matching is required.
ББББББББББББ
ББББББББББББ
IF DEC1 & DEC2
IF decoupling pins. Decoupling capacitors
should be placed directly at the pins to enhance
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stability . Two capacitors are decoupled to the
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RF ground V
ББББББББББББ
4
& DEC2.
ББББББББББББ
; one is placed between DEC1
CC1
EE
6
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
MOTOROLA ANALOG IC DEVICE DATA
IF
ÁÁÁ
Out
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
БББББББББББББ
БББББББББББББ
БББББББББББББ
БББББББББББББ
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БББББББББББББ
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2
V
CC1
26
V
EE1
IF
Out
IF Output
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The output impedance is 330 Ω; it matches
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the 330 input resistance of a 10.7 MHz
ceramic filter.
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5
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ББББББББББББ
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7
Pin
Á
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Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Limiter Decoupling
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
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Á
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Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Out
Á
Á
Á
Á
7
ÁÁ
ÁÁ
ÁÁ
8
ÁÁ
ÁÁ
9
ÁÁ
ÁÁ
10
ÁÁ
ÁÁ
1 1,14,
27 & 28
ÁÁ
ÁÁ
12
ÁÁ
ÁÁ
13
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
15
ÁÁ
ÁÁ
17
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
16
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Symbol
V
CC2
ÁÁÁ
ÁÁÁ
ÁÁÁ
Lim
ÁÁÁ
In
ÁÁÁ
Lim
ÁÁÁ
Dec1
ÁÁÁ
Lim
ÁÁÁ
Dec2
ÁÁÁ
N/C
ÁÁÁ
ÁÁÁ
Lim
Out
ÁÁÁ
ÁÁÁ
Quad
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
Det
ÁÁÁ
Gain
ÁÁÁ
Det
ÁÁÁ
Out
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
V
EE2
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
MC13158
PIN FUNCTION DESCRIPTION (continued)
Internal Equivalent Circuit
БББББББББББББ
7
V
16
7
V
V
CC2
EE2
10
Dec2
16
V
CC2
Lim
EE2
V
15
16
7
CC2
Det
Gain
V
EE2
33064 k
Lim In
8
Lim Dec1
Lim
Quad
Out
12
13
5.0 p
64 k
9
17
Det
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Description/External Circuit Requirements
Supply Voltage (V
ББББББББББББ
This pin is VCC supply for the Limiter,
Quadrature Detector, data slicer and RSSI
ББББББББББББ
buffer circuits. In the application PC board this
ББББББББББББ
pin is tied to a common VCC trace with V
Limiter Input
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The limiter input impedance is 330 Ω.
ББББББББББББ
Limiter Decou
ББББББББББББ
Decoupling capacitors are placed directly at
ББББББББББББ
these pins and to VCC (RF ground). Use the
ББББББББББББ
same procedure as in the IF decoupling.
ББББББББББББ
lin
CC2
)
CC1
No Connects
There is no internal connection to these pins;
ББББББББББББ
however it is recommended that these pins be
ББББББББББББ
connected externally to VCC (RF ground).
Limiter Output
The output impedance is low. The limiter
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drives a quadrature detector circuit with in–
ББББББББББББ
phase and quadrature phase signals.
Quadrature Detector Circuit
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The quadrature detector is a doubly balanced
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four–quadrant multiplier with an internal 5.0 pF
capacitor between Pins 12 and 13. An external
ББББББББББББ
capacitor may be added to increase the IF
ББББББББББББ
signal to Pin 13. The quadrature detector pin is
provided to connect the external RLC parallel
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resonant network which provides the 90 degree
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phase shift and drives the quadrature detector.
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Detector Buffer Amplifier
ББББББББББББ
This is an inverting amplifier. An external feed-
ББББББББББББ
back resistor from Pin 17 to 15, (the inverting
input) controls the output amplitude; another
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resistor from Pin 15 to the negative supply
ББББББББББББ
(Pin 16) sets the DC output level. A 1:1 resistor
ББББББББББББ
ratio sets the output DC level at two VBE with
respect to VEE. A small capacitor from Pin 17 to
ББББББББББББ
15 can be used to set the bandwidth.
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Supply Ground (V
ББББББББББББ
In the PCB layout, the ground pins (also applies
ББББББББББББ
to Pin 26) should be connected directly to
ББББББББББББ
chassis ground. Decoupling capacitors to V
should be placed directly at the ground pins.
ББББББББББББ
EE2
)
CC
.
8
MOTOROLA ANALOG IC DEVICE DATA
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