Motorola MC12206DT, MC12206D Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 3

 Motorola, Inc. 1997

1/97

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The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked
loop (PLL) synthesizer with pulse–swallow function. It is designed to
provide the high frequency local oscillator signal of an RF transceiver in
handheld communication applications.

Motorola’s advanced Bipolar MOSAIC V technology is utilized for
low power operation at a minimum supply voltage of 2.7V. The device is
designed for operation over 2.7 to 5.5V supply range for input frequencies
up to 2.0GHz with a typical current drain of 7.4mA. The low power
consumption makes the MC12206 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN or
personal communication services. A dual modulus prescaler is integrated
to provide either a 64/65 or 128/129 divide ratio.

For additional applications information, two

InterActiveApNote



documents containing software (based on a Microsoft Excel
spreadsheet) and an Application Note are available. Please order
DK305/D and DK306/D from the Motorola Literature Distribution Center.

• Low Power Supply Current of 6.7mA Typical for I

CC

and 0.7mA Typical

for I

P

• Supply Voltage of 2.7 to 5.5V

• Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or

128/129

• On–Chip Reference Oscillator/Buffer

• Programmable Reference Divider Consisting of a Binary 14–Bit

Programmable Reference Counter

• Programmable Divider Consisting of a Binary 7–Bit Swallow Counter

and an 11–Bit Programmable Counter

• Phase/Frequency Detector With Phase Conversion Function

• Balanced Charge Pump Outputs

• Dual Internal Charge Pumps for Bypassing the First Stage of the Loop

Filter to Decrease Lock Time

• Outputs for External Charge Pump

• Operating Temperature Range of –40°C to +85°C

• Space Efficient Plastic Surface Mount SOIC or TSSOP Packages

MAXIMUM RATINGS*

Symbol

Parameter Value Unit

V

CC

Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package) –0.5 to +6.0 VDC

V

P

Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package) VCC to +6.0 VDC

T

stg

Storage Temperature Range –65 to +150 °C

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the

Recommended Operating Conditions.

MOSAIC V , Mfax and

InterActiveApNote

are trademarks of Motorola, Inc.



D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

1

16

MECL PLL COMPONENTS

Serial Input PLL

Frequency Synthesizer

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–03

1

20

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

2

16

1

φ

R

OSCin

15

2

φ

P

OSCout

14

3

f

OUT

V

P

13

4

BISW

V

CC

Pinout: 16–Lead Package (Top View)

12

5

FC

Do

11

6

LE

GND

10

7

DATA

LD

9

8

CLK

f

IN

20

1

φ

R

OSCin

19

2

NC

NC

18

3

φ

P

OSCout

17

4

f

OUT

V

P

Pinout: 20–Lead Package (Top View)

16

5

BISW

V

CC

15

6

FC

Do

14

7

LE

GND

13

8

DATA

LD

12

9

NC

NC

11

10

CLK

f

IN

PIN NAMES

Pin I/O Function

16–Lead Pkg

Pin No.

20–Lead Pkg

Pin No.

OSCin I Oscillator input. A crystal is connected between OSCin and OSCout. An external

source can be AC coupled into this input

1 1

OSCout O Oscillator output. Pin should be left open if external source is used 2 3
V

P

— Power supply for charge pumps (VP should be greater than or equal to VCC) V

P

provides power to the Do, BISW and φP outputs

3 4

V

CC

— Power supply voltage input. Bypass capacitors should be placed as close as

possible to this pin and be connected directly to the ground plane.

4 5

Do O Internal charge pump output. Do remains on at all times 5 6
GND — Ground 6 7
LD O Lock detect, phase comparator output 7 8
f

IN

I Prescaler input. The VCO signal is AC–coupled into this pin 8 10
CLK I Clock input. Rising edge of the clock shifts data into the shift registers 9 11
DATA I Binary serial data input 10 13
LE I Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data

stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin

11 14

FC I Phase control select (with internal pull up resistor). When FC is LOW, the

characteristics of the phase comparator and charge pump are reversed. FC also
selects fp or fr on the f

OUT

pin

12 15

BISW O Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the

output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance

13 16

f

OUT

O Phase comparator input signal. When FC is HIGH, f

OUT

=fr, programmable

reference divider output; when FC is LOW, f

OUT

=fp, programmable divider output

14 17

φP O Output for external charge pump. Standard CMOS output level 15 18
φR O Output for external charge pump. Standard CMOS output level 16 20

NC — No connect — 2, 9, 12, 19

MC12206

HIPERCOMM
BR1334 — Rev 4

3 MOTOROLA

Figure 1. MC12206 Block Diagram

15–BIT SHIFT REGISTER

15–BIT LATCH

14–BIT REFERENCE COUNTER

fr

CRYST AL

OSCILLAT OR

OSCin

OSCout

PHASE/FREQUENCY

DETECTOR

φ

P

φ

R

CHARGE

PUMP 1

Do

FC

CHARGE

PUMP 2

BISW

PROGRAMMABLE REFERENCE DIVIDER

18–BIT SHIFT REGISTER

7–BIT

LATCH

11–BIT LATCH

DATA

CLK

PROGRAMMABLE DIVIDER

7–BIT

SWALLOW

A–COUNTER

11–BIT

PROGRAMMABLE

N–COUNTER

fp

CONTROL LOGIC

PRESCALER

64/65 or 128/129

f

IN

DIVIDER

OUTPUT MUX

f

OUT

LD

15

14 1

LE

7 11

7 11

CONTROL

BIT

DATA

LE

MC12206

MOTOROLA HIPERCOMM

BR1334 — Rev 4

4

DATA ENTRY FORMAT

The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit
programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock
shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred
into the latch when load enable pin is HIGH or OPEN.

Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider

“L” = data is transferred into 18–bit latch of programmable divider

WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will
affect the VCO.

PROGRAMMABLE REFERENCE DIVIDER

16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If
the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to

16383) and the prescaler divide ratio (SW=0 for ÷128/129, SW=1 for ÷64/65). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:

CR

1

R

2

R
3

R
4

R
5

R
6

R
7

R

8

R
9

R

10

R

11

R

12

R

13

R

14

S

W

SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE

REFERENCE COUNTER (R–COUNTER)

MSB

SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)

LSB

CONTROL BIT (LAST BIT)

DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER

Divide

Ratio R

R

14

R

13

R

12

R

11

R

10

R
9

R
8

R
7

R
6

R
5

R

4

R
3

R
2

R

1
8 0 0 0 0 0 0 0 0 0 0 1 0 0 0
9 0 0 0 0 0 0 0 0 0 0 1 0 0 1

• • • • • • • • • • • • • • •

16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PRESCALER SELECT BIT

Prescaler Divide Ratio P SW

128/129 0

64/65 1