Motorola MC10H174FN, MC10H174L, MC10H174P Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC10H174 is a Dual 4–to–1 Multiplexer. This device is a functional/
pinout duplication of the standard MECL 10K part, with 100% improvement in
propagation delay and no increase in power supply current.
• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 305 mW Typical
• Improved Noise Margin 150 mV (over operating voltage and
temperature range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
Input Voltage (VCC = 0) V
Output Current— Continuous
— Surge
Operating Temperature Range T
Storage Temperature Range— Plastic
— Ceramic
I
T
EE
I
out
A
stg
–8.0 to 0 Vdc
0 to V
EE
50
100
0 to +75 °C
–55 to +150
–55 to +165
Vdc
mA
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
Input Current High
Pins 3–7 & 9–13
Pin 14
Input Current Low I
High Output Voltage V
Low Output Voltage V
High Input Voltage V
Low Input Voltage V
I
E
inH
inL
OH
OL
IH
— 80 — 73 — 80 mA
——475
670——
0.5 — 0.5 — 0.3 — µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
IL
300
420——
µAdc
300
420
AC PARAMETERS
Propagation Delay
Data
Select (A, B)
Enable
Rise Time t
Fall Time t
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated
through a 50–ohm resistor to –2.0 volts.
t
pd
0.7
2.4
0.8
2.5
1.0
2.8
0.4
1.45
0.5 1.5 0.5 1.6 0.5 1.7 ns
r
0.5 1.5 0.5 1.6 0.5 1.7 ns
f
1.1
0.4
2.9
1.5
0.9
1.2
0.5
2.6
3.2
1.7
ns
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
TRUTH TABLE
ENABLE ADDRESS INPUTS OUTPUTS
E
HLL
LLLX0Y0
LLHX1Y1
LHLX2Y2
LHHX3Y3
V
CC1
DO0
DO2
DO1
DO3
V
BAZW
X
X
DIP
PIN ASSIGNMENT
Q0
EE
1
2
3
4
5
6
A
7
8
16
15
14
13
12
11
10
9
V
CC2
Q1
ENABLE
D10
D12
D11
D13
B
9/96
Motorola, Inc. 1996
2–73
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 6
MC10H174
LOGIC DIAGRAM
X0 3
X1 5
X2 4
X3 6
A 7
B9
ENABLE
Y0 13
Y1 11
Y2 12
Y3 10
14
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE = PIN 8
2 Z
15 W
MOTOROLA MECL Data
2–74
DL122 — Rev 6
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