Motorola MC10H173FN, MC10H173P, MC10H173L Datasheet


SEMICONDUCTOR TECHNICAL DATA
   
Data Propagation Delay , 1.5 ns Typical • Voltage Compensated
Power Dissipation, 275 mW Typical • MECL 10K–Compatible
Improved Noise Margin 150 mV (over
operating voltage and temperature range)
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V Input Voltage (VCC = 0) V Output Current — Continuous
— Surge Operating T emperature Range T Storage T emperature Range — Plastic
— Ceramic
EE
I
I
out
A
T
stg
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I Input Current High
Pins 3–7 & 10–13
Pin 9 Input Current Low I High Output Voltage V Low Output Voltage V High Input Voltage V Low Input Voltage V
I
E
inH
inL
OH OL
IH
73 66 73 mA
——510
475——
0.5 0.5 0.3 µA –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
IL
AC PARAMETERS
Propagation Delay
Data Clock Select
Set–up Time
Data Select
Hold Time
Data
Select Rise Time t Fall Time t
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts.
t
t
t
hold
pd
set
0.7
2.3
3.7
3.6
0.7
1.0
1.0
0.7
1.0——
0.7
1.0——
1.0
1.0
0.7
1.0——
0.7
1.0——
0.7 2.4 0.7 2.4 0.7 2.4 ns
r
0.7 2.4 0.7 2.4 0.7 2.4 ns
f
–8.0 to 0 Vdc 0 to V
EE
50
100
0 to +75 °C
–55 to +150 –55 to +165
320 300——
2.3
0.7
3.7
1.0
3.6
1.0
0.7
1.0
0.7
1.0
Vdc
mA
°C °C
320 300
2.3
3.7
3.6
— —
— —
µA

L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
TRUTH TABLE
SELECT CLOCK Q0n +
H
L
X
L L
H
DIP
PIN ASSIGNMENT
Q0
ns
Q1
D11
ns
D10 D01
ns
D00
CLOCK
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
1 2 3 4 5 6 7 8
Book (DL122/D).
16 15 14 13 12 11 10
9
1
D00 D01 Q0
n
V
CC
Q2 Q3 D20 D21 D30 D31 SELECT
3/93
Motorola, Inc. 1996
2–53
REV 5
MC10H173
APPLICATION INFORMATION
The MC10173 is a quad two–channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D1 1, D21, D31. Any change on the data input
LOGIC DIAGRAM
SELECT 9
D00 6
D01 5
D10 4
will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information.
1 Q0
2 Q1
D11 3
D20 13
D21 12
D30 11
D31 10
CLOCK 7
15 Q2
14 Q3
VCC = PIN 16 VEE = PIN 8
MOTOROLA MECL Data
2–54
DL122 — Rev 6
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