SEMICONDUCTOR TECHNICAL DATA
The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro–
nous set (S) and reset (R) are provided. The set and reset inputs override the
clock.
A common clock is provided with separate J
static, the J
–K inputs do not effect the output.
The output states of the flip–flop change on the positive transition of the
clock.
PD= 280 mW typ/pkg (No Load)
f
= 140 MHz typ
Tog
tpd= 3.0 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
S1 5
7
J1
6
K1
R1 4
C 9
S2 12
10
J2
K2 11
Q1
Q1
Q2
Q2
–K inputs. When the clock is
2
3
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE= PIN 8
15
14
CERAMIC PACKAGE
PLASTIC PACKAGE
DIP
PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
K1
J1
V
EE
1
2
3
4
5
6
7
8
L SUFFIX
CASE 620–10
P SUFFIX
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
16
15
14
13
12
11
10
V
Q2
Q2
R2
S2
K2
J2
C
9
CC2
R–S TRUTH TABLE CLOCK J–K TRUTH TABLE*
R S Q
L
L
H
H
N.D. = Not Defined *Output states change on positive
3/93
Motorola, Inc. 1996
R2 13
L
H
L
H
n+1
Q
H
L
N.D.
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
J K Q
n
3–22
L
H
L
H
transition of clock for J
condition present.
L
L
H
H
n+1
Q
L
H
Q
–K input
n
n
REV 5
Book (DL122/D).
MC10135
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load)
Clock Input
Propagation Delay t
Rise Time (20 to 80%) t2+, t
Fall Time (20 to 80%) t2–, t
Set Input ns
Propagation Delay t
Reset Input ns
Propagation Delay t
Setup Time t
Hold Time t
Toggle Frequency (Max) f
1. Individually test each input; apply V
2. Individually test each input; apply V
3. Output level to be measured after a clock pulse has been applied to the C
4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
E
inH
I
inL
OH
OL
OHA
OLA
9+2+
t
9+2–
5+2+
t
12+15+
t
5+3–
t
12+14–
4+2–
t
4+3–
t
13+15–
t
13+14+
setup
hold
tog
IHmax
ILmin
3+
3–
Under
Test
8 75 54 68 75 mAdc
6,7,9,10,1 1
4,5,12,13
4,5,6,7,9,
10,11,12,13
2
2 (3.)
3
3 (3.)
2
2 (4.)
3
3 (4.)
2
2
2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7
2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7
2
15
3
14
2
3
15
14
7 2.5 2.5 1.0 2.5 ns
7 1.5 1.5 1.0 2.5 ns
2 125 125 140 125 MHz
to pin under test.
to pin under test.
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
0.5
0.5
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
425
620
–0.890
–0.890
–1.675
–1.675
–1.655
–1.655
5.0
5.0
5.6
5.6
5.6
5.6
5.6
5.6
5.6
5.6
0.5
0.5
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
Input (Pin 6)
E
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
265
390
–0.810
–0.810
–1.650
–1.650
–1.630
–1.630
4.5
4.5
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
V
IHmax
V
ILmin
V
IHAmax
V
ILAmin
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
0.3
0.3
–0.700
–0.700
–1.615
–1.615
–1.595
–1.595
1.8
1.8
1.8 5.2
1.8
1.8
1.8
1.8
265
390
4.6
4.6
5.2
5.2
5.2
5.2
5.2
5.2
5.2
Unit
µAdc
µAdc
Vdc
Vdc
Vdc
Vdc
ns
DL122 — Rev 6
3–23 MOTOROLAMECL Data
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