SEMICONDUCTOR TECHNICAL DATA
3–8
REV 5
Motorola, Inc. 1996
3/93
The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S)
and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip–flop
may be clocked separately by holding the common clock in the low state and
using the enable inputs for the clocking function. If the common clock is to be
used to clock the flip–flop, the Clock
Enable inputs must be in the low state. In
this case, the enable inputs perform the function of controlling the common
clock.
The output states of the flip–flop change on the positive transition of the
clock. A change in the information present at the data (D) input will not affect the
output information at any other time due to master slave construction.
PD= 235 mW typ/pkg (No Load)
F
Tog
= 160 MHz typ
tpd= 3.0 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
VEE= PIN 8
S1 5
D1 7
C
E1
6
R1 4
CC 9
R2 13
C
E2
11
D2 10
S2 12
Q1
Q
1
Q
2
Q2
2
3
14
15
CLOCKED TRUTH TABLE R–S TRUTH TABLE
C D Q
n+1
R S Q
n+1
L X Q
n
L L Q
n
H L L L H H
H H H H L L
C = CE + CC.A clock H is a clock transition from a
H H N.D.
low to a high state.
N.D. = Not Defined
DIP
PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
C
E1
D1
V
EE
V
CC2
Q2
Q2
R2
S2
C
E2
D2
C
C
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
MC10131
3–9 MOTOROLAMECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 62 45 56 62 mAdc
Input Current I
inH
4
5
6
7
9
525
525
350
390
425
330
330
220
245
265
330
330
220
245
265
µAdc
I
inL
4, 5*
6, 7, 9*
0.5
0.5
0.5
0.5
0.3
0.3
µAdc
Output Voltage Logic 1 V
OH
2
2
[
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
[
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
2
[
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
[
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50Ω Load)
Clock Input
ns
Propagation Delay t
9+2–
t
9+2+
t
6+2+
t
6+2–
2
2
2
2
1.7
1.7
1.7
1.7
4.6
4.6
4.6
4.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
4.5
4.5
4.5
4.5
1.8
1.8
1.8
1.8
5.0
5.0
5.0
5.0
Rise Time (20 to 80%) t
2+
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Fall Time (20 to 80%) t
2–
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Set Input ns
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Reset Input ns
Propagation Delay t
4+2–
t
13+15–
t
4+3–
t
13+14+
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Setup Time t
setup
7 2.5 2.5 2.5 ns
Hold Time t
hold
7 1.5 1.5 1.5 ns
Toggle Frequency (Max) f
tog
2 125 125 160 125 MHz
* Individually test each input applying VIH or VIL to input under test.
[
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
Loading...