MOTOROLA MC10116FN, MC10116FNR2 Datasheet
SEMICONDUCTOR TECHNICAL DATA
3–63
REV 5
Motorola, Inc. 1996
3/93
The MC10116 is a triple differential amplifier designed for use in sensing
differential signals over long lines. The base bias supply (VBB) is made available
at pin 11 to make the device useful as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the MC10116 with excellent common mode
noise rejection. If any amplifier in a package is not used, one input of that
amplifier must be connected to VBB (pin 11) to prevent upsetting the current
source bias network.
Complementary outputs are provided to allow driving twisted pair lines, to
enable cascading of several amplifiers in a chain, or simply to provide
complement outputs of the input logic function.
PD= 85 mW typ/pkg (No Load)
tpd= 2.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
VEE= PIN 8
5
4
11
3
2
10
9
7
6
13
12
15
14
VBB*
*VBB to be used to supply bias to the MC10116 only and bypassed (when used)
with 0.01 µF to 0.1 µF capacitor to ground (0 V). VBB can source < 1.0 mA.
When the input pin with the bubble goes positive, the output pin with the bubble
goes positive.
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
A
OUT
A
IN
A
IN
B
OUT
B
OUT
V
EE
V
CC2
C
OUT
C
OUT
C
IN
C
IN
V
BB
B
IN
B
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MC10116
MOTOROLA MECL Data
DL122 — Rev 6
3–64
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 23 17 21 23 mAdc
Input Current I
inH
4 150 95 95 µAdc
I
CBO
4 1.5 1.0 1.0 µAdc
Output Voltage Logic 1 V
OH
2
3
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
3
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Reference Voltage V
BB
11 –1.420 –1.280 –1.350 –1.230 –1.295 –1.150 Vdc
Switching Times (50Ω Load) ns
Propagation Delay t
4+2+
t
4–2–
t
4+3–
t
4–3+
2
2
3
3
1.0
1.0
1.0
1.0
3.1
3.1
3.1
3.1
1.0
1.0
1.0
1.0
2.0
2.0
2.0
2.0
2.9
2.9
2.9
2.9
1.0
1.0
1.0
1.0
3.3
3.3
3.3
3.3
Rise Time (20 to 80%) t
2+
t
3+
2
3
1.1
1.1
3.6
3.6
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.7
3.7
Fall Time (20 to 80%) t
2–
t
3–
2
3
1.1
1.1
3.6
3.6
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.7
3.7
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