Motorola MC10E141FNR2, MC100E141FNR2, MC100E141FN, MC10E141FN Datasheet
D
4VCCO
D2D
3
Q
2
Q
7
V
CCO
D
5
D
6
D
7
DLSEL0
Q
3
SEL1
CLK
MR
V
EE
DR
D
0
D
1
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
6
Q
5
V
CC
NC
V
CCO
Q
4
Q0Q
1
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 3
Motorola, Inc. 1996
7/96
The MC10E/100E141 is an 8-bit full-function shift register. The E141
performs serial/parallel in and serial/parallel out, shifting in either
direction. The eight inputs D0– D7 accept parallel input data, while
DL/DR accept serial input data for left/right shifting. The Qn outputs do
not need to be terminated for the shift operation to function. To minimize
noise and power, any Q output not used should be left unterminated.
• 700MHz Min. Shift Frequency
• 8-Bit
• Full-Function, Bi-Directional
• Asynchronous Master Reset
• Pin-Compatible with E241
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
The select pins, SEL0 and SEL1, select one of four modes of
operation: Load, Hold, Shift Left, Shift Right, according to the Function
Table.
Input data is accepted a set-up time before the positive clock edge. A
HIGH on the Master Reset (MR) pin asynchronously resets all the
registers to zero.
FUNCTION TABLE
SEL0 SEL1 Function
L L Load
L H Shift Right (Dn to D
n+1
)
H L Shift Left (Dn to D
n –1
)
H H Hold
PIN NAMES
Pin Function
D0– D
7
Parallel Data Inputs
DL, DR Serial Data Inputs
SEL0, SEL1 Mode Select In Inputs
CLK Clock
Q0– Q
7
Data Outputs
MR Master Reset
EXPANDED FUNCTION TABLE
Function DL DR SEL0 SEL1 MR CLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Load X X L L L Z D0 D1 D2 D3 D4 D5 D6 D7
Shift Right X L L H L Z L Q0 Q1 Q2 Q3 Q4 Q5 Q6
X H L H L Z H L Q0 Q1 Q2 Q3 Q4 Q5
Shift Left L X H L L Z L Q0 Q1 Q2 Q3 Q4 Q5 L
H X H L L Z Q0 Q1 Q2 Q3 Q4 Q5 L H
Hold X X H H L Z Q0 Q1 Q2 Q3 Q4 Q5 L H
X X H H L Z Q0 Q1 Q2 Q3 Q4 Q5 L H
Reset X X X X H X L L L L L L L L
8-BIT SHIFT
REGISTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E141 MC100E141
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
LOGIC DIAGRAM
BITS 1 – 6
DL
Q
7
D
Q
R
D
Q
R
D
Q
R
DR
D
0
SEL1
SEL0
CLK
MR
Q
0
D
Q
D
7
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 131 181 131 181 131 181
100E 131 181 131 181 151 181
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
f
SHIFT
Max. Shift Frequency 700 900 700 900 700 900 MH
z
t
PLH
Propagation Delay To Output ps
t
PHL
Clk 625 750 975 625 750 975 625 750 975
MR 600 725 975 600 725 975 600 725 975
t
s
Setup Time ps
D 175 25 175 25 175 25
SEL0 350 200 350 200 350 200
SEL1 300 150 300 150 300 150
t
h
Hold Time ps
D 200 – 25 200 – 25 200 – 25
SEL0 100 – 200 100 – 200 100 – 200
SEL1 100 –150 100 –150 100 –150
t
RR
Reset Recovery Time 900 700 900 700 900 700 ps
t
PW
Minimum Pulse Width ps
Clk, MR 400 400 400
t
SKEW
Within-Device Skew 60 60 60 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 525 800 300 525 800 300 525 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
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