LOGIC DIAGRAM
V
CCO
D
3
D
2
V
EE
D
1
D
0
EN
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
3bQ3a
Q3bQ3aV
CCO
Q2bQ
2a
Q
2b
Q
2a
V
CC
Q
1b
Q
1a
Q
1b
Q
1a
NC V
CCOQ0aQ0b
Q
0aQ0b
V
CCO
D
0
D
1
D
2
D
3
EN
Q
0a
Q
0b
Q
0a
Q
0b
Q
1a
Q
1b
Q
1a
Q
1b
Q
2a
Q
2b
Q
2a
Q
2b
Q
3a
Q
3b
Q
3a
Q
3b
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E112 is a quad driver with two pairs of OR/NOR
outputs from each gate, and a common, buffered enable input. Using the
data inputs the device can serve as an ECL memory address fan-out
driver. Using just the enable input, the device serves as a clock driver,
although the MC10E/100E111 is designed specifically for this purpose,
and offers lower skew than the E112. For memory address driver
applications where scan capabilities are required, please refer to the
E212 device.
• 600ps Max. Propagation Delay
• Common Enable Input
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D0 – D
3
Data Inputs
EN Enable Input
Qna, Q
nb
True Outputs
Qna, Q
nb
Inverting Outputs
QUAD DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E112 MC100E112
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current µA
D 200 200 200
EN 200 200 200
I
EE
Power Supply Current mA
10E 47 56 47 56 47 56
100E 47 56 47 56 54 65
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D 200 400 600 200 400 600 200 400 600
EN 275 450 675 275 450 675 275 450 675
t
SKEW
Within-Device Skew ps
Dn to Qn, Qn 80 80 80 1
Qna to Qnb 40 40 40 2
t
r
Rise/Fall Times ps
t
f
20 - 80% 275 425 700 275 425 700 275 425 700
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Skew defined between common OR or common NOR outputs of a single gate.