Motorola MC10E016FN, MC100E016FNR2, MC10E016FNR2, MC100E016FN Datasheet
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E016 is a high-speed synchronous, presettable,
cascadable 8-bit binary counter. Architecture and operation are the same
as the MC10H016 in the MECL 10H family , extended to 8-bits, as shown
in the logic symbol.
The counter features internal feedback of TC
, gated by the TCLD
(terminal count load) pin. When TCLD is LOW (or left open, in which case
it is pulled LOW by the internal pull-downs), the TC
feedback is disabled,
and counting proceeds continuously, with TC
going LOW to indicate an
all-one state. When TCLD is HIGH, the TC
feedback causes the counter
to automatically reload upon TC
= LOW, thus functioning as a
programmable counter. The Qn outputs do not need to be terminated for
the count function to operate properly. To minimize noise and power,
unused Q outputs should be left unterminated.
• 700MHz Min. Count Frequency
• 1000ps CLK to Q, TC
• Internal TC Feedback (Gated)
• 8-Bit
• Fully Synchronous Counting and TC Generation
• Asynchronous Master Reset
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
FUNCTION TABLE
CE PE TCLD MR CLK Function
X L X L Z Load Parallel (Pn to Qn)
L H L L Z Continuous Count
L H H L Z Count; Load Parallel on TC = LOW
H H X L Z Hold
X X X L ZZ Masters Respond, Slaves Hold
X X X H X Reset (Qn : = LOW, TC : = HIGH)
Z = clock pulse (low to high);
ZZ = clock pulse (high to low)
PIN NAMES
Pin Function
P0 – P
7
Parallel Data (Preset) Inputs
Q0– Q
7
Data Outputs
CE Count Enable Control Input
PE Parallel Load Enable Control Input
MR Master Reset
CLK Clock
TC Terminal Count Output
TCLD TC-Load Control Input
8-BIT SYNCHRONOUS
BINARY UP COUNTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
1
Pinout: 28-Lead PLCC (Top View)
MR
CLK
TCLD
V
EE
NC
P
0
P
1
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
PE
CE P7P6P5V
CCO
TC
Q
7
Q
6
V
CC
Q
5
Q
4
Q
3
P2P3P4V
CCOQ0Q1Q2
V
CCO
* All VCC and V
CCO
pins are tied together on the die.
MC10E016 MC100E016
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
8-BIT BINARY COUNTER LOGIC DIAGRAM
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
P
1
SLAVEMASTER
5
TC
Q
1
Q
0
P7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
CE
Q
0
BIT 1
CE
Q
0
Q0M
Q0M
BIT 0
PE
TCLD
CE
PO
MR
CLK
BIT 7
BITS 2–6
Q
7
MC10E016 MC100E016
2–3 MOTOROLAECLinPS and ECLinPS Lite
DL140 — Rev 4
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 151 181 151 181 151 181
100E 151 181 151 181 174 208
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
f
COUNT
Max. Count Frequency 700 900 700 900 700 900 MHz
t
PLH
Propagation Delay to Output ps
t
PHL
CLK to Q 600 725 1000 600 725 1000 600 725 1000
MR to Q 600 775 1000 600 775 1000 600 775 1000
CLK to TC 550 775 900 550 775 900 550 775 1050
MR to TC 625 775 1000 625 775 1000 625 775 1000
t
s
Setup Time ps
Pn 150 – 30 150 – 30 150 – 30
CE 600 400 600 400 600 400
PE 600 400 600 400 600 400
TCLD 500 300 500 300 500 300
t
h
Hold Time
Pn 350 100 350 100 350 100
CE 0 – 400 0 – 400 0 – 400
PE 0 – 400 0 – 400 0 – 400
TCLD 100 – 300 100 – 300 100 – 300
t
RR
Reset Recovery Time 900 700 900 700 900 700 ps
t
PW
Minimum Pulse Width ps
CLK, MR 400 400 400
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 510 800 300 510 800 300 510
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