Motorola MBRP30090CT Datasheet

MCM101524

MOTOROLA FAST SRAM

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1M x 4 Bit Fast Static Random Access Memory with ECL I/O

The MCM101524 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits. This circuit is fabricated using high performance silicon–gate BiCMOS technology . Asynchronous design eliminates the need for external clocks or timing strobes.

The MCM101524 is available in a 400 mil, 36 lead TAB.

• Fast Access Times: 12, 15 ns

• Equal Address and Chip Select Access Times

• Power Operation: – 195 mA Maximum, Active AC

BLOCK DIAGRAM

ROW

DECODER

MEMORY MATRIX

1024 ROWS x

4096 COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

A15 A14 A13 A12 A11 A10

A9 A8

•

A19 A18 A5 A3 A1

A16

A7 A6 A4 A2

A17

A0 – A19 Address Inputs W Write Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chip Select D0 – D3 Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Q0 – Q3 Data Output NC No Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supply V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN NAMES

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

Order this document

by MCM101524/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM101524

11 12 13

14 15

16 17

32 31 30 29

36 35 34 33

A13

A12

A11

A10

A14

A15

A17

A16

A18

Q2 D2 NC

A9 A4

A5 A6

A3 A8 A19 NC D3 Q3

A1 A2

TB PACKAGE

400 MIL TAB

CASE 984A–01

REV 2 9/94

 Motorola, Inc. 1994

MCM101524 2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

W Operation Data Output Current

H X Not Enabled X L — L H Read X Q I

L L Write X L I

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

VEE Pin Potential (to Ground) V

– 7.0 to + 0.5 V

Voltage Relative to VCC for Any Pin Except V

Vin, V

outVEE

– 0.5 to+ 0.5 V

Output Current (per I/O) I

out

– 50 mA

Power Dissipation P

2.0 W

Temperature Under Bias T

bias

– 30 to + 85 °C

Operating Temperature T

0 to + 60 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE:Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to the OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 0 V, VEE = – 5.2 V ± 5%, TJ = 0 to + 60°C, Unless Otherwise Noted)

DC OPERATING CONDITIONS AND SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

– 5.46 – 5.2 – 4.94 V

Input High Voltage V

– 1165 — – 880 mV

Input Low Voltage V

– 1810 — – 1475 mV

Output High Voltage V

– 1025 — – 880 mV

Output Low Voltage V

– 1810 — – 1620 mV

Input Low Current I

– 50 — — µA

Input High Current I

— — 220 µA

Chip Select Input Low Current I

IL(CS)

0.5 — 170 µA

Operating Power Supply Current: tAVAV = 20 ns (All Outputs Open)* I

— — – 195 mA

Quiescent Power Supply Current: fo = 0 MHz (Outputs Open) I

EEQ

— — – 150 mA

Voltage Compensation (VOH) ∆VOH/∆V

± 35 mV/V @ – 4.94 to – 5.46 V

Voltage Compensation (VOL) ∆VOL/∆V

± 60 mV/V @ – 4.94 to – 5.46 V

*Address Increment

RISE/FALL TIME CHARACTERISTICS

Parameter Symbol Test Condition Min Typ Max Unit

Output Rise Time t

20% to 80% 0.5 1.0 1.5 ns

Output Fall Time t

20% to 80% 0.5 1.0 1.5 ns

CAPACITANCE (f = 1.0 MHz, T

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Typ Max Unit

Input Capacitance Address and Data

, W

3.5 4

7 7

Output Capacitance Q C

out

4 8 pF

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

MCM101524

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VEE = – 5.2 V ± 5%, VCC = 0 V, TJ = 0 to +60°C, Unless Otherwise Noted)

Input Pulse Levels – 1.7 V to – 0.9 V (See Figure 1). . . . . . . . . . . . .

Input Rise/Fall Time 1 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 50%. . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level VOH = – 1165 mV. .

VOL = – 1475 mV

Output Load (AC Test Circuit) See Figure 2. . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1 and 2)

MCM101524–12 MCM101524–15

Parameter Symbol Min Max Min Max Unit Notes

Read Cycle Time t

AVAV

12 — 15 — ns 2, 3

Address Access Time t

AVQV

— 12 — 15 ns

Chip Select Access Time t

SLQV

— 12 — 15 ns 6

Select High to Output Low t

SHQL

0 8 0 9 ns

Output Hold from Address Change t

AXQX

4 — 4 — ns

Power Up Time t

SLIEEH

0 — 0 — ns 4

Power Down Time t

SHIEEL

— 12 — 15 ns 4

NOTES:

1. W

is high for read cycle.

2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. This parameter is sampled and not 100% tested.

5. Device is continuously selected (S

≤ VIL).

6. Addresses valid prior to or coincident with S

going low.

80%

Figure 1. Input Levels Figure 2. AC Test Circuit

AC TEST CONDITIONS

50%

20% 20%

50%

80%

– 0.9 V

– 1.7 V

– 2.0 V

0.01

F0.1 µF

tr = Rise Time tf = Fall Time 50% = Timing Reference Levels

RL = 50

Ω

CL = 30 pF

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