Motorola DSP56800 User Manual

DSP56800FM/D

Rev. 2.0, 05/2002

DSP56800

16-Bit Digital Signal Processor

Family Manual

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 iii

Chapter 1

Introduction

1.1 DSP56800 Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.1.1 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

1.1.2 Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3

1.1.3 Family Members. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

1.2 Introduction to Digital Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

1.3 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

1.4 For the Latest Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

Chapter 2

Core Architecture Overview

2.1 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

2.1.1 Data Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

2.1.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

2.1.3 Program Controller and Hardware Looping Unit. . . . . . . . . . . . . . . . . . . . . . .2-4

2.1.4 Bus and Bit-Manipulation Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.1.5 On-Chip Emulation (OnCE) Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.1.6 Address Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.1.7 Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2.2 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

2.3 Blocks Outside the DSP56800 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

2.3.1 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

2.3.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.3.3 Bootstrap Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.3.4 IP-BUS Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.3.5 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2.4 DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

Chapter 3

Data Arithmetic Logic Unit

3.1 Overview and Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

3.1.1 Data ALU Input Registers (X0, Y1, and Y0) . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

3.1.2 Data ALU Accumulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

3.1.3 Multiply-Accumulator (MAC) and Logic Unit . . . . . . . . . . . . . . . . . . . . . . . .3-5

3.1.4 Barrel Shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

3.1.5 Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

3.1.6 Data Limiter and MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

3.2 Accessing the Accumulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.2.1 Accessing an Accumulator by Its Individual Portions . . . . . . . . . . . . . . . . . . .3-8

Contents

iv DSP56800 Family Manual 

3.2.2 Accessing an Entire Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

3.2.2.1 Accessing for Data ALU Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

3.2.2.2 Writing an Accumulator with a Small Operand . . . . . . . . . . . . . . . . . . . .3-10

3.2.2.3 Extension Registers as Protection Against Overflow. . . . . . . . . . . . . . . .3-10

3.2.2.4 Examples of Writing the Entire Accumulator . . . . . . . . . . . . . . . . . . . . .3-11

3.2.3 General Integer Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

3.2.3.1 Writing Integer Data to an Accumulator . . . . . . . . . . . . . . . . . . . . . . . . .3-11

3.2.3.2 Reading Integer Data from an Accumulator. . . . . . . . . . . . . . . . . . . . . . .3-12

3.2.4 Using 16-Bit Results of DSP Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

3.2.5 Saving and Restoring Accumulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

3.2.6 Bit-Field Operations on Integers in Accumulators. . . . . . . . . . . . . . . . . . . . .3-13

3.2.7 Converting from 36-Bit Accumulator to 16-Bit Portion . . . . . . . . . . . . . . . .3-13

3.3 Fractional and Integer Data ALU Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

3.3.1 Interpreting Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16

3.3.2 Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.3.2.1 Signed Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.3.2.2 Unsigned Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.3.2.3 Signed Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

3.3.2.4 Unsigned Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

3.3.3 Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

3.3.4 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

3.3.5 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

3.3.5.1 Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19

3.3.5.2 Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20

3.3.6 Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

3.3.7 Unsigned Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

3.3.7.1 Conditional Branch Instructions for Unsigned Operations. . . . . . . . . . . .3-22

3.3.7.2 Unsigned Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

3.3.8 Multi-Precision Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23

3.3.8.1 Multi-Precision Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . .3-23

3.3.8.2 Multi-Precision Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23

3.4 Saturation and Data Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26

3.4.1 Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26

3.4.2 MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28

3.4.3 Instructions Not Affected by the MAC Output Limiter . . . . . . . . . . . . . . . . .3-29

3.5 Rounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-30

3.5.1 Convergent Rounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-30

3.5.2 Two’s-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31

3.6 Condition Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33

3.6.1 36-Bit Destinations—CC Bit Cleared. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33

3.6.2 36-Bit Destinations—CC Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34

3.6.3 20-Bit Destinations—CC Bit Cleared. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34

3.6.4 20-Bit Destinations—CC Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34

3.6.5 16-Bit Destinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35

3.6.6 Special Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35

3.6.7 TST and TSTW Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36

3.6.8 Unsigned Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-36

 v

Chapter 4

Address Generation Unit

4.1 Architecture and Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2

4.1.1 Address Registers (R0-R3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.1.2 Stack Pointer Register (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.1.3 Offset Register (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.1.4 Modifier Register (M01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4.1.5 Modulo Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4.1.6 Incrementer/Decrementer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

4.2.1 Register-Direct Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

4.2.1.1 Data or Control Register Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

4.2.1.2 Address Register Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

4.2.2 Address-Register-Indirect Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

4.2.2.1 No Update: (Rn), (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

4.2.2.2 Post-Increment by 1: (Rn)+, (SP)+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

4.2.2.3 Post-Decrement by 1: (Rn)-, (SP)- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12

4.2.2.4 Post-Update by Offset N: (Rn)+N, (SP)+N . . . . . . . . . . . . . . . . . . . . . . .4-13

4.2.2.5 Index by Offset N: (Rn+N), (SP+N). . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14

4.2.2.6 Index by Short Displacement: (SP-xx), (R2+xx) . . . . . . . . . . . . . . . . . . .4-15

4.2.2.7 Index by Long Displacement: (Rn+xxxx), (SP+xxxx). . . . . . . . . . . . . . .4-16

4.2.3 Immediate Data Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17

4.2.3.1 Immediate Data: #xxxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18

4.2.3.2 Immediate Short Data: #xx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20

4.2.4 Absolute Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20

4.2.4.1 Absolute Address (Extended Addressing): xxxx . . . . . . . . . . . . . . . . . . .4-21

4.2.4.2 Absolute Short Address (Direct Addressing): <aa> . . . . . . . . . . . . . . . . .4-22

4.2.4.3 I/O Short Address (Direct Addressing): <pp> . . . . . . . . . . . . . . . . . . . . .4-23

4.2.5 Implicit Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23

4.2.6 Addressing Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23

4.3 AGU Address Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25

4.3.1 Linear Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25

4.3.2 Modulo Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25

4.3.2.1 Modulo Arithmetic Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25

4.3.2.2 Configuring Modulo Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-27

4.3.2.3 Supported Memory Access Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .4-29

4.3.2.4 Simple Circular Buffer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29

4.3.2.5 Setting Up a Modulo Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-30

4.3.2.6 Wrapping to a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-31

4.3.2.7 Side Effects of Modulo Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-32

4.3.2.7.1 When a Pointer Lies Outside a Modulo Buffer . . . . . . . . . . . . . . . . .4-32

4.3.2.7.2 Restrictions on the Offset Register. . . . . . . . . . . . . . . . . . . . . . . . . . .4-32

4.3.2.7.3 Memory Locations Not Available for Modulo Buffers . . . . . . . . . . .4-33

4.4 Pipeline Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-33

Chapter 5

Program Controller

vi DSP56800 Family Manual 

5.1 Architecture and Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5.1.1 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5.1.2 Instruction Latch and Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5.1.3 Interrupt Control Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5.1.4 Looping Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

5.1.5 Loop Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

5.1.6 Loop Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5

5.1.7 Hardware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

5.1.8 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

5.1.8.1 Carry (C)—Bit 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.1.8.2 Overflow (V)—Bit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.1.8.3 Zero (Z)—Bit 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.1.8.4 Negative (N)—Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

5.1.8.5 Unnormalized (U)—Bit 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.1.8.6 Extension (E)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.1.8.7 Limit (L)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.1.8.8 Size (SZ)—Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.1.8.9 Interrupt Mask (I1 and I0)—Bits 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

5.1.8.10 Reserved SR Bits— Bits 10–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9

5.1.8.11 Loop Flag (LF)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9

5.1.9 Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9

5.1.9.1 Operating Mode Bits (MB and MA)—Bits 1–0. . . . . . . . . . . . . . . . . . . .5-10

5.1.9.2 External X Memory Bit (EX)—Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11

5.1.9.3 Saturation (SA)—Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11

5.1.9.4 Rounding Bit (R)—Bit 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.9.5 Stop Delay Bit (SD)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.9.6 Condition Code Bit (CC)—Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.9.7 Nested Looping Bit (NL)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

5.1.9.8 Reserved OMR Bits—Bits 2, 7 and 9–14. . . . . . . . . . . . . . . . . . . . . . . . .5-13

5.2 Software Stack Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

5.3 Program Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

5.3.1 Repeat (REP) Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

5.3.2 DO Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15

5.3.3 Nested Hardware DO and REP Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15

5.3.4 Terminating a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15

Chapter 6

Instruction Set Introduction

6.1 Introduction to Moves and Parallel Moves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

6.2 Instruction Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3

6.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5

6.4 Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6

6.4.1 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6

6.4.2 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

6.4.3 Bit-Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

6.4.4 Looping Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

6.4.5 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

 vii

6.4.6 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11

6.5 Instruction Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12

6.5.1 ANDC, EORC, ORC, and NOTC Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12

6.5.2 LSLL Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13

6.5.3 ASL Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13

6.5.4 CLR Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13

6.5.5 POP Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14

6.6 DSP56800 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14

6.6.1 Register Field Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14

6.6.2 Using the Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16

6.6.3 Instruction Summary Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-17

6.7 The Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-30

6.7.1 Instruction Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-30

6.7.2 Memory Access Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-31

Chapter 7

Interrupts and the Processing States

7.1 Reset Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

7.2 Normal Processing State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2

7.2.1 Instruction Pipeline Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2

7.2.2 Instruction Pipeline with Off-Chip Memory Accesses. . . . . . . . . . . . . . . . . . .7-3

7.2.3 Instruction Pipeline Dependencies and Interlocks . . . . . . . . . . . . . . . . . . . . . .7-4

7.3 Exception Processing State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

7.3.1 Sequence of Events in the Exception Processing State . . . . . . . . . . . . . . . . . .7-5

7.3.2 Reset and Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

7.3.3 Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

7.3.4 Configuring Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

7.3.5 Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9

7.3.5.1 External Hardware Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10

7.3.5.2 DSP Core Hardware Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . .7-11

7.3.5.3 DSP Core Software Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11

7.3.6 Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-12

7.3.7 The Interrupt Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14

7.3.8 Interrupt Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16

7.4 Wait Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17

7.5 Stop Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19

7.6 Debug Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22

Chapter 8

Software Techniques

8.1 Useful Instruction Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

8.1.1 Jumps and Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

8.1.1.1 JRSET and JRCLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

8.1.1.2 BR1SET and BR1CLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

8.1.1.3 JR1SET and JR1CLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

8.1.1.4 JVS, JVC, BVS, and BVC Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

viii DSP56800 Family Manual 

8.1.1.5 Other Jumps and Branches on Condition Codes . . . . . . . . . . . . . . . . . . . .8-4

8.1.2 Negation Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8.1.2.1 NEGW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8.1.2.2 Negating the X0, Y0, or Y1 Data ALU registers . . . . . . . . . . . . . . . . . . . .8-5

8.1.2.3 Negating an AGU register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5

8.1.2.4 Negating a Memory Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5

8.1.3 Register Exchanges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

8.1.4 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

8.1.4.1 MAX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

8.1.4.2 MIN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7

8.1.5 Accumulator Sign Extend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7

8.1.6 Unsigned Load of an Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7

8.2 16- and 32-Bit Shift Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8

8.2.1 Small Immediate 16- or 32-Bit Shifts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8

8.2.2 General 16-Bit Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8

8.2.3 General 32-Bit Arithmetic Right Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9

8.2.4 General 32-Bit Logical Right Shifts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9

8.2.5 Arithmetic Shifts by a Fixed Amount. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10

8.2.5.1 Right Shifts (ASR12–ASR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-10

8.2.5.2 Left Shifts (ASL16–ASL19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12

8.3 Incrementing and Decrementing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

8.4 Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

8.4.1 Positive Dividend and Divisor with Remainder. . . . . . . . . . . . . . . . . . . . . . .8-14

8.4.2 Signed Dividend and Divisor with No Remainder. . . . . . . . . . . . . . . . . . . . .8-15

8.4.3 Signed Dividend and Divisor with Remainder. . . . . . . . . . . . . . . . . . . . . . . .8-16

8.4.4 Algorithm Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18

8.4.5 Overflow Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19

8.5 Multiple Value Pushes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19

8.6 Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20

8.6.1 Large Loops (Count Greater Than 63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20

8.6.2 Variable Count Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21

8.6.3 Software Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21

8.6.4 Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

8.6.4.1 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

8.6.4.2 Nested Hardware DO and REP Loops . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23

8.6.4.3 Comparison of Outer Looping Techniques . . . . . . . . . . . . . . . . . . . . . . .8-24

8.6.5 Hardware DO Looping in Interrupt Service Routines . . . . . . . . . . . . . . . . . .8-25

8.6.6 Early Termination of a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25

8.7 Array Indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26

8.7.1 Global or Fixed Array with a Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26

8.7.2 Global or Fixed Array with a Variable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8.7.3 Local Array with a Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8.7.4 Local Array with a Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8.7.5 Array with an Incrementing Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8.8 Parameters and Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-28

8.9 Time-Critical DO Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-29

8.10 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-30

 ix

8.10.1 Setting Interrupt Priorities in Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-30

8.10.1.1 High Priority or a Small Number of Instructions . . . . . . . . . . . . . . . . . . .8-31

8.10.1.2 Many Instructions of Equal Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-31

8.10.1.3 Many Instructions and Programmable Priorities . . . . . . . . . . . . . . . . . . .8-32

8.10.2 Hardware Looping in Interrupt Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-32

8.10.3 Identifying System Calls by a Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-32

8.11 Jumps and JSRs Using a Register Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-33

8.12 Freeing One Hardware Stack Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-34

8.13 Multitasking and the Hardware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-34

8.13.1 Saving the Hardware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-35

8.13.2 Restoring the Hardware Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-35

Chapter 9

JTAG and On-Chip Emulation (OnCE™)

9.1 Combined JTAG and OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1

9.2 JTAG Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2

9.2.1 JTAG Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

9.2.2 JTAG Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

9.3 OnCE Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4

9.3.1 OnCE Port Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5

9.3.2 OnCE Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5

9.3.2.1 Command, Status, and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9.3.2.2 Breakpoint and Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9.3.2.3 Pipeline Save and Restore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9.3.2.4 FIFO History Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

Appendix A

Instruction Set Details

A.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

A.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A.4 Condition Code Computation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6

A.4.1 The Condition Code Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A.4.1.1 Size (SZ)—Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

A.4.1.2 Limit (L)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

A.4.1.3 Extension in Use (E)—Bit 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

A.4.1.4 Unnormalized (U)—Bit 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

A.4.1.5 Negative (N)—Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9

A.4.1.6 Zero (Z)—Bit 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.4.1.7 Overflow (V)—Bit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.4.1.8 Carry (C)—Bit 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10

A.4.2 Effects of the Operating Mode Register’s SA Bit . . . . . . . . . . . . . . . . . . . . A-11

A.4.3 Effects of the OMR’s CC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

A.4.4 Condition Code Summary by Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . A-12

A.5 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-16

A.6 Instruction Set Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26

x DSP56800 Family Manual 

A.7 Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27

Appendix B

DSP Benchmarks

B.1 Benchmark Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

B.1.1 Real Correlation or Convolution (FIR Filter). . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.1.2 N Complex Multiplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.1.3 Complex Correlation Or Convolution (Complex FIR). . . . . . . . . . . . . . . . . . B-4

B.1.4 Nth Order Power Series (Real, Fractional Data) . . . . . . . . . . . . . . . . . . . . . . B-5

B.1.5 N Cascaded Real Biquad IIR Filters (Direct Form II) . . . . . . . . . . . . . . . . . . B-5

B.1.6 N Radix 2 FFT Butterflies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

B.1.7 LMS Adaptive Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

B.1.7.1 Single Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9

B.1.7.2 Double Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10

B.1.7.3 Double Precision Delayed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-11

B.1.8 Vector Multiply-Accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

B.1.9 Energy in a Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13

B.1.10 [3x3][1x3] Matrix Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14

B.1.11 [NxN][NxN] Matrix Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

B.1.12 N Point 3x3 2-D FIR Convolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17

B.1.13 Sine-Wave Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20

B.1.13.1 Double Integration Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20

B.1.13.2 Second Order Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21

B.1.14 Array Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22

B.1.14.1 Index of the Highest Signed Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22

B.1.14.2 Index of the Highest Positive Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22

B.1.15 Proportional Integrator Differentiator (PID) Algorithm. . . . . . . . . . . . . . . . B-23

B.1.16 Autocorrelation Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24

 xi

Table 3-1 Accessing the Accumulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Table 3-2 Interpretation of 16-Bit Data Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Table 3-3 Interpretation of 36-bit Data Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Table 3-4 Saturation by the Limiter Using the MOVE Instruction. . . . . . . . . . . . . . . . . . 3-27

Table 3-5 MAC Unit Outputs with Saturation Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29

Table 4-1 Addressing Mode Forcing Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 4-2 Jump and Branch Forcing Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Table 4-3 Addressing Mode—Register Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Table 4-4 Addressing Mode—Address Register Indirect. . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-5 Address-Register-Indirect Addressing Modes Available . . . . . . . . . . . . . . . . . . 4-9

Table 4-6 Addressing Mode—Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Table 4-7 Addressing Mode—Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

Table 4-8 Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Table 4-9 Programming M01 for Modulo Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Table 5-1 Interrupt Mask Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Table 5-2 Program ROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Table 5-3 Program RAM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Table 5-4 MAC Unit Outputs With Saturation Mode Enabled (SA = 1) . . . . . . . . . . . . . 5-11

Table 5-5 Looping Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Table 6-1 Memory Space Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Table 6-2 Instruction Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Table 6-3 Arithmetic Instructions List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-4 Logical Instructions List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Table 6-5 Bit-Field Instruction List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Table 6-6 Loop Instruction List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Table 6-7 Move Instruction List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Table 6-8 Program Control Instruction List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Table 6-9 Aliases for Logical Instructions with Immediate Data. . . . . . . . . . . . . . . . . . . 6-12

Table 6-10 LSLL Instruction Alias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Table 6-11 ASL Instruction Remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Table 6-12 Clear Instruction Alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Table 6-13 Move Word Instruction Alias—Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Table 6-14 Register Fields for General-Purpose Writes and Reads . . . . . . . . . . . . . . . . . . 6-15

Table 6-15 Address Generation Unit (AGU) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

List of Tables

xii DSP56800 Family Manual 

Table 6-16 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Table 6-17 Move Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Table 6-18 Immediate Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

Table 6-19 Register-to-Register Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

Table 6-20 Move Word Instructions—Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

Table 6-21 Conditional Register Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Table 6-22 Data ALU Multiply Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Table 6-23 Data ALU Extended Precision Multiplication Instructions . . . . . . . . . . . . . . . 6-21

Table 6-24 Data ALU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

Table 6-25 Data ALU Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

Table 6-26 Data ALU Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

Table 6-27 Data ALU Shifting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

Table 6-28 AGU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

Table 6-29 Bit-Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

Table 6-30 Branch on Bit-Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

Table 6-31 Change of Flow Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27

Table 6-32 Looping Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27

Table 6-33 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Table 6-34 Data ALU Instructions—Single Parallel Move . . . . . . . . . . . . . . . . . . . . . . . . 6-29

Table 6-35 Data ALU Instructions—Dual Parallel Read . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30

Table 7-1 Processing States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

Table 7-2 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Table 7-3 Additional Cycles for Off-Chip Memory Accesses . . . . . . . . . . . . . . . . . . . . . . 7-4

Table 7-4 DSP56800 Core Reset and Interrupt Vector Table. . . . . . . . . . . . . . . . . . . . . . . 7-7

Table 7-5 Interrupt Priority Level Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

Table 7-6 Interrupt Mask Bit Definition in the Status Register . . . . . . . . . . . . . . . . . . . . . 7-8

Table 7-7 Fixed Priority Structure Within an IPL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

Table 8-1 Operations Synthesized Using DSP56800 Instructions . . . . . . . . . . . . . . . . . . . 8-1

Table A-1 Register Fields for General-Purpose Writes and Reads. . . . . . . . . . . . . . . . . . . . . . . . . A-1

Table A-2 Address Generation Unit (AGU) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Table A-3 Data ALU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

Table A-4 Address Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Table A-5 Addressing Mode Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Table A-6 Miscellaneous Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Table A-7 Other Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

Table A-8 Notation Used for the Condition Code Summary Table . . . . . . . . . . . . . . . . . . . . . . . A-12

Table A-9 Condition Code Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13

Table A-10 Instruction Timing Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17

Table A-11 Instruction Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18

 xiii

Table A-12 Parallel Move Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19

Table A-13 MOVEC Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

Table A-14 MOVEM Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

Table A-15 Bit-Field Manipulation Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

Table A-16 Branch/Jump Instruction Timing Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20

Table A-17 RTS Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21

Table A-18 TSTW Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21

Table A-19 Addressing Mode Timing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21

Table A-20 Memory Access Timing Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22

Table B-1 Benchmark Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Table B-2 Variable Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17

xiv DSP56800 Family Manual 

 xv

Figure 1-1 DSP56800-Based DSP Microcontroller Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Figure 1-2 DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-3 Example of Chip Built Around the DSP56800 Core . . . . . . . . . . . . . . . . . . . . . 1-5

Figure 1-4 Analog Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Figure 1-5 Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Figure 1-6 Mapping DSP Algorithms into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 2-1 DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2 DSP56800 Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-3 Sample DSP56800-Family Chip Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 2-7

Figure 2-4 DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Figure 3-1 Data ALU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Figure 3-2 Data ALU Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 3-3 Right and Left Shifts Through the Multi-Bit Shifting Unit . . . . . . . . . . . . . . . . 3-6

Figure 3-4 Writing the Accumulator Extension Registers (F2) . . . . . . . . . . . . . . . . . . . . . . 3-8

Figure 3-5 Reading the Accumulator Extension Registers (F2). . . . . . . . . . . . . . . . . . . . . . 3-9

Figure 3-6 Writing the Accumulator by Portions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Figure 3-7 Writing the Accumulator as a Whole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Figure 3-8 Bit Weightings and Operand Alignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Figure 3-9 Word-Sized Integer Addition Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Figure 3-10 Comparison of Integer and Fractional Multiplication . . . . . . . . . . . . . . . . . . . 3-19

Figure 3-11 MPY Operation—Fractional Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Figure 3-12 Integer Multiplication (IMPY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

Figure 3-13 Single-Precision Times Double-Precision Signed Multiplication . . . . . . . . . . 3-24

Figure 3-14 Example of Saturation Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

Figure 3-15 Convergent Rounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

Figure 3-16 Two’s-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Figure 4-1 Address Generation Unit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-2 Address Generation Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-3 Address Register Indirect: No Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Figure 4-4 Address Register Indirect: Post-Increment. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Figure 4-5 Address Register Indirect: Post-Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-6 Address Register Indirect: Post-Update by Offset N . . . . . . . . . . . . . . . . . . . . 4-13

Figure 4-7 Address Register Indirect: Indexed by Offset N. . . . . . . . . . . . . . . . . . . . . . . . 4-14

Figure 4-8 Address Register Indirect: Indexed by Short Displacement. . . . . . . . . . . . . . . 4-15

List of Figures

xvi DSP56800 Family Manual 

Figure 4-9 Address Register Indirect: Indexed by Long Displacement. . . . . . . . . . . . . . . 4-16

Figure 4-10 Special Addressing: Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Figure 4-11 Special Addressing: Immediate Short Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19

Figure 4-12 Special Addressing: Absolute Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21

Figure 4-13 Special Addressing: Absolute Short Address. . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

Figure 4-14 Special Addressing: I/O Short Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

Figure 4-15 Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Figure 4-16 Circular Buffer with Size M=37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

Figure 4-17 Simple Five-Location Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

Figure 4-18 Linear Addressing with a Modulo Modifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

Figure 5-1 Program Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Figure 5-2 Program Controller Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

Figure 5-3 Accessing the Loop Count Register (LC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Figure 5-4 Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Figure 5-5 Operating Mode Register (OMR) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Figure 6-1 Single Parallel Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Figure 6-2 Dual Parallel Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Figure 6-3 DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Figure 6-4 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

Figure 7-1 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

Figure 7-2 Example Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-3 Example On-Chip Peripheral and IRQ Interrupt Programming. . . . . . . . . . . . . 7-9

Figure 7-4 Illegal Instruction Interrupt Servicing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

Figure 7-5 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Figure 7-6 Repeated Illegal Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Figure 7-7 Interrupting a REP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

Figure 7-8 Wait Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Figure 7-9 Simultaneous Wait Instruction and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

Figure 7-10 STOP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19

Figure 7-11 STOP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20

Figure 7-12 STOP Instruction Sequence Recovering with RESET . . . . . . . . . . . . . . . . . . . 7-21

Figure 8-1 Example of a DSP56800 Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29

Figure 9-1 JTAG/OnCE Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

Figure 9-2 JTAG Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

Figure 9-3 OnCE Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

Figure A-1 DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5

Figure A-2 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7

Figure B-1 N Radix 2 FFT Butterflies Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6

Figure B-2 LMS Adaptive Filter Graphic Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7

 xvii

Figure B-3 LMS Adaptive Filter—Single Precision Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . B-9

Figure B-4 LMS Adaptive Filter—Double Precision Memory Map . . . . . . . . . . . . . . . . . . . . . . . B-10

Figure B-5 LMS Adaptive Filter—Double Precision Delayed Memory Map . . . . . . . . . . . . . . . . B-11

Figure B-6 Vector Multiply-Accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12

Figure B-7 [3x3][1x3] Matrix Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14

Figure B-8 [NxN][NxN] Matrix Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

Figure B-9 3x3 Coefficient Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17

Figure B-10 Image Stored as 514x514 Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17

Figure B-11 Sine Wave Generator—Double Integration Technique . . . . . . . . . . . . . . . . . . . . . . . . B-20

Figure B-12 Sine Wave Generator—Second Order Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21

Figure B-13 Proportional Integrator Differentiator Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-23

xviii DSP56800 Family Manual 

 xix

Example 3-1 Loading an Accumulator with a Word for Integer Processing . . . . . . . . . . . . . 3-11

Example 3-2 Reading a Word from an Accumulator for Integer Processing . . . . . . . . . . . . 3-12

Example 3-3 Correctly Reading a Word from an Accumulator to a D/A . . . . . . . . . . . . . . . 3-12

Example 3-4 Correct Saving and Restoring of an Accumulator—Word Accesses . . . . . . . . 3-13

Example 3-5 Bit Manipulation on an Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Example 3-6 Converting a 36-Bit Accumulator to a 16-Bit Value . . . . . . . . . . . . . . . . . . . . 3-14

Example 3-7 Fractional Arithmetic Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Example 3-8 Integer Arithmetic Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Example 3-9 Multiplying Two Signed Integer Values with Full Precision. . . . . . . . . . . . . . 3-21

Example 3-10 Fast Integer MACs using Fractional Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . 3-21

Example 3-11 Multiplying Two Unsigned Fractional Values. . . . . . . . . . . . . . . . . . . . . . . . . 3-23

Example 3-12 64-Bit Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

Example 3-13 64-Bit Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

Example 3-14 Fractional Single-Precision Times Double-Precision Value—Both Signed . . 3-24

Example 3-15 Integer Single-Precision Times Double-Precision Value—Both Signed. . . . . 3-24

Example 3-16 Multiplying Two Fractional Double-Precision Values. . . . . . . . . . . . . . . . . . . 3-25

Example 3-17 Demonstrating the Data Limiter—Positive Saturation. . . . . . . . . . . . . . . . . . . 3-26

Example 3-18 Demonstrating the Data Limiter — Negative Saturation . . . . . . . . . . . . . . . . . 3-27

Example 3-19 Demonstrating the MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

Example 4-1 Initializing the Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

Example 4-2 Accessing the Circular Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

Example 4-3 Accessing the Circular Buffer with Post-Update by Three . . . . . . . . . . . . . . . 4-30

Example 4-4 No Dependency with the Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33

Example 4-5 No Dependency with an Address Pointer Register. . . . . . . . . . . . . . . . . . . . . . 4-33

Example 4-6 No Dependency with No Address Arithmetic Calculation. . . . . . . . . . . . . . . . 4-34

Example 4-7 No Dependency with (Rn+xxxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

Example 4-8 Dependency with a Write to the Offset Register . . . . . . . . . . . . . . . . . . . . . . . 4-34

Example 4-9 Dependency with a Bit-Field Operation on the Offset Register. . . . . . . . . . . . 4-34

Example 4-10 Dependency with a Write to an Address Pointer Register . . . . . . . . . . . . . . . . 4-34

Example 4-11 Dependency with a Write to the Modifier Register . . . . . . . . . . . . . . . . . . . . . 4-35

Example 4-12 Dependency with a Write to the Stack Pointer Register. . . . . . . . . . . . . . . . . . 4-35

Example 4-13 Dependency with a Bit-Field Operation and DO Loop . . . . . . . . . . . . . . . . . . 4-35

List of Examples

xx DSP56800 Family Manual 

Example 6-1 MOVE Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Example 6-2 Logical OR with a Data Memory Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Example 6-3 Valid Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Example 6-4 Invalid Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Example 6-5 Examples of Single Parallel Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29

Example 7-1 Pipeline Dependencies in Similar Code Sequences . . . . . . . . . . . . . . . . . . . . . . 7-4

Example 7-2 Common Pipeline Dependency Code Sequence. . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Example 8-1 JRSET and JRCLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Example 8-2 BR1SET and BR1CLR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Example 8-3 JR1SET and JR1CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

Example 8-4 JVS, JVC, BVS and BVC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Example 8-5 JPL and BES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Example 8-6 Simple Fractional Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Example 8-7 Signed Fractional Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Example 8-8 Simple Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Example 8-9 Signed Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Example A-1 Arithmetic Instruction with Two Parallel Reads . . . . . . . . . . . . . . . . . . . . . . . A-22

Example A-2 Jump Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23

Example A-3 RTS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25

Example B-1 Source Code Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

 xxi

About This Book

This manual describes the central processing unit of the DSP56800 Family in detail. It is intended to be
used with the appropriate DSP56800 Family member user’s manual, which describes the central
processing unit, programming models, and details of the instruction set. The appropriate DSP56800
Family member technical data sheet provides timing, pinout, and packaging descriptions.

This manual provides practical information to help the user accomplish the following:

• Understand the operation and instruction set of the DSP56800 Family

• Write code for DSP algorithms

• Write code for general control tasks

• Write code for communication routines

• Write code for data manipulation algorithms

Audience

The information in this manual is intended to assist design and software engineers with integrating a
DSP56800 Family device into a design and with developing application software.

Organization

Information in this man ual is organized into cha pters by topic. The contents of the chapters are as follows:
Chapter 1, “Introduction.” This section in troduces t he DSP56800 core ar chitect ure and its applicati on. It

also provides the novice with a brief overview of digital signal processing.
Chapter 2, “Core Architecture Overview.” The DSP56800 core architecture consists of the data

arithmetic logic uni t ( ALU), ad dress generation unit (AGU), pr ogr am co ntr o l ler, bus and bit-manipulati on
unit, and a JTAG/On-Chip Emulat ion (OnCE

™) port. This section descr ibes each subsystem and the buses

interconnecting the major components in the DSP56800 central processing module.
Chapter 3, “Data Arithmetic Logic Unit.” This section describes the data ALU architecture, its

programming model, an introduction to fractional and integer arithmetic, and a discussion of other topics
such as unsigned and multi-precision arithmetic on the DSP56800 Family.

Chapter 4, “Address Generation Unit.” This sec tion specifically de scr ibes the AGU architectur e and its
programming model, addressing modes, and address modifiers.

Chapter 5, “Program Controll er.” This section describes i n detail the p rogram control ler archite cture, its
programming model, and hardware looping. Note, however, that the different processing states of the
DSP56800 core, including interrupt processing, are described in Chapter 7, “Interrupts and the Processing
States.”

xxii DSP56800 Family Manual 

Chapter 6, “Instruction Set Intr oductio n.” This section presents a n int roduct ion to para llel moves and a
brief description of the syntax, instruction formats, operand and memory references, data organization,
addressing modes, and instruction set. It also includes a summary of the instruction set, showing the
registers and addressing modes available to each instruction. A detailed description of each instruction is
given in Appendix A, “Instruction S et Details.”

Chapter 7, “Interrupts and the Processing States.” This section describes five of the six processing
states (normal, exception, reset, wait, and stop). The sixth processing state (debug) is covered more
completely in Chapter 9, “JTAG and On-Chip Emulation (OnCE™).”

Chapter 8, “Software Techniques.” Th is sect ion tea che s the adva nced use r techni que s for more eff icie nt
programming of the DSP56800 Family. It includes a description of useful instruction sequences and
macros, optimal loop and interrupt programming, topics related to the stack of the DSP56800, and other
useful software topics.

Chapter 9, “JTAG and On-Chip Emulation (OnCE™).” This section describes the combined
JTAG/OnCE port and its funct ions. Thes e two are i ntegra lly re lated , sharin g the same pins f or I/O, and a re
presented together in this section.

Appendix A, “Instruction Set Details.” This section presents a detailed description of each DSP56800
Family instruction, its use, and its effect on the processor.

Appendix B, “DSP Benchmarks.” DSP56800 Family benchmark examp le programs and resul ts are list ed
in this appendix.

Suggested Reading

A list of DSP-related books is included here as an aid for the engineer who is new to the field of DSP:

Advanced Topics in Signal Processing, Jae S. Lim and Alan V. Oppenheim (Prentice-Hall: 1988).
Applications of Digital Signal Processing, A. V. Oppenhei m (Prent ice-Hall: 1978).
Digital Processing of Signals: Theory and Practice, Maurice Bellanger (John Wiley and Sons: 1984).
Digital Signal Processing, Alan V. Oppenheim and Ronald W. Schafer (Prentice-Hall: 1975).
Digital Signal Proces sing: A Syste m Design Ap proach, Da vid J. DeF atta, Joseph G. Lu cas, an d Willi am S.

Hodgkiss (John Wiley and Sons: 1988).
Discrete-Time Signal Process ing, A. V. Oppenheim and R.W. Schafer (Prentice-Hall: 1989).
Foundations of Digital Signal Processing and Data Analysis, J. A. Cadzow (Macmillan: 1987).
Handbook of Digital Signal Processing, D. F. Elliott (Academic Press: 1987).
Introduction to Digital Signal Processing, John G. Proakis and Dimitris G. Manolakis (Macmillan: 1988).
Multirate Digital Signal Processing, R. E. Crochiere and L. R. Rabiner (Prentice-Hall: 1983).
Signal Processing Algorithms, S. Stearns and R. Davis (Prentice-Hall: 1988).
Signal Processing Handbook, C. H. Chen (Marcel Dekker: 1988).
Signal Processing: The Modern Approach, James V. Candy (McGraw-Hill: 1988).
Theory and Application of Digital Signal Processing, Lawrence R. Rabiner and Bernard Gold

(Prentice- Hall: 1975).

 xxiii

Conventions

This document uses the following notational conventions:

• Bits within register s are always listed fro m most significant bit (MSB) to least significant bi t (LSB).

• Bits within a register are formatted AA[n:0] when more than one bit is involved in a description.

For purposes of description, the bits are presented as if they are contiguous within a register.
However, this is not always the case. Refer to the programming model diagrams or to the
programmer’s sheets to see the exact location of bits within a register.

• When a bit is describe d as “set,” its value is set to 1. When a bit is described as “cleared,” its value
is set to 0.

• Memory addresses in the separate program and data memory spaces are differentiated by a
one-letter prefix. Data memory addresses are preceded by “X:” while program memory addresses
have a “P:” prefix. For example, “P:$0200” indicates a location in program memory.

• Hex values are indic ated with a do llar s ign ($) prece ding t he he x val ue, as f ollows: $FFFB i s t he X
memory address for the Interrupt Priority Register (IPR).

• Code examples are displayed in a monospaced font, as follows:

Definitions, Acronyms, and Abbreviations

The following terms appear frequently in this manual:
DSP digital signal processor

JTAG Joint Test Action Group
OnCE™ On-Chip Emulation
ALU arithmetic logic unit
AGU address generation unit
A complete list of relevant terms is included in the Glossary at the end of this manual.

BFSET #$0007,X:PCC ; Configure: line 1

; MISO0, MOSI0, SCK0 for SPI master line 2

; ~SS0 as PC3 for GPIO line 3

xxiv DSP56800 Family Manual 

 Introduction 1-1

Chapter 1

Introduction

The DSP56800 Digital Signal Processors provide low cost, low power, mid-performance computing,
combining DSP power and parallelism with MCU-like programming simplicity. The DSP56800 core is a
general-purpose central processing unit, designed for both efficient digital signal processing and a variety
of controller operations.

1.1 DSP56800 Family Architecture

The DSP56800 Family uses the DSP56800 16-bit DSP core. This core is a general-purpose central
processing unit (CPU), designed for both efficient DSP and controller operations. Its instruction-set
efficiency as a DSP is superior to other low-cost DSP architectures and has been designed for efficient,
straightforward coding of controller-type tasks.

Figure 1-1. DSP56800-Based DSP Microcontroller Chip

The general-purpose MCU-style instruction set, with its powerful addressing modes and bit-manipulation
instructions, enables a user to begin writing code immediately, without having to worry about the
complexities previously associated with DSPs. A software stack allows for unlimited interrupt and
subroutine nesting, as well as support for structured programming techniques such as parameter passing

Address

Data

JTAG I/O

GPIO

Peripherals

Memory

16-Bit DSP

CPU Core

Debug

Port

PLL

I/O Pins

External

Bus

Interface

AA0012

1-2 DSP56800 Family Manual 

Introduction

and the use of local variables. The veteran DSP programmer sees a powerful DSP instruction set with
many different arithmet ic operation s and flexible s ingle- and dual- memory moves that can occur in paral lel
with an arit hmetic operation. The general-purpose nature of the instruction set also allows for an efficient
compiler implementation.

A variety of standard peripherals can be added around the DSP56800 core (see Figure 1-1 on page 1-1)
such as serial ports, general-purpose timers, real-time and watchdog timers, different memory
configurations (RAM, ROM, or both), and general-purpose I/O (GPIO) ports.

On-Chip Emulation (OnCE™) capability is provided through a debug port conforming to the Joint Test
Action Group (JTAG) standard. This provides real-time, embedded system debugging with on-chip
emulation capability through the five-pin JTAG interface. A user can set hardware and software
breakpoints, display and change registers and memory locations, and single step or step through multiple
instructions in an application.

The DSP56800’s efficient instruction set, multiple internal buses, on-chip program and data memories,
external bus interface, standard peripherals, and industry-standard debug support make the DSP56800
Family an excellent solution for real-time embedded control tasks. It is an excellent fit for wireless or
wireline DSP applications, digital control, and controller applications in need of more processing power.

1.1.1 Core Overview

The DSP56800 core is a pr ogra mma ble 16- bi t CMOS digital signal pr ocessor that consist s o f a 16- bi t data
arithmetic logic unit (ALU), a 16-bit address generation unit (AGU), a program decoder, On-Chip
Emulation (OnCE), associat ed buses, and an instruc tion set. Figur e 1-2 on page 1-3 shows a block diagram
of the DSP56800 core. The main features of the DSP56800 core include the following:

• Processing capability of up to 35 million instructions per second (MIPS) at 70 MHz

• Requires only 2.7–3.6 V of power

• Single-instruction cycle 16-bit x 16-bit parallel multiply-accumulator

• Two 36-bit accumulators including extension bits

• Single-instruction 16-bit barrel shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Two external interrupt request pins

• Three 16-bit internal core data buses

• Three 16-bit internal address buses

• Instruction set that supports both DSP and controller functions

• Controller-style addressing modes and instructions for smaller code size

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with unlimited depth

• On-Chip Emulation for unobtrusive, processor-speed-independent debugging

• Low-power wait and stop modes

• Operating frequency down to DC

• Single power supply

DSP56800 Family Architecture

 Introduction 1-3

Figure 1-2. DSP56800 Core Block Diagram

1.1.2 Peripheral Blocks

The following peripheral blocks are available for members of the DSP56800 16-bit Family:

• Program ROM and RAM modules

• Bootstrap ROM for program RAM parts

• Data ROM and RAM modules

• Phase-locked loop (PLL) module
— 32.0 kHz and 38.4 kHz crystals accepted
— Crystal fre quencies

≥ 1 MHz accepted

— Programmable multiplication factor
— Three pins required (SXFC, V

DDS

, and GNDS)

Y1 Y0

Limiter

X0 A2 A1 A0 B2 B1 B0

MAC

and

ALU

Bus And Bit

Manipulation

Unit

OnCE

SP
R0
R1
R2

MOD.

ALU

+/-

Instr. Decoder

And

Interrupt Unit

Clock Gen.

PGDB

CGDB

PDB

XAB2

XAB1

PAB

Clock & Control

Data
ALU

Program

Controller

AGU

Program
Memory

Data Memory

Peripherals

XDB2

R3

OMR

External

Bus

Interface

PC

LA LC

SR

HWS

M01 N

AA0006

1-4 DSP56800 Family Manual 

Introduction

• 16-bit Timer Module
— Three independent 16-bit timers
— Each may be clocked from a pin, the oscillator clock, or the PLL output
— Zero to two pins required

• Computer operating properly (COP) and real-time timer module
— COP timer uses output of real-time tim er chain
— Programmable real-time timer
— Count register readable
— No pins required

• Synchronous serial interface module (SSI)
— Synchronous serial interface for hooking up to codecs
— Frame sync and gated clock modes
— Independent transmit and receive channels
— Up to 32-slot network mode available
— Three to six pins required

• Serial peripheral interface (SPI)
— Simple, synchronous, 8-bi t serial interface f or inter facing to MCUs and MCU-style perip herals
— Master and slave modes
— Four pins required

• Programmable general-purpose I/O
— Pins can be individually programmed as input or output
— Pins can be individually multiple xed bet ween per ipheral functionality and GPIO
— Pins can have interrupt capabili ty

More blocks will be defined in the future to meet customer needs.

Introduction to Digital Signal Processing

 Introduction 1-5

1.1.3 Family Members

The DSP56800 core processor is design ed as a core proc essor fo r a family of Motor ola DSPs. An example
of a chip that can be built with this core is shown in Figure 1-3 on page 1-5.

Figure 1-3. Example of Chip Built Around the DSP56800 Core

1.2 Introduction to Digital Signal Processing

DSP is the arithmetic processing of real-time signals sampled at regular intervals and digitized. Examples
of DSP processing include the following:

• Filtering

• Convolution (mixing two signals)

• Correlation (comparing two signals)

• Rectification, amplification, and transformation

Figure 1-4 on page 1-6 shows an example of analog signal processi ng. The cir cui t i n the ill ust r ati on f il te rs
a signal fro m a sensor us ing an operational amplifier and controls an actuator with th e result. Since the
ideal filter is impossible to design, the engineer must design the filter for acceptable response by
considering variat ions in temper ature, component aging, power -supply vari ation, and co mponent accurac y.
The resulting circuit typically has low noise immunity, requires adjustments, and is difficult to modify.

1Kx16
XRAM

16Kx16

ROM

Watchdog

Serial

DSP56800

16-Bit

DSP
Core

Ext. Bus
Interface

GPIO

16

16

ADR

DATA

IRQA

IRQB

& Real-time

PLL

JTAG

Timers

AA0002

1-6 DSP56800 Family Manual 

Introduction

The equivalent circuit using a DSP is shown in Figure 1-5 on page 1-7. This application requires an
analog-to-digital (A/D ) converter and digital-to-analog (D/A) converter in addition to the DSP. Even with
these additional parts, the component count can be lower usi ng a DSP due to the high i nt egr at ion available
with current components.

Figure 1-4. Analog Signal Processing

x(t)

Input

From

Sensor

yt()
xt()

---------

R

f

R

i

----- -

1

1jwRfC

f

+

----------------------------–=

y(t)

Output

To

Actuator

t

x(t)

R

i

R

f

C

f

Analog Fil ter

Frequency Characteristics

Ideal
Filter

f

f

c

Frequency

Gain

y(t)

+

–

AA0003

Actual

Filter

Introduction to Digital Signal Processing

 Introduction 1-7

Processing in this circuit begins by band limiting the input signal with an anti-alias filter, eliminating
out-of-band signals that can be aliased back into the pass band due to the sampling process. The signal is
then sampled, digitized with an A/D converter, and sent to the DSP.

The filter implement ed by th e DSP is s tr ict l y a matt er of sof twa re. The DSP can directly employ any fil t er
that can also be impl ement ed usi ng analog techniques. Al so, adaptive filter s c an b e easily put into pra ct ic e
using DSP, whereas these filters are extremely difficult to implement using analog techniques. (Similarly,
compression can also be implemented on a DSP.)

Figure 1-5. Digital Signal Processing

A

DSP Operation

Ideal
Filter

f

f

c

Frequency

Gain

FIR Filter

Finite Impulse

Response

ck() nk–()×

k0=

N

∑

A/D D/A

x(n)

y(n)

y(t)

x(t)

Analog

Filter

f

f

c

Frequency

Gain

Digital

Filter

f

f

c

Frequency

Gain

Low-Pass

Anti-Aliasing

Filter

Digital-to-Analog

Converter

Reconstruction

Low-Pass

A

A

Analog In Analog Out

Sampler and

Analog-to-Digital

Converter

AA0004

1-8 DSP56800 Family Manual 

Introduction

The DSP output is processed by a D/A converter and is low-pass filtered to remove the effects of
digitizing. In summary, the advantages of using the DSP include the following:

• Fewer components

• Stable, deterministic performance

• No filter adju stments

• Wide range of applications

• Filters with much closer tolerances

• High noise immunity

• Adaptive filters easily implemented

• Self-test can be built in

• Better power-su ppl y reje ct ion

The DSP56800 Family is not a custom IC designed for a particular application; it is designed as a
general-purpose DSP architecture to efficiently execute commonly used DSP benchmarks and controller
code in minimal time.

As shown in Figure 1-6, the key attributes of a DSP are as follows:

• Multiply/accumulate (MAC) operation

• Fetching up to two operands per instruction cycle for the MAC

• Program control to provide versatile operation

• Input/output to move data in and out of the DSP

Figure 1-6. Mapping DSP Algorithms into Hardware

X

Σ

MAC

X

Memory

Program

AA0005

FIR Filter

ck() nk–()×

k0=

N

∑

A/D D/A

x(n)

y(n)

y(t)x(t)

Summary of Features

 Introduction 1-9

The multiply-accumulation (MAC) operation is the fundamental operation used in DSP. The DSP56800
Family of processors has a dual Harvard architecture optimized for MAC operations. Figure 1-6 on
page 1-8 shows how the DSP56800 architecture matches the shape of the MAC operation. The two
operands, c( ) and x( ), are directed to a multiply operation, and the result is summed. This process is built
into the chip by allowing two separate data-memory accesses to feed a single-cycle MAC. The entire
process must occur under program control to direct the correct operands to the multiplier and save the
accumulated result as needed. Since the memory and the MAC are independent, the DSP can perform two
memory moves, a multiply and an accumulate, and two address updates in a single operation. As a result,
many DSP benchmarks execute very efficiently for a single-multiplier architecture.

1.3 Summary of Features

The high throughput o f the DSP56800 Family process ors makes th em well-sui ted for wi reless a nd wirelin e
communication, high-speed control, low-cost voice processing, numeric processing, and computer and
audio applications. The main features that contribute to this high throughput include the following:

• Speed—The DSP56800 supports most mid-performanc e DSP applic ati ons.

• Precision—The da ta paths are 16 bits wi de, providing 96 dB of d ynamic range; intermedi ate results

held in the 36-bit accumulators can range over 216 dB.

• Parallelism—Each on-chip execution uni t, memory, and perip heral operat es in depe ndentl y and i n
parallel with the othe r units throug h a sophistica ted bus system. The da ta ALU, AGU, and program
controller operate in parallel so that the following can be executed in a single instruction:

— An instruction pre-fetc h
— A 16-bit x 16-bit multiplication
— A 36-bit addition
— Two data moves
— Two address-pointer updates using one of two types of arithmetic (linear or modulo)
— Sending and receiving full-duplex data by the serial ports
— Timers continuing to count in parallel

• Flexibility—While many other DSPs need external communications circuitry to interface with

peripheral circuits (such as A/D converters, D/A converters, or host processors), the DSP56800
Family provides on-chip serial and parallel interfaces that can support various configurations of
memory and peripheral modules. The peripherals are interfaced to the DSP56800 core through a
peripheral interface bus, designed to provide a common interface to many different peripherals.

• Sophisticated debugging— Motorola’s On-Chip Emulation technology (OnCE) allows simple,
inexpensive, and speed-independent access to the internal registers for debugging. OnCE tells
application programmer s exactly what the st atus is within the regi sters, memory locatio ns, and even
the last inst ructions that were executed.

• Phase-locked loop (PLL)–based clocking—The PLL allows the chip to use almost any av ailab le
external system clock for full-speed operation while also supplying an output clock synchronized
to a synthesized internal core clock. It impro ves the synchronou s timing of the proce ssors’ external
memory port, eliminating the timing skew common on other processors.

• Invisible pipeline—The t hree-st age inst ruction pipelin e is es sential ly invi sible t o the p rogrammer ,
allowing straightforward program development in either assembly language or high-level
languages such as C or C++.

1-10 DSP56800 Family Manual 

Introduction

• Instruction set—The instruction mnemonics are MCU-like, making the transition from
programming microprocessors to programming the chip as easy as possible. New microcontroller
instructions, a ddressing modes, a nd bit-field ins tructions all ow for signifi cant decreases in program
code size. The orthogonal syntax controls the parallel execution units. The hardware DO loop
instructio n and the repeat (REP) in struction make writing straight-li ne code obsolete.

• Low power—Designed in CMOS, the DSP56800 Family inherently consumes very low power.
Two additional low power modes, stop and wait, further reduce power requirements. Wait is a
low-power mode where the DSP56800 core is shut down but the peripherals a nd interrupt control ler
continue to operate s o that an interrupt can bring the chip out of wait mode. In stop mode, ev en more
of the circuitry is shut down for the lowest power-consumption mode. There are also several
different ways to bring the chip out of stop mode.

1.4 For the Latest Information

For the latest electronic version of this document, as well as other DSP documentation (including user’s
manuals, product briefs, data sheets, and errata) please consult the inside front cover of this manual for
contact information for the following services:

• Motorola MFAX™ service

• Motorola DSP World Wide Web site

• Motorola DSP Helpline

The MFAX service and the DSP Web site maintain the most current specifications, documents, and
drawings. These two services are available on demand 24 hours a day.

 Core Architecture Overview 2-1

Chapter 2

Core Architecture Overview

The DSP56800 core architecture is a 16-bit multiple-bus processor designed for efficient real-time digital
signal processing and general purpose computing. The architecture is designed as a standard
programmable core from which various DSP integrated circuit family members can be designed with
different on-chip and off-chip memory sizes and on-chip peripheral requirements. This chapter presents
the overall core architecture and the general programming model. More detailed information on the data
ALU, AGU, program controller, and JTAG/OnCE blocks within the architecture are found in later
chapters.

2.1 Core Block Diagram

The DSP56800 core is composed of functional units that operate in parallel to increase the throughput of
the machine. The program controller, AGU, and data ALU each contain their own register set and control
logic, so each may opera te ind ependen tly and in para llel with th e other two. Likewi se, eac h funct ional unit
interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal
address and data buses. The architecture is pipelined to take advantage of the parallel units and
significantly decrease the execution time of each instruction.

For example, it is possible for the data ALU to perform a multiplication in a first instruction, for the AGU
to generate up to two addresses for a second instruction, and for the program controller to be fetching a
third instruction. In a similar manner, it is possib le for th e bit-ma nipula tion uni t to perfor m an operati on of
the third instruction described above in place of the multiplication in the data ALU.

The major components of the core are the following:

• Data ALU

• AGU

• Program controller and hardware looping unit

• Bus and bit-manipulation unit

• OnCE debug port

• Address buses

• Data buses

Figure 2-1 on page 2-2 shows a block diagram of the CPU architecture.

2-2 DSP56800 Family Manual 

Core Architecture Overview

Figure 2-1. DSP56800 Core Block Diagram

Note that Figure 2-1 illustrates two methods for connecting peripherals to the DSP56800 core: using the
Motorola-standard IP-BUS interface or via a dedicated peripheral global data bus (PGDB). When the
IP-BUS interface is u sed, peripheral registers may be memory ma pped into any data (X) memory add ress
range and are accessed with standard X-memory reads and writes. When the PGDB interface is used,
peripheral registers are mapped to the last 64 locations in X memory and are accessed with a special
memory addressing mode (see Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on
page 4-23).

The interface method used to connect to peripherals is dependent on the specific DSP56800-based device
being used. Consult your device user’s manual for more information on periphera l interfaci ng.

CGDB

PDB

PAB

XAB2

XAB1

XDB2
PGDB

Program

Memory

Data

Memory

IP-BUS

Interface

External

Bus

Interface

Instr. Decoder

and

Interrupt Unit

Program

Controller

OMR

PC

LA LC

SR

HWS

SP
R0
R1
R2

MOD.

ALU

+/-

AGU

R3

M01 N

Bus and Bit

Manipulation

Unit

OnCE

Y1 Y0

Limiter

X0 A2 A1 A0 B2 B1 B0

Data
ALU

MAC

and

ALU

Core Block Diagram

 Core Architecture Overview 2-3

2.1.1 Data Arithmetic Logic Unit (ALU)

The data arithmetic logic unit (ALU) performs all of the arithmetic and logical operations on data
operands. It consists of the following:

• Three 16-bit input registers (X0, Y0, and Y1)

• Two 32-bit accumulator registers (A and B)

• Two 4-bit accumulator extension registers (A2 and B2)

• An accumulator shifter (AS)

• One data lim iter

• One 16-bit barrel shifter

• One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit

The data ALU is capable of multiplication, multiply-accumulation (with positive or negative
accumulation), addition, subtraction, shifting, and logical operations in one instruction cycle. Arithmetic
operations are done using two’s-complement fractional or integer arithmetic. Support is also provided for
unsigned and multi-precision arithmetic.

Data ALU source operands may be 16, 32, or 36 bits and may individually originate from input registers,
memory locations, immediat e d ata , or acc umulators. ALU results are st or ed i n one of the accumulators. I n
addition, some arithmetic instructions store their 16-bit results either in one of the three data ALU input
registers or directly in memory. Arithmetic operations and shifts can have a 16-bit or a 36-bit result.
Logical operations are performed on 16-bit operands and always yield 16-bit results.

Data ALU register values can be transferred (read or write) across the core global data bus (CGDB) as
16-bit operands. The X0 register value can also be written by X memory data bus two (XDB2) as a 16-bit
operand. Refer to Chapter 3, “Data Arithmetic Logic Unit,” for a detailed description of the data ALU.

2.1.2 Address Generation Unit (AGU)

The address generation unit (AGU) performs all of the effective address calculations and address storage
necessary to address data operands in memory. The AGU operates in parallel with other chip resources to
minimize address-generation overhead. It contains two ALUs, allowing the generation of up to two 16-bit
addresses every instruction cycle: one for either X memory address bus one (XAB1) or program address
bus (PAB) and one for X memory address bus two (XAB2). The ALU can directly address 65,536
locations on the XAB1 or XAB2 and 65,536 locat ions on the PAB, totali ng 131,072 sixteen -bit data words.
It supports a complete set of addressing modes. Its arithmetic unit can perform both linear and modulo
arithmetic.

The AGU contains the following registers:

• Four address registers (R0-R3)

• A stack pointer register (SP)

• An offset register (N)

• A modifier register (M01)

• A modulo arithmetic unit

• An incrementer/decrementer unit

2-4 DSP56800 Family Manual 

Core Architecture Overview

The address registers are 16-bit registers that may contain an address or data. Each address register can
provide an address for the XAB1 and PAB a ddress bu ses. For inst ruction s that r ead two va lues fr om X data
memory, R3 provides an address for the XAB2, and R0 or R1 provides an address for the XAB1. The
modifier and offset registers are 16-bit registers that control updating of the address registers. The offset
register can als o be used to store 16-bi t dat a. AGU reg is ter s ma y b e r ea d or written by the CGDB a s 1 6-bit
operands. R efer to Chapter 4 , “Address Generation Unit,” for a detailed description of the AGU.

2.1.3 Program Controller and Hardware Looping Unit

The program controller performs the following:

• Instruction prefe tch

• Instruction decoding

• Hardware loop control

• Interrupt (exception) processing

Instruction execution is carried out in other core units such as the data ALU, AGU, or bit-manipulation
unit. The program controller consists of the following:

• A program counter unit

• Instruction latch and decoder

• Hardware looping cont rol logic

• Interrupt c ontrol logic

• Status and control registers

Located within the program controller are the following:

• Four user-accessible registers:
— Loop address register (LA)
— Loop count register (LC)
— Status register (SR)
— Operating mode register (OMR)

• A program counter (PC)

• A hardware stack (HWS)

In addition to the tasks listed above, the program controller also controls the memory map and operating
mode. The operating mode and memory map are programmable via the OMR, and are established after
reset by external interface pins.

The HWS is a separate internal last-i n-first -out (LIF O) buffe r of two 16-b it words th at sto res the ad dress of
the first instruction in a hardware DO loop. When a new hardware loop is begun by executing the DO
instruction, the address of the first instruction in the loop is stored (pushed) on the “top” location of the
HWS, and the LF bit in the SR is set. The previous value of the loop flag (LF) bit is copied to the OMR’s
NL bit. When an ENDDO instruction is encountered or a hardware loop terminates naturally, the 16-bit
address in the “top” location of the HWS is discarded, and the LF bit is updated with the value in the
OMR’s nested looping (NL) bit.

The program controller is described in detail in Chapter 5, “Program Controller.” For more details on
program looping, refer to Section 5.3, “Program Looping,” on page 5-14 and Section 8.6, “Loops,” on
page 8-20. For information on reset and interrupts, refer to Chapter 7, “Interrupts and the Processing
States.”

Core Block Diagram

 Core Architecture Overview 2-5

2.1.4 Bus and Bit-Manipulation Unit

Transfers between internal buses are accomplished in the bus unit. The bus unit is similar to a switch
matrix and can connect any two of the three internal data buses together without introducing delays. This
allows data to be moved from program to data memory, for example. The bus unit is also used to transfer
data to the PGDB on those devices that use it to connect to on-chip peripherals.

The bit-manipulation unit performs bit-field manipulations on X (data) memory words, peripheral
registers, and all reg is te rs wi thi n th e DSP56800 core. It is capable of test i ng, se tting, clearing, or inver ting
any bits specified in a 16-bit mask. For branch-on-bit-field instructions, this unit tests bits on the upper or
lower byte of a 16-bit word (that is, the mask can only test up to 8 bits at a time).

2.1.5 On-Chip Emulation (OnCE) Unit

The On-Chip Emulation (OnCE) unit allows the user to interact in a debug environment with the
DSP56800 core and its peripherals non-intrusively. Its capabilities include examining registers, on-chip
peripheral registers or memory, setting breakpoints on program or data memory, and stepping or tracing
instructions. I t pr ovid es simple, inexpensive, and speed-inde pend ent ac cess to the internal DSP56800 core
by interacting with a us er-inte rface pr ogram runn ing on a h ost workst ation f or sop histica ted debugg ing and
economical system development.

Dedicated pins through the JTAG port a ll ow t he user access to the DSP in a target sy st em, r et ai ning debug
control without sacrificing other user-accessible on-chip resources. This technique eliminates the costly
cabling and the access to processor pins required by traditional emulator systems. Refer to Chapter 9,
“JTAG and O n-Chip Emulation (OnCE™),” for a detailed description of the JTAG/OnCE port. Consult
your development system’s documentation for information on debugging using the JTAG/OnCE port
interface.

2.1.6 Address Buses

Addresses are provided to the internal X data memory on two unidirectional 16-bit buses, X memory
address bus one (XAB1) and X memory address bus two (XAB2). Program memory addresses are
provided on the 16-bit program address bus (PAB). Note that XAB1 can provide addresses for accessing
both internal and external memory, whereas XAB2 can only provide addresses for accessing internal
memory.

2.1.7 Data Buses

Inside the c hip, data is transferred using the following:

• Bidirectional 16-bit buses:
— Core global data bus (CGDB)
— Program data bus (PDB)
— Peripheral data bus (PGDB)

1

• One unidirectional 16-bit bus: X memory data bus two (XDB2)

Data transfer between the data ALU and the X data memory uses the CGDB when one memory access is
performed. When two simultaneous memory reads are performed, the transfers use the CGDB and the
XDB2. All other data transfers occur using the CGDB, except transfers to and from peripherals on

1. Implemented on DSP56800 family devices that do not use the IP-BUS interface for peripherals.

2-6 DSP56800 Family Manual 

Core Architecture Overview

DSP56800-based devices that implement the PGDB peripheral data bus. Instruction word fetches occur
simultaneously over the PDB. The bus structure supports general register-to-register moves,
register-to-memo ry moves , an d memory- to-re giste r moves , an d can t ransf er up to t hree 1 6-bi t wor ds in the
same instruction cy cle. Tr ansfe rs bet ween buse s are a ccomp lishe d in the bus and bit -manipu lati on unit . As
a general rule, when any register less than 16 bits wide is read, the unused bits are read as zeros. Reserved
and unused bits should always be written with ze ros to insure future compatibility.

2.2 Memory Architecture

The DSP56800 has a dual Harvard memory architecture, with separate program and data memory spaces.
Each address space s uppo rt s up t o 2

16

(65,536) memory words. Dedi cat ed a ddr ess and data buses for ea ch
address space allow for simultaneous accesses to both program memory and data memory. There is also a
support for a second rea d-only data path to dat a memory. In DSP56800 Fa mily devi ces that i mplement this
second bus, it is possible to initiate two simultaneous data re ad operation s, allowing for a total of three
parallel memory accesses.

Figure 2-2. DSP56800 Memory Spaces

Locations $0 through $007F in the program memory space are available for reset and interrupt vectors.
Peripheral registers are located in the data memory address space as memory-mapped registers. This
peripheral space can be located anywhere in the data address space, although the address range
$FFC0–$FFFF is frequently used because an addressing mode optimized for this region provides faster
access; however, the location of the peripheral space is dependent on the specific system implementation
of the DSP56800 core. See Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on page 4-23
for more information.

$0

$FFFF

0

64K or 2

16

$FFC0 (64K - 64)

Optimized for

Peripherals

X Data

Memory

Space

$0

$FFFF

0

64K or 2

16

Program

Memory

Space

Interrupt

Vectors

$7F 127

Blocks Outside the DSP56800 Core

 Core Architecture Overview 2-7

2.3 Blocks Outside the DSP56800 Core

The following blocks are optionally found on DSP56800-based DSP chips and are considered peripheral
and memory blocks, not part of the DSP56800 cor e. Thes e and ot her block s are descr ib ed in gr eater detail
in the appropriate chip-specific user’s manual. Figure 2-3 shows an example DSP56800-based device.
Note that this device uses the Motorola IP-BUS interface to connect to peripherals. Other chips may use
the PGDB peripheral bus.

Figure 2-3. Sample DSP56800-Family Chip Block Diagram

2.3.1 External Data Memory

External data memory (dat a RAM, data ROM, or both) can be added around the core on a chip. Addre sse s
are received from the XAB1 and XAB2. Data transfers occur on the CGDB and XDB2. One read, one
write, or two reads can be performed during one instruction cycle using the internal data memory.
Depending upon the particular on-chip peripherals found on a device, some portion of the data address
space may be reserved for peripheral registers, and not be accessible as external data memory. A total of
65,536 memory locations can be addressed.

Program
RAM/ROM
Expansion

XAB1
XAB2
PAB

PDB

CGDB

IRQB

RESET

16-Bit Data Bus

IRQA

Peripheral

Modules

Expansion

Area

DSP

16-Bit

Core

Program

Data ALU

16 x 16 + 36

→

36-Bit MAC

Three 16-Bit Input Registers

Two 36-Bit Accumulators

JTAG/

On-Chip

Address

Generation

Unit

Internal

Data Bus

Switch

PLL

XDB2

Data

RAM/ROM

Expansion

Clock

Generator

Controller

IP-BUS

Bridge

OnCE

TM

2-8 DSP56800 Family Manual 

Core Architecture Overview

2.3.2 Program Memory

Program memory (program RAM, program ROM, or both) can be added around the core on a chip.
Addresses are received from the PAB and data transfers occur on the PDB. The first 128 locations of the
program memory are availabl e for inter rupt vectors, al though it is not necess ary to use all 128 loca tions for
interrupt vectors. Some can be used for the user program if desired. The number of locations required for
an application depen ds on what perip herals on th e chip are used by an appli cation and th e locatio ns of their
corresponding interrupt vectors. The program memory may be expanded off chip, and up to 65,536
locations can be addressed.

2.3.3 Bootstrap Memory

A program bootstrap ROM is usually found on chips that have on-chip program RAM instead of ROM.
The bootstrap ROM is used for initially loading application code into the on-chip program RAM so it can
be run from there. Refer to Section 5.1.9.1, “Operating Mode Bits ( MB and MA)—Bits 1–0,” on page 5-10
and to the user’s manual of the particular DSP chip for a description of the different bootstrapping modes.

2.3.4 IP-BUS Bridge

Some devices based on the DSP56800 architecture connect to on-chip peripherals using the
Motorola-standard IP-BUS interface. These devices contain an IP-BUS bridge unit, which allows
peripherals to be accessed using the CGDB data bus and XAB1 address bus. Peripheral registers are
memory-mapped into the data address space. Consult the appropriate DSP56800-based device User’s
Manual for more information on peripheral interfacing for a particular chip.

2.3.5 Phase Lock Loop (PLL)

The phase lock loop ( PLL) all ows the DSP chip to use an ext er nal clock different from the internal system
clock, while optionally supplying an output clock synchronized to a synthesized internal clock. This PLL
allows full-speed operation using an external clock running at a different speed. The PLL performs
frequency multiplication, skew elimination, and reduces overall system power by reducing the frequency
on the input reference clock.

2.4 DSP56800 Core Programming Model

The registers in the DSP 56800 core t hat are con sidered pa rt of the DSP56800 core pr ogramming model are
shown in Figure 2-4 on page 2-9. There may also be other important registers that are not included in the
DSP56800 core, but mapped into t he data addre ss space. Th ese includ e registers f or peripher al device s and
other functions that are not bound into the core.

DSP56800 Core Programming Model

 Core Architecture Overview 2-9

Figure 2-4. DSP56800 Core Programming Model

N M01

Program Controller Unit

Hardware Stack (HWS)

Data ALU Input Registers

Accumulator Registers

Data Arithmetic Logic Unit

SP

R3

R2

R1

R0

MR CCR OMR

Pointer

Registers

Offset

Register

Modifier

Register

Program

Counter

Status

Register (SR)

Operating Mode

Register

LA

LC

Loop Address

Loop Counter

Y

A

B

X0 Y0Y1

A0A1A2

B0B1B2

PC

31 16 15 0

15 0 15 015 0

31 16 15 035 32

15 015 03

31 16 15 035 32

15 015 0

15 0 15 0 15 0

15 0 15 0 15 087

15 015 0

Address Generation Unit

AA0007

12 0

0

30

2-10 DSP56800 Family Manual 

Core Architecture Overview

 Data Arithmetic Logic Unit 3-1

Chapter 3

Data Arithmetic Logic Unit

This chapter des cri bes the architectu re and the operation of the data arithmetic logic unit (ALU), th e block
where the multiplication, logical operations, and arithmetic operations are performed. (Addition can also
be performed in the address ge nerat ion unit , and the bi t-mani pulat ion unit can perf orm lo gical operati ons.)
The data ALU contains the following:

• Three 16-bit input registers (X0, Y0, and Y1)

• Two 32-bit accumulator registers (A and B)

• Two 4-bit accumulator extension registers (A2 and B2)

• An accumulator shifter (AS)

• One data lim iter

• One 16-bit barrel shifter

• One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit

Multiple buses in the data ALU perform complex arithmetic operations (such as a multiply-accumulate
operations) in parallel with up to two memory transfers. A discussion of fractional and integer data
representations; signed, unsigned, and multi-precision arithmetic; condition code generation; and the
rounding modes used in the data ALU are also described in this section.

The data ALU can perform the following operations in a single instruction cycle:

• Multiplication (with or without rounding)

• Multiplication with inverted product (with or without rounding)

• Multiplication and accumulation (with or without rounding)

• Multiplication and accumulation with inverted product (with or without rounding)

• Addition and subtraction

• Compares

• Increments and decrements

• Logical operations (AND, OR, and EOR)

• One’s-complement

• Two’s-complement (negation )

• Arithmetic and logical shi ft s

• Rotates

• Multi-bit shifts on 16-bit values

• Rounding

• Absolute value

3-2 DSP56800 Family Manual 

Data Arithmetic Logic Unit

• Division iteration

• Normalization iteration

• Conditional register moves (Tcc)

• Saturation (limiting)

3.1 Overview and Architecture

The major components of the data ALU are the following:

• Three 16-bit input registers (X0, Y0, and Y1)

• Two 32-bit accumulator registers (A and B)

• Two 4-bit accumulator extension registers (A2 and B2)

• An accumulator shifter (AS)

• One data lim iter

• One 16-bit barrel shifter

• One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit

A block diagram of the data ALU unit is shown in Figure 3-1 on page 3-3, and its corresponding
programming model is shown in Figure 3-2 on page 3-4. In the programming model, accumulator “A”
refers to the entire 36-bit accumulator register , whereas “A2,” “A1,” and “A0” refer to the directly
accessible extension, most significant portions, and least significant portions of the 36-bit accumulator,
respectively. Instructions can access the register as a whole or by these individual portions (see
Section 3.1.2, “Data ALU Accumulator Registers,” on page 3-4 and Section 3.2, “Accessing the
Accumulator Registers,” on page 3-7). The blocks and registers within the data ALU are explained in the
following sections.

Overview and Architecture

 Data Arithmetic Logic Unit 3-3

Figure 3-1. Data ALU Block Diagram

XDB2

Condition Codes

to Status Register

Arith/Logical

Shifter

x

Optional

Invert

SHIFTER/MUX

A0A2 A1

+

B0B2 B1

Condition Code

Generation

CGDB

36-bit Accumulator Shifter

Rounding
Constant

Y1
Y0
X0

MAC Output Limiter

EXT:MSP:LSP

LIMITER

OMR’s SA Bit

OMR’s CC Bit

3-4 DSP56800 Family Manual 

Data Arithmetic Logic Unit

3.1.1 Data ALU Input Registers (X0, Y1, and Y0)

The data ALU registers (X0, Y1, and Y0) are 16-bit registers that serve as inputs for the data ALU. Each
register may be read or writt en by t he CGDB as a wor d operan d. They may b e trea te d as thr ee ind ependent
16-bit registers, or as one 16-bit register and one 32-bit register. Y1 and Y0 can be concatenated to form
the 32-bit register Y, with Y1 being the most significant word and Y0 being the least significant word.
Figure 3-2 shows this arrangement.

These data ALU input registers are used as source operands for most data ALU operations and allow new
operands to be loaded from the memory for the next i nst ruc ti on whi le t he register contents are used by the
current instruction. X0 may also be written by the XDB2 during the dual read instruction. Certain
arithmetic operations also allow these registers to be specified as destinations.

3.1.2 Data ALU Accumulator Registers

The two 36-bit data ALU accumulat or register s can b e accesse d either as a 36-bi t register (A or B) or as th e
following, individual portions of the register:

• 4-bit extension register (A2 or B2)

• 16-bit MSP (A1 or B1)

• 16-bit LSP (A0 or B0)

The three individual portions make up the entire accumulator register, as shown in Figure 3-2.
These two techniques for accessing the accumulator registers provide important flexibility for both DSP

algorithms and gen eral-pur pose comput ing tasks . Access ing these regist ers as en tire acc umulators (A or B)
is particularly useful for DSP tasks, because this preserves the full precision of multiplication and other
ALU operations. Data limiting and saturation are also possible using the full registers, in cases where the
final result of a computation that has overflowed is moved (see Section 3.4.1, “Data Limiter,” on page
3-26).

Figure 3-2. Data ALU Programming Model

X0

Data ALU Input Registers

Accumulator Registers

Data Arithmetic Logic Unit

Y

A

B

Y0Y1

A0A1A2

B0B1B2

AA0035

15 0

15 0

31 16 15 0

15 0

31 16 15 035 32

15 0 15 030
31 16 15 035 32

15 0 15 030

Overview and Architecture

 Data Arithmetic Logic Unit 3-5

Accessing an accu mulator t hrough it s indivi dual por tions (A2 , A1, A0, B2, B1, or B0) i s useful for sys tems
and control programming. When accumulators are manipulated using their constituent components,
saturation and limiting are disabled. This allows for microcontroller-like 16-bit integer processing for
non-DSP purposes.

Section 3.2, “Accessing the Accumulator Registers,” provides a complete discussion of the wa ys i n whi ch
the accumulators can be employed. A description of the data limiting and saturation features of the data
ALU is provided in Section 3.4, “Saturation and Data Limiting.”

3.1.3 Multiply-Accumulator (MAC) and Logic Unit

The multiply-accum ul at or (MAC) and logic unit is the ma in arithmetic processing unit of the DSP. This is
the block that performs all multiplication, addition, subtraction, logical, and other arithmetic operations
except shifting. It accepts up to three input operands and outputs one 36-bit result of the form
EXT:MSP:LSP (extension: most s ignif icant prod uct:l east signi fica nt pr oduct) . Arit hmetic opera tions in t he
MAC unit occur indepe ndentl y and i n para llel with memor y acce sses o n the CGDB, XDB2, and PDB. The
data ALU registers provide pipelining for both data ALU inputs and outputs. An input register may be
written by memory in the same instruction where it is used as the source for a data ALU operation. The
inputs of the MAC and logic unit can come from the X and Y registers (X0, Y1, Y0), the accumulators
(A1, B1, A, B), and also directly from memory for common instructions such as ADD and SUB.

The multiplier executes 16-bit x 16-bit parallel signed/unsigned fractional and 16-bit x 16-bit parallel
signed integer multiplications. The 32-bit product is added to the 36-bit contents either of the A or B
accumulator or of the 16-bit contents of the X0, Y0, or Y1 registers and then stored in the same register.
This multiply-accumulate is a single cycle operation (no pipeline). For integer multiplication, the 16 LSBs
of the product are stored in the MSP of th e accumula tor; the ext ensi on regis ter is fille d with sig n extensi on
and the LSP of the accumulator remains unchanged.

If a multiply without accumulation is specified by a MPY or MPYR instruction, the unit clears the
accumulator and then adds the contents to the product. The results of all arithmetic instructions are valid
(sign extended) 36-bit operands in the form EXT:MSP:LSP (A2:A1:A0 or B2:B1:B0).

When a 36-bit result is to be stored as a 16-bit operand, the LSP can simply be truncated, or it can be
rounded into the MSP. The rounding performed is either the convergent rounding (round to the nearest
even) or two’s-complement rounding. The type of rounding is specified by the rounding bit in the
operating mode register. See Section 3.5, “Rounding,” for a more detailed discussion of rounding.

The logic unit performs the logical operations AND, OR, EOR, and NOT on data ALU registers. It is 16
bits wide and operates on data in the MSP of the accumulator. The least significant and EXT portions of
the accumulator are not affected. Logical operations can also be performed in the bit-manipulation unit.
The bit-manipulation unit is used when performing logical operations with immediate values and can be
performed on any register or memory location.

3.1.4 Barrel Shifter

The 16-bit barrel shif ter per forms s ingle- cycle , 0- t o 15-bit arit hmetic o r logic al shi fts of 16-bit data. Sin ce
both the amount to be shifted as well as the value to shift come from registers, it is possible to shift data by
a variable amount. See Fig ure 3-3 on page 3-6. It is also possible to us e thi s unit to right shi ft 32-b it values
using the ASRAC and LSRAC instructions, as demonstrated in Section 8.2, “16- and 32-Bit Shift
Operations,” on page 8-8.

3-6 DSP56800 Family Manual 

Data Arithmetic Logic Unit

Figure 3-3. Right and Left Shifts Through the Multi-Bit Shifting Unit

After shifting, the extension register is always loaded with zero extension for logical shifts or sign
extension for arithmetic shifts. For right shifts, the LSP is set to zero except for the ASRAC an d LSRAC
instructions, whe re t he l ower bi ts are shifted in to the LSP. For left shifts , t he upper bits are not shifted into
the extension register, and the LSP is always set to zero.

3.1.5 Accumulator Shifter

The accumulator shifter is an asynchronous parallel shifter with a 36-bit input and a 36-bit output. The
operations performed by this unit are as follows:

• No shift performed—ADD, SUB, MAC, and so on

• 1-bit left shift—ASL, LSL, ROL

• 1-bit right shift—ASR, LSR, ROR

• Force to zero—MPY, IMPY(16)

The output of the shifter goes directly to the MAC unit as an input.

3.1.6 Data Limiter and MAC Output Limiter

The data ALU contains two units that implement optional saturation of mathematical results, the Data
Limiter and the MAC Ou tput Limiter. The Data Limiter satur ates values when data is moved out of an
accumulator with a move instruction or parallel move. The MAC Output Limiter saturates the output of the
data ALU’s MAC unit.

Section 3.4, “Saturation and Data Limiting,” provides an in-depth discussion of saturation and li mit in g, as
well as a description of the operation of the two limiter units.

FAAAF

EXT MSP

0000

LSP

A

Multi-Bit

Shifting Unit

16 4

AAA0F

EXT MSP

0000

LSP

A

Multi-Bit

Shifting Unit

16 4

$AAAA $4 $AAAA $4

Example: Right Shifting (ASRR) Example: Left Shifting (ASLL)

35 32 31 16 15 0 35 32 31 16 15 0

AA0039

Accessing the Accumulator Registers

 Data Arithmetic Logic Unit 3-7

3.2 Accessing the Accumulator R egisters

An accumulator register can be accessed in two different ways:

• as an entire register (F)

• by the individual register portion (F2, F1, or F0)

The ability to access the accumulator registers in both ways provides important flexibility, allowing for
powerful DSP algorithms as well as general-purpose computing tasks.

Accessing an enti re accumu lator re gister (A or B) is par ticular ly usef ul for DSP tasks, s ince it preserve s the
complete 36-bit register—and thus the entire precision of a multiplication or other ALU operation. It also
provides limiting (or saturation) capability in cases when storing a result of a computation that would
overflow the destination size. See Section 3.4, “Saturation and Data Limiting.”

Accessing an accumulator through its individual portions (F2, F1, or F0) is useful for systems and control
programming. For example, if a DSP algorithm is in progress and an interrupt is received, it is usually
necessary to save every accumulator used by the interrupt service routine. Since an interrupt can occur at
any step of the DSP task (that is, right in the middle of a DSP algorithm), it is important that no saturation
takes place. Thus, an interrupt service routine can store the individual accumulator portions on the stack,
effectively saving the entire 36-bit value without any limiting. Upon completion of the interrupt routine,
the contents of the accumulator can be exactly restored from the stack.

The DSP56800 instruction set transparently supports both methods of access. An entire accumulator may
be accessed simply through th e speci ficati on of the f ull-re gister n ame (A or B), whi le porti ons are a ccessed
through the use of their respective names (A0, B1, and so on).

Table 3-1 provides a summary of the various access methods. These are described in more detail in
Section 3.2.1, “Accessing an Accumulator by Its Individual Portions,” and Section 3.2.2, “Accessing an
Entire Accumulator.”

Table 3-1. Accessing the Accumulator Registers

Register Read of an Accumulator Register Write to an Accumulator Register

A
B

For a MOVE instruction:

If the extension bits are not in use for the
accumulator to be read, then the 16-bit con­tents of the F1 portion of the accumulator are
read onto the CGDB bus.
If the extension bits are in use, then a 16-bit
“limited” value is instead read onto th e CGD B.
See Section 3.4.1, “Data Limiter.”

When used in an arithmetic operation:

All 36 bits are sent to the MAC unit without
limiting.

For a MOVE instruction:

The 16 bits of the CGDB bus are written into
the 16-bit F1 portion of the register.
The extension portion of the same accumula­tor, F2, is filled with sign extension. The F0
portion is set to zero.

A2
B2

For a MOVE instruction:

The 4-bit register is read onto the 4 LSBs of
the CGDB bus.
The upper 12 bits of the bus are sign
extended.
See Figure 3-5 on page 3-9.

For a MOVE instruction:

The 4 LSBs of the CGDB are written into the
4-bit register; the upper 12 bits are ignored.
The corresponding F1 and F0 portions are no t
modified.
See Figure 3-4 on page 3-8.

3-8 DSP56800 Family Manual 

Data Arithmetic Logic Unit

In all cases in Table 3-1 where a MOVE operation is specified, it is understood that the function is
identical for parallel moves and bit-field operations.

3.2.1 Accessing an Accumulator by Its Individual Portions

The instruction set provides instructions for loading and storing one of the portions of an accumulator
register without affec ting the other two port ions. When an instr uctions uses the F1 or F0 notat ion instead of
F, the instruction only operates on the 16-bit portion specified without modifying the other two portions.
When an instruction specifies F2, then the instruction operates only on the 4-bit accumulator extension
register without modifying the F1 or F0 portions of the accumulator. Refer to Table 3-1 for a summary of
accessing the accumulator registers.

Data limiting, as outlined in Section 3.4, “Saturation and Data Limiting,” is enabled only when an entire
accumulator is being stored to memory. When only a portion of an accumulator is being stored (by using
an instruction which specifies F2, F1, or F0), limiting through the data limiter does not occur.

When F2 is written, the register receives the low-order portion of the word; the high-order portion is not
used. See Figure 3-4.

Figure 3-4. Writing the Accumulator Extension Registers (F2)

A1
B1

For a MOVE instruction:

The 16-bit F1 portion is read onto the CGDB
bus.

When used in an arithmetic operation:

The F1 register is used as a 16-bit source
operand fo r an arithmetic operation.

F1 can be used in the following:
MOVE
Parallel Move
Several different arithmetic

For a MOVE instruction:

The contents of the CGD B bus are written into
the 16-bit F1 register.
The corresponding F2 and F0 portions are no t
modified.

A0
B0

For a MOVE instruction:

The 16-bit F0 register is read onto the CGDB
bus.

For a MOVE instruction:

The contents of the CGD B bus are written into
the 16-bit F0 register.
The corresponding F2 and F1 portions are no t
modified.

Table 3-1. Accessing the Accumulator Registers (Continued)

Register Read of an Accumulator Register Write to an Accumulator Register

CGDB Bus Contents

Not Used

LSB of

Word

Register F2 Used

as a Destination

15 4 3 0

F2No Bits Present

Register F2

15 4 3 0

Accessing the Accumulator Registers

 Data Arithmetic Logic Unit 3-9

When F2 is read, the register contents occupy the low-order portion (bits 3–0) of the word; the high-order
portion (bits 15–4) is sign extended. See Figure 3-5.

Figure 3-6 shows the result of wr itin g value s to ea ch port ion of the a ccumu lator . Note t hat onl y the p ortio n
specified in the instruction is modified; the other two portions remain unchanged.

See Section 3.2, “Accessing the Accumulator Registers,” for a discussion of when it is appropriate to
access an accumulator by its individual portions and when it is appropriate to access it as an entire
accumulator.

Figure 3-5. Reading the Accumulator Extension Registers (F2)

Figure 3-6. Writing the Accumulator by Portions

F2

CGDB Bus Contents

Register F2

Used as a Source

Sign Extension

of F2

Contents

of F2

No Bits Present

Register F2

LSB Of

Word

15 4 3 0

15 4 3 0

Before Execution

XXXXX

A2 A1

XXXX

A0

A

After Execution

XXXXD

A2 A1

XXXX

A0

A

35 32 31 16 15 0 35 32 31 16 15 0

Writing the F2 Portion Example: MOVE #$ABCD,A2

Before Execution

XXXXX

A2 A1

XXXX

A0

A

After Execution

1234X

A2 A1

XXXX

A0

A

35 32 31 16 15 0 35 32 31 16 15 0

Writing the F1 Portion Example: MOVE #$1234,A1

Before Execution

XXXXX

A2 A1

XXXX

A0

A

After Execution

XXXXX

A2 A1

A987

A0

A

35 32 31 16 15 0 35 32 31 16 15 0

Writing the F0 Portion Example: MOVE #$A987,A0

3-10 DSP56800 Family Manual 

Data Arithmetic Logic Unit

3.2.2 Accessing an Entire Accumulator

3.2.2.1 Accessing for Data ALU Operations

The complete accumulator is accessed to provide a source, a destination, or both for an ALU or
multiplication operation in the data ALU. In this case, the accumulator is written as an entire 36-bit
accumulator (F), not as an individual register (F2, F1, or F0). The accumulator registers receive the
EXT:MSP:LSP of the multiply-accumulator unit output when used as a destination and supply a source
accumulator of the same form. Most data ALU operations specify the 36-bit accumulator registers as
source operands, destination operands, or both.

3.2.2.2 Writing an Accumulator with a Small Operand

Automatic sign extension of the 36-bit accumulators is provided when the accumulator is written with a
smaller size operand. This can occur when writing F from the CGDB (MOVE instruction) or with the
results of certain data ALU operations (for example, ADD, SUB, or TFR from a 16-bit register to a 36-bit
accumulator). If a word operand is to be written to an accumu lator register (F), the F1 portion of the
accumulator is written with the word operand, the LSP is zeroed, and the EXT portion receives sign
extension. This is also the case for a MOVE instruction that moves one accumulator to another, but is not
the case for a TFR instru ction that mo ves one entire accumula tor to another. No sign extension is
performed if an individual 16-bit register is written (F1 or F0).

NOTE:

A read of the F1 register in a MOVE instruction is identical to a read of the
F accumulator for the case where the extension bits of that accumulator
only contain sign-extension information. In this case there is no need for
saturation or limiting, so reading the F accumulator produces the same
result as reading the F1 register.

3.2.2.3 Extension Registers as Protection Against Overflow

The F2 extension registers offer protection against 32-bit overflow. When the result of an accumulation
crosses the MSB of MSP (bit 31 of F), the ext ens ion bit of the status r egi st er (E) is set. Up to 15 ove rf lows
or underflows are possible using these extension bits, after which the sign is lost beyond the MSB of the
extension register. When this occurs, the overflow bit (V) in the status register is set. Having an extension
register allows overflow during intermediate calculations without losing important information. This is
particularly useful during execution of DSP algorithms, when intermediate calculations (but not the final
result that is written to memory or to a peripheral) may some times overflow.

The logic detectio n of “exten sio n regis ter i n use” i s also u sed to de termin e when to satu rate t he valu e of an
accumulator when it is b eing read onto the CGDB or transferred to any da ta ALU regis ter. If saturation
occurs, the content of the original accumulator is not affected (except if the same accumulator is specified
as both source a nd des tin atio n); on ly th e v alue trans ferre d over the CGDB is limit ed t o a fu ll -scal e posi tive
or negative 16-bit value ($7FFF or $8000).

When limiting occurs, a flag is set and latched in the status register (L). The limiting block is explained in
more detail in Section 3.4.1, “Data Limiter.”

NOTE:

Limiting will be performed only when the entire 36-bit accumulator
register (F) is specified as the source for a parallel data move or a register
transfer. It is not performed when F2, F1 or F0 is specified.

Accessing the Accumulator Registers

 Data Arithmetic Logic Unit 3-11

3.2.2.4 Examples of Writing the Entire Accumulator

Figure 3-7 shows the result of writing a 16-bit signed value to an entire accumulator. Note that all three
portions of the accumulator are modified. The LSP (B0) is set to zero, and the extension portion (B2) is
appropriately sign extended.

Figure 3-7. Writing the Accumulator as a Whole

Successfully using the DSP56800 Family requires a f ul l u nder standing of the methods a nd i mp li cat io ns of
the various accumulator-register access methods. The architecture of the accumulator registers offers a
great deal of flexibility and power, but it is necessary to completely understand the access mechanisms
involved to fully exploit this power.

3.2.3 General Integer Processing

General integer and control processing typically involves manipulating 16- and 32-bit integer quantities.
Rarely will such code use a full 36-bit accumulator such as that implemented by the DSP56800 Family.
The architecture of the DSP56800 supports the manipulation of 16-bit integer quantities using the
accumulators, but care must be taken when performing such manipulation.

3.2.3.1 Writing Integer Data to an Accumulator

When loading an acc umulator , it i s most de sirab le for the 36 b its of the ac cumulat or t o corr ectl y refl ect th e
16-bit data. To this end, it is recommended that all accumulator loads of 16-bit data clear the least
significant portion of the accumulator and also sign extend the extension portion. This can be
accomplished through specifying the full accumulator register as the destination of the move, as shown in
Example 3-1.

Example 3-1. Loading an Accumulator with a Word for Integer Processing

MOVE X:(R0),A ; A2 receives sign extension

; A1 receives the 16-bit dat a
; A0 receives the value $000 0

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

12340

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Writing a Positive Value into 36-Bit Accumulator Example: MOVE #$1234,B

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

A987F

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Writing a Negative Value into 36-Bit Accumulator Example: MOVE #$A987,B

3-12 DSP56800 Family Manual 

Data Arithmetic Logic Unit

Loading a 16 - bit integer value into th e A1 portion of the register is generally discouraged. In almost all
cases, it is preferable to follow Example 3-1 on page 3-11. One notable exception is when 36-bit
accumulator values must be stored temporaril y. See Section 3.2.5, “Saving and Restor ing Accumulators,”
for more details.

3.2.3.2 Reading Integer Data from an Accumulat or

Integer and control processing algorithms typically involve the manipulation of 16-bit quantities that
would be adversely affected by saturation or limiting. When such integer calculations are performed, it is
often desirable not to have over flow protection when results are stor ed to memory. To ens ure that the da ta
ALU’s data limiter is not active when an accumulator is being read, it is necessary to store not the full
accumulator, but just the MSP (A1 portion). See Example 3-2.

Example 3-2. Reading a Word from an Accumulator for Integer Processing

MOVE A1,X:Variable_1 ; Saturation is disable d

Note that with the use of the A1 register instead of the A register, saturation is disabled. The value in A1 is
written “as is” to memory.

3.2.4 Using 16-Bit Results of DSP Algorithms

A DSP Algorithm may use the full 36-bit precision of an accumulator while performing DSP calculations
such as digital filtering or matrix multiplications. Upon completion of the algorithm, however, sometimes
the result of the calculation must be saved in a 16-bit memory location or must be written to a 16-bit D/A
converter. Since DSP algorithms process digital signals, it is important that when the 36-bit accumulator
value is convert ed t o a 16- bit value, saturatio n i s en abl ed so signals that ove rf low 16 bits are appropri ately
clipped to the maximum positive or negative value. See Example 3-3.

Example 3-3. Correctly Reading a Word from an Accumulator to a D/A

MOVE A,X:D_to_A_data ; Saturation is enabled

Note the use of the A accumulator instead of the A1 register. Using the A accumulator enables saturation.

3.2.5 Saving and Restoring Accumulators

Interrupt service routines offer one example of a time when it is critical that an accumulator be saved and
restored without being altered in any way. Since an interrupt can occur at any time, the exact usage of an
accumulator at that instant is unknown, so it cannot be altered by the interrupt service routine without
adversely affectin g any calcul ation that may have bee n in progres s. In order f or an accumula tor to be sav ed
and restored correctly, it must be done with limiting disabled. This is accomplished through sequentially
saving and restoring the individual parts of the register, and not the whole register at once. See
Example 3-4 on page 3-13.

Accessing the Accumulator Registers

 Data Arithmetic Logic Unit 3-13

Example 3-4. Correct Saving and Restoring of an Accumulator—Wo rd Acce sse s

; Saving the A Accumulator t o the Stack
LEA (SP)+ ; Point to first empty locat ion
MOVE A2,X:(SP)+ ; Save extension register
MOVE A1,X:(SP)+ ; Save F1 register
MOVE A0,X:(SP) ; Save F0 register

; Restoring the A Accumulator from the Stack
MOVE X:(SP)-,A0 ; Restore F0 register
MOVE X:(SP)-,A1 ; Restore F1 register
MOVE X:(SP)-,A2 ; Restore extension register

It is important that inter rupt service routines do not use the MOV E A,X:(SP)+ instructio n when saving to
the stack. This instruction operates with saturation enabled, and may inadvertently store the value $7FFF
or $8000 onto the stac k, acco rding to th e ru les employe d by t he Data Limi ter. This could have ca ta strop hic
effects on any DSP calculation that was in progress.

3.2.6 Bit-Field Operations on Integers in Accumulators

When bit-manipulation operations on accumulator registers are performed, as is done for integer
processing, care must be taken. The bit-manipulation instructions operate as a “Read-Modify-Write”
sequence, and thus may be affected by limiting during the “Read” portion of this sequence. In order for
bit-manipulation oper at ions to generate the expect ed re sul ts , li mit ing must be di sa bled. To ensure that this
is the case, the MSP (A1 portion) of an accumulator should be used as the target operand for the ANDC,
EORC, ORC, NOTC, BFCLR, BFCHG, and BFSET instructions, not the full accumulator. See
Example 3-5.

Example 3-5. Bit Manipulation on an Accumulator

; BFSET using the A1 registe r

BFSET #$0F00,A1 ; Reads A1 wi th saturation disable d

; Sets bits 11 through 8 and stores back to A1
; Note: A2 and A0 unmodified

; BFSET using the A register

BFSET #$0F00,A ; Reads A1 with saturation e nabled - may limit

; Sets bits 11 through 8 and stores back to A1
; A2 is sign extended and A0 is cleared

Since the BFTSTH, BFTSTL, BRCLR, and BRSET instructions only test the accumulator value and do
not modify it, it is recommended to do these operations on the A1 register where no limiting can occur
when integer processing is performed.

3.2.7 Converting from 36-Bit Accumulator to 16-Bit Portion

There are two t ype s of instructions t hat are useful for co nverting the 36-bi t contents of an acc umulator to a
16-bit value, which can then be stored to memory or used for further computations. This is useful for
processing word-sized operands (16 bits), since it guarantees that an accumulator contains correct sign
extension and that the lea st sign if ica nt 16 bits are all zeros. The two techniques are shown in Example 3-6
on page 3-14.

3-14 DSP56800 Family Manual 

Data Arithmetic Logic Unit

Example 3-6. Converting a 36-Bit Accumulator to a 16-Bit Value

;Converting with No Limiting
MOVE A1,A ;Sign E xtend A2, A0 set to $ 0000
MOVE A1,B ;Sign E xtend B2, B0 set to $ 0000

;Converting with Limiting En abled
MOVE A,A ;S ign Extend A2, Limit if Required
MOVE A,B ;S ign Extend B2, Limit if Required

Where limiting is enabled, as in the second example in Example 3-6, limiting only occurs when the
extension register is in use. You can determine if the extension register is in use by examining the
extension bit (E) of the status regi ster. Refer to Section 5.1.8, “Status Register,” on page 5-6.

3.3 Fractional and Integer Data ALU Arithmetic

The ability to perform both integer and fractional arithmetic is one of the strengths of the DSP56800
architecture; there is a need for both types of arithmetic.

Fractional arithmetic is typically required for computation-intensive algorithms such as digital filters,
speech coders, vect or a nd a rr ay pr oce ssing, digital control, and other signal-pro ces si ng t asks. In this mode
the data is interpreted as fractional values, and the computations are performed interpreting the data as
fractional. Often, satu ration is us ed when performing calculations in this mode to prevent the severe
distortion that occurs in an output signal generated from a result where a computation overflows without
saturation (see Figure 3-14 on page 3-28). Saturation can be selectively enabled or disabled so that
intermediate calculations can be per fo rmed wit hout limiting, and limi t ing is onl y done on final resul t s ( see
Example 3-7).

Integer arithmetic, on the other hand, is invaluable for controller code, for array indexing and address
computations, compilers, peripheral setup and handling, bit manipulation, bit-exact algorithms, and other
general-purpose tasks. Typically, saturation is not used in this mode, but is available if desired. (See
Example 3-8.)

The main difference between fractional and integer representations is the location of the decimal (or
binary) point. For fractional arithmetic, the decimal (or binary) point is always located immediately to the
right of the MSP’s most significant bit; for integer values, it is always located immediately to the right of
the value’s LSB. Figure 3-8 on page 3-15 shows the location of the decimal point (binary point), bit
weightings, and operands alignment for different fractional and integer representations supported on the
DSP56800 architecture.

Example 3-7. Fractional Arithmetic Examples

0.5 x 0.25 = 0.125

0.625 + 0.25 = 0.875

0.125 / 0.5 = 0.25

0.5 >> 1 = 0.25

Example 3-8. Integer Arithmetic Examples

4 x 3 = 12
1201 + 79 = 1280
63 / 9 = 7
100 << 1 = 200

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-15

The representation of numbers allowed on the DSP56800 architecture are as follows:

• Two’s-complement values

• Fractional or integer values

• Signed or unsigned values

• Word (16-bit), long word (32-bit) , or accumulator (36-bit)

The different representations not only affect the arithmetic operations, but also the condition code
generation. These numbers can be represented as decimal, hexadecimal, or binary numbers.

To maintain alignments of the binary point when a word operand is written to an accumulator A or B, the
operand is written to the most significant accumulator register (A1 and B1) and its most significant bit is
automatically sign extended through the accumulator extension register. The least significant accumulator
register is a utomatically cleared.

Some of the advantages of fractional data representation are as follows:

• The MSP (left half) has the same format as the input data.

• The LSP (right half) can be rounded into the MSP without shifting or updating the exponent.

Figure 3-8. Bit Weightings and Operand Alignments

16-Bit Word Operand

X0,Y0,Y1,A1,B1,

16-Bit Memory

32-Bit Long Word Operand

Y = Y1:Y0

36-Bit Accumulator

A,B

16-Bit Word Operand

X0,Y0,Y1,A1,B1 ,

16-Bit Memory

32-Bit Long Word Operand

in A1,B1

36-Bit Accumulator

A,B

Fractional Two’s-Complement Representations

Integer Two’s-Complement Representations

.

-2

0

2

-15

-2

0

2

-15

2

-16

2

-31

2

0

2

-152-16

2

-31

-2

4

-2

15

2

0

2

14

-2

31

2162

15

2

0

2

31

2162

15

2

0

-2

35

AA0041

3-16 DSP56800 Family Manual 

Data Arithmetic Logic Unit

• Conversion to floating-point representation is easier because the industry-standard floating-point
formats use fractional mantissas.

• Coefficients for most digital filters are derived as fraction s by DSP digi tal-filter design softw are
packages. The results from the DSP design tools can be used wit hout the extensive dat a conversions
that other formats require.

• A significant bit is not lost through sign extension.

3.3.1 Interpreting Data

Data in a memory location or regist er can be inter prete d as frac tiona l or int eger, de pend ing on the needs of
a user’s program. Table 3-2 shows how a 16-bit value can be interpreted as either a fractional or integer
value, depending on the location of the binary point.

The following equation shows the relationship between a 16-bit integer and a fractional value:

Fractional V alue = Intege r Value / (2

15

)

There is a similar equation relating 36-bit integers and fractional values:

Fractional V alue = Intege r Value / (2

31

)

Table 3-3 shows how a 36-bit value c an be interpreted as eith er a n integer or a fractional val u e, depending
on the location of the binary point.

Table 3-2. Interpretation of 16-Bit Data Values

Binary

Representation

1

1.This corresponds to the location of the binary point when the data is interpreted as fractional. If
the data is interpreted as integer, the binary point is located immediately to the right of the LSB.

Hexadecimal

Representation

Integer Value

(decimal)

Fractional Value

(decimal)

0.100 0000 0000 0000 $4000 16,384 0.5

0.010 0000 0000 0000 $2000 8,192 0.25

0.001 0000 0000 0000 $1000 4,096 0.125

0.111 0000 0000 0000 $7000 28,672 0.875

0.000 0000 0000 0000 $0000 0 0.0

1.100 0000 0000 0000 $C000 - 16,384 - 0.5

1.110 0000 0000 0000 $E000 - 8,192 - 0.25

1.111 0000 0000 0000 $F000 - 4,096 - 0.125

1.001 0000 0000 0000 $9000 - 28,672 - 0.875

Table 3-3. Interpretation of 36-bit Data Values

Hexadecimal

Representation

1

36-Bit Integer in

Entire Accumulator

(decimal)

16-Bit Integer in MSP

(decimal)

Fractional

Value

(decimal)

$7 FFFF FFFF 34,359,738,367 - ~ 16.0

$1 4000 0000 5,368,709,120 - 2.5
$0 4000 0000 1,073,741,824 16,384 0.5
$0 2000 0000 536,870,912 8,192 0.25
$0 0000 0000 0 0 0.0

$F C000 0000 - 1,073,741,824 - 16,384 - 0.5

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-17

3.3.2 Data Formats

Four types of two’s-complement data formats are supported by the 16-bit DSP core:

• Signed fractional

• Unsigned fractional

• Signed integer

• Unsigned in teger

The ranges for each of these formats, discussed in the following subsections, apply to all data stored in
memory and to data stored in the data ALU registers. The extension registers associated with the
accumulators allow word g rowth so tha t the most p ositive s igned fra ctional number that can b e represente d
in an accumulator is approximately 16.0 an d t he most negative signed fr act ional number is -16.0 as shown
in Table 3-3. An important factor to consider is that when the accumulator extension registers are in use,
the data containe d in the a ccumulator s cannot be stored ex actly in memory or o ther regi sters. I n these c ases
the data must be limited to the most positive or most negative number consistent w ith the size of the
destination and the sign of the accumulator, the MSB of the extension register.

3.3.2.1 Signed Fractional

In this format the N bit operand is represented using the 1.[N-1] format (1 sign bit, N-1 fractional bits).
Signed fractional numbers lie in the following range:

-1.0

≤ SF ≤ +1.0 - 2

-[N-1]

For words and long-word s igned fra ctions, t he most nega tive number th at can be represent ed is -1.0 , whose
internal representation is $8000 and $80000000, respectively. The most positive word is $7FFF or 1.0 ­2

-15

, and the most positive long word is $7FFFFFFF or 1.0 - 2

-31

.

3.3.2.2 Unsigned Fractional

Unsigned fractional number s may be though t of as positi ve only. The un signed numbe rs have ne arly twi ce
the magnitude of a signed number with the same number of bits. Unsigned fractional numbers lie in the
following ra nge:

0.0

≤ UF ≤ 2.0 - 2

-[N-1]

Examples of unsigned fractional numbers are 0.25, 1.25, and 1.999. The binary word is interpreted as
having a binary poin t aft er th e MSB. The mos t posi tive 16-bi t unsi gned nu mber is $FFFF or {1.0 + (1.0 - 2

-

[N-1]

)} = 1.99996948. The smallest unsigned number is zero ($0000).

$F E000 0000 - 536,870,912 - 8,192 - 0.25
$E C000 0000 - 5,368,709,120 - -2 .5

$8 0000 0001 -34,359,738,367 - -16.0

1.When the accumulator ext ension registers are in use, the data contai ned in the accu-

mulators cannot be st ored e xactl y in memory or o ther regis te rs. I n the se cas es the data
must be limited to the most positive or most negative number consistent with the size
of the destination.

Table 3-3. Interpretation of 36-bit Data Values (Continued)

Hexadecimal

Representation

1

36-Bit Integer in

Entire Accumulator

(decimal)

16-Bit Integer in MSP

(decimal)

Fractional

Value

(decimal)

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Data Arithmetic Logic Unit

3.3.2.3 Signed Integer

This format is used when data is being processed as integers. Using this format, the N-bit operand is
represente d using the N .0 format (N integer bits). Signed in teger numbe rs lie in the following range:

-2

-[N-1]

≤ SI ≤ [2

[N-1]

-1]

For words and long-word signed integers the most negative word that can be represented is -32768
($8000), and the most negative long word is -2147483648 ($80000000). The most positive word is 32767
($7FFF), and the most positive long word is 2147483647 ($7FFFFFFF).

3.3.2.4 Unsigned Integer

Unsigned integer numbers may be thought of as positive only. The unsigned numbers have nearly twice
the magnitude of a si gned number of the same leng th. Unsi gned intege r numbers lie i n th e foll owing ra nge:

0

≤ UI ≤ [2

N

-1]

Examples of unsigned integer numbers are 25, 125, and 1999. The binary word is interpreted as having a
binary point immediately to the right of the LSB. The most positive, 16-bit, unsigned integer is 65536
($FFFF). The smallest unsigned number is zero ($0000).

3.3.3 Addition and Subtraction

For fractional and integer arithmetic, the operations are performed identically for addition, subtraction, or
comparing two values. This means that any add, subtract, or compare instruction can be used for both
fractional and integer values.

To perform fractional or integer arithmetic operations with word-sized data, the data is loaded into the
MSP (A1 or B1) of the accumulator as shown in Figure 3-9.

Figure 3-9. Word-Sized Integer Addition Example

Fractional word-si zed a rithmet ic wo uld be perf ormed i n a s imila r ma nner. For ar ithmet ic op erati ons whe re
the destina tion is a 16- bit register or memory location, th e fractiona l or integer operation i s correctly
calculated and stored in its 16-bit destination.

Before Execution

$0000$0020$0

A2 A1 A0

$0040

X0

After Execution

$0000$0060$0

A2 A1 A0

$0040

X0

MOVE #64,X0 ; Load integer value 64 ($40) into X0
MOVE #32,A ; Load integer value 32 ($20) into A Accumulator

; (correctly sign extends into A 2 and zeros A0)
ADD X0,A ; Perform Integer Word Addition
MOVE A1,X:RESULT ; Save Result (without saturating) to Memory

AA0045

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-19

3.3.4 Logical Operations

For fractional and integer arithmetic, the logical operations (AND, OR, EOR, and bit-manipulation
instructions) are performed identically. This means that any DSP56800 logical or bit-field instruction can
be used for both fractional and integer values. Typically, logical operations are only performed on integer
values, but there is no inherent reason why they cannot be performed on fractional values as well.

Likewise, shifting can be done on both integer and fractional data values. For both of these, an arithmetic
left shift of 1 bit corresponds to a multiplication by two. An arithmetic right shift of 1 bit corresponds to a
division of a signe d value by two, and a logical right shift of 1 bi t corresponds to a div is ion of an unsigned
value by two.

3.3.5 Multiplication

The multiplication operation is not the same for integer and fractional arithmetic. The result of a fractional
multiplication differ s in a simple manner from the result of an integer multiplication. This d ifference
amounts to a 1-bit shift of the final result, as illustrated in Figure 3-10. Any binary multiplication of two
N-bit signed numbers gives a signed result that is 2N-1 bits in length. This 2N-1 bit result must then be
correctly placed into a field of 2N bits to correctly fit into the on-chip registers. For correct fractional
multiplication, an extra 0 bit is placed at the LSB to give a 2N bit result. For correct integer multiplication,
an extra sign bit is placed at the MSB to give a 2N bit result.

The MPY, MAC, MPYR, and MACR instructions perform fractional multiplication and fractional
multiply-accumulation. The IMPY(16) instruction performs integer multiplication. Section 3.3.5.2,
“Integer Multiplication,” explains how to perform integer multiplication.

3.3.5.1 Fractional Multiplication

Figure 3-11 on page 3-20 shows the multiply-accumulation implementation for fractional arithmetic. The
multiplication of two, 16-bit, signed, fractional operands gives an intermediate 32-bit, signed, fractional
result with the LSB always set to zero. This intermed iate result is added to on e of t he 36-bit accumulators.
If rounding is specified in the MPY or MAC instruction (MACR or MPY R), the intermediate results will
be rounded to 16 bits before being stored back to the destination accumulator, and the LSP will be set to
zero.

Figure 3-10. Comparison of Integer and Fractional Multiplication

S S

S

2N—1 Product

2N Bits

S S

0

2N—1 Product

2N Bits

Integer Fractional

Signed Multiplication: N X N Æ 2N - 1 Bits

X

Sign Extension Zero Fill

X

Signed Multiplier Signed Multiplier

SMSP LSP SMSP LSP

AA0042

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Data Arithmetic Logic Unit

3.3.5.2 Integer Multiplication

Two techniques for performing integer multiplication on the DSP core are as follows:

• Using the IMPY(16) instruction to generate a 16-bit result in the MSP of an accumulator

• Using the MPY and MAC instructions to generate a 36-bit full precision result

Each technique has its advantages for different types of computations.
An examination of the instruction set shows that for execution of single precision operations, most often

the instructions operate on the MSP (bits 31–16) of the accumulator instead of the LSP (bits 15–0). This is
true for the LSL, LSR, ROL, ROR, NOT, INCW, and DECW instructions and others. Likewise, for the
parallel MOVE instructi ons, it is possible to move dat a to and from the MSP of an accumulat or , but thi s i s
not true for the LSP. Thus, an integer multiplication instruction that places its result in the MSP of an
accumulator allows for more efficient computing. This is the reason why the IMPY(16) instruction places
its results in bits 31–16 of an accum ulator. The limitation wi th the IMPY(1 6) instruction is that the result
must fit within 16 bits or there is an o verflow.

Figure 3-12 on page 3-21 shows the multiply operation for integer arithmetic. The multiplication of two
16-bit signed integer operands using the IMPY(16) instruction gives a 16-bit signed integer result that is
placed in the MSP ( A1 or B1) o f the ac cumulator. The corre sponding e xtension registe r (A2 or B2) is f illed
with sign extension and the LSP (A0 or B0) remains unchanged.

Figure 3-11. MPY Operation—Fractional Arithmetic

ss

0

ss

EXP MSP LSP

Signed Fractional

Input Operands

Signed

Intermediary

Multiplier Result

Signed Fractional

MPY Result

Input Operand 1 Input Operand 2

32 Bits

36 Bits

16 Bits 16 Bits

AA0043

16 16

0

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-21

At other times it is necessary to maintain the full 32-bit precision of an integer multiplication. To obtain
integer results, an MPY instruction is used, immediately followed by an ASR instruction. The 32-bit long
integer result is then correctly located into the MSP and LSP of an accumulator with correct sign extension
in the extension register of the same accumulator (see Example 3-9).

Example 3-9. Multiplying Two Signed Integer Values with Full Precision

MPY X0,Y0,A ; Generates correct answer s hifted

; 1 bit to the left

ASR A ; Leave s Correct 32-bit Inte ger

; Result in the A Accumulato r
; and the A2 register contai ns
; correct sign extension

When a multiply-accumulate is perform ed on a set of integer numbers, there is a faster w ay for generating
the result than performing an ASR in struction after each mul t iply. The technique is to use fractional
multiply-accumulates for the bulk of the computation and to then convert the final result back to integer.
See Example 3-10.

Example 3-10. Fast Integer MACs using Fractional Arithmetic

MOVE X:(R0)+,Y0 X:(R3)+,X0
DO #N,LABEL
MAC X0,Y0,A X:(R0)+,Y0 X:(R3)+,X0

LABEL

ASR A ; Convert to Integer only after MA Cs are

; completed

3.3.6 Division

Fractional and integer division of both positive and signed values is supported using the DIV instruction.
The dividend (numerator) is a 32-bit fractional or 31-bit integer value, and the divisor (denominator) is a
16-bit fractional or integer value, respectively. See Section8.4, “Division,” on page 8-13 for a complete
discussion of division.

Figure 3-12. Integer Multiplication (IMPY)

16 Bits

Signed Integer

Output

s

s

Unchanged EXP MSP

Signed Integer

Input Operands

Signed

Intermediate

Multiplier Result

0s

S Ext.

Input Operand 1 Input Operand 2

31 Bits

16 Bits 16 Bits

16 Bits

AA0044

3-22 DSP56800 Family Manual 

Data Arithmetic Logic Unit

3.3.7 Unsigned Arithmetic

Unsigned arithmetic can be performed on the DSP56800 architecture. The addition, subtraction, and
compare instructions work for both signed and unsigned values, but the condition code computation is
different. Likewise, there is a diff erence for unsigned multiplicatio n.

3.3.7.1 Conditional Branch Instructions for Unsigned Operations

Unsigned arithmetic is supported on operations such as addition, subtraction, comparison, and logical
operations using the same ADD, SUB, CMP, and other instructions used for signed computations. The
operations are performed the same for both representations. The difference lies both in which status bits
are used in comparing signed and unsigned numbers and in how the data is interpreted, for which see
Section 3.3.2, “Data Formats.”

Four additional Bcc instruction variants are provided for branching based on the comparison of two
unsigned numbers. These variants are:

• HS (High or same)—unsigned greater than or equal to

• LS (Low or same)—unsigned less than or equal to

• HI (High)—unsigned greater tha n

• LO (Low)—unsigned less than

The variants used for co mparing u nsigne d numbers, HS, LS , HI, and LO, ar e used in place o f GE, LE, GT,
and LT respectively, which are used for comparing signed numbers. Note that the HS condition is exactly
the same as the carry clear (CC), and that LO is exactly the same as carry set (CS).

Unsigned comparisons are enabled when the CC bit in the OMR register is set. When this bit is set, the
value in the extension register is ignored when generating the C, V, N, and Z condition codes, and the
condition codes are set using only the 32 LSBs of the result. Typically, this mode is very useful for
controller and compiled code.

NOTE:

The unsigned branch conditi on variants (HS, LS, HI, and LO) may only be
used when the CC bit is set in the program controller’s OMR register. If
this bit is not set, then these condition codes should not be used.

In cases where it is neces sary to maintain all 36 bit s of the re sult and the ext ensio n regis ter is r equire d, any
unsigned numbers must fi rs t be c onverted to signed when loaded int o the accumulator using the t echnique
in Section 8.1.6, “Unsigned Load of an Accumulator,” on page 8-7. In these cases, the extension register
will contain the correct value, and since values are now signed, it is possible to use the signed branch
conditions: GE, LE, GT, or LT. Typically, this mode is more useful for DSP code.

3.3.7.2 Unsigned Multiplication

Unsigned multiplications are sup ported with the MACSU and MPYSU inst ructi ons. If onl y one o perand is
unsigned, then these instructions can be used directly. If both operands are unsigned, an
unsigned-times-unsigned multiplication is performed using the technique demonstrated in Example 3-11
on page 3-23.

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-23

Example 3-11. Multiplying Two Unsigned Fractional Values

MOVE X:FIRST,X0 ; Get first operand from mem ory
ANDC #$7FFF,X0 ; Force first operand to be positi ve
MOVE X:SECOND,Y0 ; Get second operand from memory
MPYSU X0,Y0,A
TSTW X:FIRST ; Perform final addition if MSB of first operand was a one
BGE OVER ; If first operan is less that one, jum p to OVER
MOVE #$0,B
MOVE Y0,B1 ; Move Y0 to B without sign extension
ADD B,A

OVER

(ASR A) ; Optio nally convert to inte ger result

3.3.8 Multi-Precision Operations

The DSP56800 instruction set contains several instructions which simplify extended- and multi-precision
mathematical operat ion s. By using these ins tr uct ion s, 64-bit and 96-bit calculations can be per for med, and
calculations involving different-sized operands are greatly simplified.

3.3.8.1 Multi-Precision Addition and Subtraction

Two instructions, ADC and SBC, assist in performing multi-precision addition (Example 3-12) and
subtraction (Example 3-13), such as 64-bit or 96-bit operations.

3.3.8.2 Multi-Precision Multiplication

Two instructions are provided to assist with multi-precision multiplication. When these instructions are
used, the multiplier acc ept s one sig ned and one unsigned two’s-complement operand. T he in st ruc ti ons are :

• MPYSU—multiplication with one signed and one unsigned operand

Example 3-12. 64-Bit Addition

X:$1:X:$0:Y1:Y0 + A2:A1:A0:B1:B0 = A2:A1:A0:B1:B0
(B2 must contain only sign extension before addition begins;
that is, bits 35–31 are all 1s or 0s)

MOVE X:$21,B ; Correct sign extension
MOVE X:$20,B0
ADD Y,B ; First 32-bit addition
MOVE X:$0,Y0 ; Get second 32-bit operand from memo ry
MOVE X:$1,Y1
ADC Y,A ; Second 32-bit addition

Example 3-13. 64-Bit Subtraction

A2:A1:A0:B1:B0 - X:$1:X:$0:Y1:Y0 = A2:A1:A0:B1:B0
(B2 must contain only sign extension before addition begins;
that is, bits 35–31 are all 1s or 0s)

MOVE X:$21,B ; Correct sign extension
MOVE X:$20,B0
SUB Y,B ; First 32-bit subtraction
MOVE X:$0,Y0 ; Get second 32-bit operand from memory
MOVE X:$1,Y1
SBC Y,A ; Second 32-bit subtraction

3-24 DSP56800 Family Manual 

Data Arithmetic Logic Unit

• MACSU—multiply-accumulate with one signed and one unsigned operand

The use of these instructions in multi-precision multiplication is demonstrated in Figure 3-13, with
corresponding examples shown in Example 3-14, Example 3-15 on page 3-24, and Example 3-16 on
page 3-25.

Figure 3-13. Single-Precision Times Double-Precision Signed Multiplication

Example 3-14. Fractional Single-Precision Times Double-Precision Value—Both Signed

(5 Icyc, 5 Instruction Words)

MPYSU X0,Y0,A ; Single Precision times Lowe r Portion
MOVE A0,B

MOVE A1,A0 ; 16-bit Arithmetic Right Shift
MOVE A2,A1 ; (note that A2 contains only sign extension)

MAC X0,Y1,A ; Single Precision times Uppe r Portion

; and added to Previous

Example 3-15. Integer Single-Precision Times Double-Precision Value—Both Signed

(7 Icyc, 7 Instruction Words)

MPYSU X0,Y0,A ; Single Precision times Low er Portion
MOVE A0,B

MOVE A1,A0 ; 16-bit Arithmetic Right Shift
MOVE A2,A1 ; (note that A2 contains only sig n

; extension)

MAC X0,Y1,A ; Single Precision x Upper P ortion and add to Previous
ASR A ; Conve rt result to integer, A2 contains sign extensio n
ROR B ; (52-b it shift of A2:A1:A0: B1)

32 Bits

X0

x

Sign Ext.

Signed x Unsigned

Y1 Y0

B1A0A1A2

X0 x Y0

Signed x Signed

AA0046

+

16 Bits

48 Bits

X0 x Y1

Fractional and Integer Data ALU Arithmetic

 Data Arithmetic Logic Unit 3-25

Example 3-16. Multiplying Two Fractional Double-Precision Values

;
; Signed 32x32 => 64 Multipli cation Subroutine
;
; Parameters:
; R1 = ptr to lowest word of one operand
; R2 = ptr to lowest word of one operand
; R3 = ptr to where result s are stored

MULT_S32_X_S32
CLR B ; clears B2 portion

; Multiply lwr1 * lwr2 and sav e lowest 16-bits of r esult
; Operation ; X0 Y1 Y0 A

; --------- ; ----- ----- ----- ------------------­ MOVE X:(R1),Y0 ; --- --- lwr1 ----­ ANDC #CLRMSB,Y0 ; --- --- lwr1’ ----­ MOVE X:(R2)+,Y1 ; --- lwr2 lwr1’ ----­ MPYSU Y0,Y1,A ; --- lwr2 lwr1’ lwr1’.s * lwr2.u
TSTW X:(R1)+ ; check if MSB set in original lwr1 value
BGE CORRECT_RES1 ; perform correction if this was true
MOVE Y1,B1 ; --- lwr2 lwr1’ ----­ ADD B,A ; --- lwr2 lwr1’ lwr1.u * lwr2.u
CORRECT_RES1
MOVE A0,X:(R3)+ ; --- lwr2 lwr1’ lwr1.u * lwr2.u

; Multiply two cross products and save next lowest 16-bits of result
; Operation ; X0 Y1 Y0 A
; --------- ; ----- ----- ----- ------------------­ MOVE A1,X:TMP ; (arithmetic 16-bit right shift of 36-bit accum)
MOVE A2,A ; ---- ---- ---- ----­ MOVE X:TMP,A0 ; ---- ---- ---- A = product1 >> 16

MOVE X:(R1)-,X0 ; upr1 lwr2 lwr1’ A = product1 >> 16
MACSU X0,Y1,A ; upr1 lwr2 lwr1’ A+upr1.s*lwr2.u

MOVE X:(R1),Y1 ; upr1 lwr1 lwr1’ A+upr1.s*lwr2.u
MOVE X:(R2),Y0 ; upr1 lwr1 upr2 A+upr1.s*lwr2.u
MACSU Y0,Y1,A ; upr1 lwr1 upr2 A+upr1.s*lwr2.u+upr 2.s*lwr1.u
MOVE A0,X:(R3)+ ; upr1 lwr1 upr2 A = result w/ cross prods

; Multiply upr1 * upr2 and sav e highest 32-bits of result
; Operation ; X0 Y1 Y0 A
; --------- ; ----- ----- ----- ------------------­ MOVE A1,X:TMP ; (arithmetic 16-bit right shift of 36-bit accum)
MOVE A2,A ; upr1 lwr1 upr2 ----­ MOVE X:TMP,A0 ; upr1 lwr1 upr2 A = result >> 16

MAC X0,Y0,A ; upr1 lwr1 upr2 A + upr1.s * upr2.s
MOVE A0,X:(R3)+ ; --- --- --- ----­ MOVE A1,X:(R3)+ ; --- --- --- -----

RTS

; The corresponding algorithm for integer multiplication of 32-bit values
; would be the same as for fractional with the addition of a final arithmetic
; right shift of the 64-bit result.

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Data Arithmetic Logic Unit

3.4 Saturation and Data Limiting

DSP algorithms are sometimes capable of calculating values larger than the data precision of the machine
when processing real data streams. Normally, a processor would allow the value to overflow when this
occurred, but this creates problems when processing real-time signals. The solution is saturation, a
technique whereby values that exceed the machine data precision are “clipped,” or converted to the
maximum value of the same sign that fits within the given data precision.

Saturation is especially important when data is running through a digital filter whose output goes to a
digital-to-an alog con ver ter ( DAC), si nce it “clips” the output data i nstead of all owing ar ithmet ic over flow.
Without saturat ion, t he out put d ata may i ncorr ectly s witch from a larg e posi tive numb er t o a l arge neg ative
value, which can cause problems for DAC outputs in embedded applications.

The DSP56800 architecture supports optional saturation of results through two limiters found within the
data ALU:

• the Data Limiter

• the MAC Output Limiter

The Data Limiter saturates values when data is moved out of an accumulator with a MOVE instruction or
parallel move. The MAC Output Limiter saturates the output of the data ALU’s MAC unit.

3.4.1 Data Limiter

The data limiter protects against overflow by selectively limiting when reading an accumulator register as
a source operand in a MOVE instruction. When a MOVE instruction specifies an accumulator (F) as a
source, and if the conten ts of th e selecte d source acc umulator can be represe nted in th e destina tion opera nd
size without ove rflow (that is, the a ccumu lator exte nsion re giste r not in us e), t he dat a li mite r is enabl ed but
does not saturate, and the register contents are placed onto the CGDB unmodified. If a MOVE instruction
is used and the contents of the selected source accumulator cannot be represented without overflow in the
destination operand size, the data limiter will substitute a “limited” data value onto the CGDB that has
maximum magnitude and the same sign as the source accumulator, as shown in Table 3-4 on page 3-27.

The F0 portion of an accumulator is ignored by the data limiter.
Consider a simple example, shown in Example 3-17.

Example 3-17. Demonstrating the Data Limiter—Positive Saturation

MOVE #$7FFC,A ; Initialize A = $0:7FFC:0000
INC A ; A = $ 0:7FFD:0000

MOVE A,X:(R0)+ ; Write $7FFD to memory (limiter e nabled)
INC A ; A = $ 0:7FFE:0000
MOVE A,X:(R0)+ ; Write $7FFE to memory (limiter e nabled)
INC A ; A = $ 0:7FFF:0000
MOVE A,X:(R0)+ ; Write $7FFF to memory (limiter e nabled)

INC A ; A = $ 0:8000:0000 <=== Over flows 16-bits
MOVE A,X:(R0)+ ; Write $7FFF

to memory (limiter saturates)
INC A ; A = $ 0:8001:0000
MOVE A,X:(R0)+ ; Write $7FFF

to memory (limiter saturates)
INC A ; A = $ 0:8002:0000
MOVE A,X:(R0)+ ; Write $7FFF to memory (limiter saturates)

MOVE A1,X:(R0)+ ; Write $8002

to memory (limiter disabled)

Saturation and Data Limiting

 Data Arithmetic Logic Unit 3-27

Once the accumulator incre ment s to $8 000 in Exa mple 3-17, the positive result can no lon ger be wr itt en to
a 16-bit memory location without overflow. So, instead of writing an overflowed value to memory, the
value of the most positive 16-bit number, $7fff, is written instead by the data limiter block. Note that the
data limiter block does not affect the accumulator; it only affects the value written to memory. In the last
instruction, the limiter is disabled because the register is specified as A1.

Consider a second example, shown in Example 3-18 on page 3-27.

Example 3-18. Demonstrating the Data Limiter — Negative Saturation

MOVE #$8003,A ; Initialize A = $F:8003:0000
DEC A ; A = $ F:8002:0000

MOVE A,X:(R0)+ ; Write $8002 to memory (limiter e nabled)
DEC A ; A = $ F:8001:0000
MOVE A,X:(R0)+ ; Write $8001 to memory (limiter e nabled)
DEC A ; A = $ F:8000:0000
MOVE A,X:(R0)+ ; Write $8000 to memory (limiter e nabled)

DEC A ; A = $ F:7FFF:0000 <=== Over flows 16-bits
MOVE A,X:(R0)+ ; Write $8000

to memory (limiter saturates)
DEC A ; A = $ F:7FFE:0000
MOVE A,X:(R0)+ ; Write $8000

to memory (limiter saturates)
DEC A ; A = $ F:7FFD:0000
MOVE A,X:(R0)+ ; Write $8000

to memory (limiter saturates)
MOVE A1,X:(R0)+ ; Write $7FFD to memory (limiter disabl ed)

Once the accumulator decrements to $7FFF in Example 3-18, the negative result can no longer fit into a
16-bit memory locat ion withou t overfl ow. So, inste ad of writ ing an ove rflowed va lue to m emory, the va lue
of the most negative 16-bit number, $8000, is written instead by the data limiter block.

Test logic exists in the extension portion of each accumulator register to support the operation of the
limiter circuit; the logic detects overflows so that the limiter can substitute one of two constants to
minimize errors due t o ove rf low. This process is ca ll ed “saturation arithmet ic . ” When limiting does occur,
a flag is set and latched in the status register. The value of the accumulator is not changed.

It is possib le to bypass this limiting feature when reading an accumulato r by reading it out throug h its
individual portions.

Figure 3-14 on page 3-28 demonstrates the importance of limiting. Consider the A accumulator with the
following 36-bit value to be read to a 16-bit destination:

0000 1.000 0000 0000 0000 0000 0000 0000 0000 (in binary)
(+ 1.0 in fractional decimal, $0 8000 0000 in hexadecimal)

If this accumulator is rea d without th e limiting enabled by a MOV E A1,X0 ins truction, the 16-bit X0
register after the MOVE instruction would contain the following, assuming signed fractional arithmetic:

1.000 0000 0000 0000(- 1.0 fractional decimal, $8000 in hexadecimal)

Table 3-4. Saturation by the Limiter Using the MOVE Instruction

Extension bits in use in selected

accumulator?

MSB of F2 Output of Limiter onto the CGDB Bus

No n/a Same as Input—Unmodified MSP
Yes 0 $7FFF—Maximum Positive Value
Yes 1 $8000—Maxi mum Negative Value

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Data Arithmetic Logic Unit

This is clearl y in er ror b ecause th e value -1.0 i n the X0 regi ster great ly diff ers f rom the value of +1.0 in the
source accumulator. In this case, overflow has occurred. To minimize the error due to overflow, it is
preferable to write t he maximu m (“limited”) value the destination can as sume. In th is exampl e, the li mited
value would be:

0.111 1111 1111 1111(+ 0.999969 fractional decimal, $7FFF in hexadecimal)

This is clearly closer to the original value, +1.0, than -1.0 is, and thus introduces less error. Saturation is
equally applicable to both integer and fractional arithmetic.

Thus, saturation arithmetic can have a large effect in moving from register A1 to register X0. The
instruction MOVE A1,X0 performs a move without limiting, and the instruction MOVE A,X0 performs a
move of the same 16 bits with limiting enabled. The magnitude of the error without limiting is 2.0; with
limiting it is 0.000031.

3.4.2 MAC Output Limiter

The MAC output limiter optionally saturates or limits results calculated by data ALU arithmetic operations
such as multiply, add, increment, round, and so on.

The MAC Output Limiter can be enabled by setting the SA bit in the OMR register. See Section 5.1.9.3,
“Saturation (SA)—Bit 4,” on page 5-11.

Consider a simple example, shown in Example 3-19.

Example 3-19. Demonstrating the MAC Output Limiter

BFSET #$0010,OMR ; Set SA bit—-enables MAC Output Limiter
MOVE #$7FFC,A ; Initialize A = $0:7FFC:0000
NOP

INC A ; A = $ 0:7FFD:0000
INC A ; A = $ 0:7FFE:0000
INC A ; A = $ 0:7FFF:0000

INC A ; A = $ 0:7FFF:FFFF <=== Satu rates to 16-bits!
INC A ; A = $ 0:7FFF:FFFF <=== Satu rates to 16-bits!
ADD #9,A ; A = $0:7FFF:FFFF <=== Saturates to 16-bits!

Figure 3-14. Example of Saturation Arithmetic

*Limiting automatically occurs when the 36-bit operands A and B are read with a MOVE instruction. Note that the
contents of the original accumulator are not changed.

Without Limiting—MOVE A1,X0 With Limiting—MOVE A,X0

A = +1.00 . . . 0 1 0 0 . . . . . . . . . . 0 0 0 0 . . . . . . . . . . . 0 0

3015 015 0

35 0

X0 = +0.9999690 1 1 . . . . . . . . . . 1 1

IERRORI = .000031

A = +1.00 . . . 0 1 0 0 . . . . . . . . . . 0 0 0 0 . . . . . . . . . . . 0 0

3015 015 0

35 0

X0 = -1.01 0 0 . . . . . . . . . . 0 0

IERRORI = 2.0

15 0 15 0

Saturation and Data Limiting

 Data Arithmetic Logic Unit 3-29

Once the accumulator increments to $7FFF in Example 3-19, the saturation logic in the MAC Output
limiter prevents it from growing larger because it can no longer fit into a 16-bit memory location without
overflow. So instead of writing an overflowed value to back to the A accumulator, the value of the most
positive 32-bit number, $7FFF:FFFF, is written instead as the arithmetic result.

The saturation log ic operat es by checkin g 3 bits of the 36 -bit r esult out of t he MAC unit: EXT[3] , EXT[0 ],
and MSP[15]. When the SA bit is set, these 3 bits determine if saturation is performed on the MAC unit’s
output and whether to saturate to the maximum positive value ($7FFF:FFFF) or the maximum negative
value ($8000:0000), as shown in Table 3-5.

The MAC Output Limiter not only affects the results calculated by the instruction, but can also affect
condition code computation as well. See Appendix A.4.2, “Effects of the Operating Mode Register’s SA
Bit,” on page A-11 for more information.

3.4.3 Instructions Not Affected by the MAC Output Limiter

The MAC Output Limiter is al wa ys dis abl ed ( even if the SA bit is set) when the following i nstructions are
being executed:

• ASLL, ASRR, LSRR

• ASRAC, LSRAC

• IMPY

• MPYSU, MACSU

• AND, OR, EOR

• LSL, LSR, ROL, ROR, NOT

• TST

The CMP is not affected by the OMR’s SA bit except for the case when the first operand is not a register
(that is, it is a memory location or an immediate value) and the second operand is the X0, Y0, or Y1
register. In this p articular case, the U bit ca lculation is affected by the SA bit. No other bits ar e affected by
the SA bit f or the CMP instruction.

Table 3-5. MAC Unit Outputs with Saturation Enabled

EXT[3] EXT[0] MSP[15] Result Stored in Accumulator

0 0 0 Result out of MAC Arra y wit h no lim iting

occurring
0 0 1 $0:7FFF:FFFF
0 1 0 $0:7FFF:FFFF
0 1 1 $0:7FFF:FFFF
1 0 0 $F:8000:0000
1 0 1 $F:8000:0000
1 1 0 $F:8000:0000
1 1 1 Result out of MAC Arra y wit h no lim iting

occurring

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Data Arithmetic Logic Unit

Also, the MAC Output Limiter only affects operations performed in the data ALU. It has no effect on
instructions executed in other blocks of the core, such as the following:

• Bit Manipulation Instructions (Table 6-29 and Table 6-30 on page 6-26)

• Move instructions (Table 6-17 through Table 6-20)

• Looping instructions (Table 6-32 on page 6-27)

• Change of flow instructions (Table 6-31 on page 6-27)

• Control instructions (Table 6-33 on page 6-28)

NOTE:

The SA bit affects the TFR instruction when it is set, optionally limiting
data as it is transferred from one accumulator to another.

3.5 Rounding

The DSP56800 provides three instructions that can perform rounding—RND, MACR, and MPYR. The
RND instruction simply rounds a value in the accumulator register specified by the instruction, whereas
the MPYR or MACR instructions round the result calculated by the instruction in the MAC array. Each
rounding instruction rounds the result to a single-precision value so the value can be stored in memory or
in a 16-bit register. In addition, for instructions where the destination is one of the two accumulators, the
LSP of the destination accumulator (A0 or B0) is set to $0000.

The DSP core implements two types of rounding: convergent rounding and two’s-complement rounding.
For the DSP56800, the roun ding point is between bi ts 16 and 15 of a 36- bit value; for the A accumulat or, it
is between the A1 register’s LSB and the A0 register’s MSB. The usual rounding method rounds up any
value above one-half (that is, LSP > $8000) and rounds down any value below one-half (that is, LSP <
$8000). The question arises as to which way the number one-h alf (LSP = $8000) sho uld be rounded. If it is
always rounded one way, the results will eventually be biased in that direction. Convergent rounding
solves the problem by rounding down if the number is even (bit 16 equals zero) and rounding up if the
number is odd (bit 16 equals one), whereas two’s-complement rounding always rounds this number up.
The type of rounding is selected by the rounding bit (R) of the operating mode register (OMR) in the
program controller.

3.5.1 Convergent Rounding

This is the default rounding mode. This rounding is also called “round to nearest even number.” For most
values, this mode rounds identically to two’s-complement rounding; it only differs for the case where the
least significant 16 bit s is exa ctly $8000. For t his cas e, con vergent roundi ng preve nts any i ntrodu ction of a
bias by rounding down if the number is even (bit 16 equals zero) and rounding up if the rounding is odd
(bit 16 equals one). Figur e 3-15 on page 3-31 shows the four possible cases for rounding a numbe r in the A
or B accumulator.

Rounding

 Data Arithmetic Logic Unit 3-31

3.5.2 Two’s-Complement Rounding

When this type of rounding is selected by sett ing the rounding bit in the OMR, one i s added to the bit to the
right of the rounding p oint (bit 15 of A0) bef ore the bi t truncat ion durin g a rounding operatio n. Figure 3-16
shows the two possible cases.

Figure 3-15. Convergent Rounding

Case I: If A0 < $8000 (1/2), then round down (add nothing)

Before Rounding

After Rounding

Case II: If A0 > $8000 (1/2), then round up (Add 1 To A1)

Case III: If A0 = $8000 (1/2), and the LSB of A1 = 0 (even),then round down (add nothing)

Case IV: If A0 = $8000 (1/2), and the LSB = 1 (odd), then round up (add 1 To A1)

*A0 is always clear; performed during RND, MPYR, and MACR

X X . . X X X X X . . . X X X 0 1 0 0 0 1 1 X X X . . . . X X X

35 32 31 16 15 0

A2 A1 A0

0

X X . . X X X X X . . . X X X 0 1 0 0 0 0 0 . . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0*

Before Rounding

After Rounding

X X . . X X X X X . . . X X X 0 1 0 0 1 1 1 0 X X . . . . X X X

35 32 31 16 15 0

A2 A1 A0

1

X X . . X X X X X . . . X X X 0 1 0 1 0 0 0 . . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0*

Before Rounding

After Rounding

X X . . X X X X X . . . X X X 0 1 0 0 1 0 0 0 . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0

0

X X . . X X X X X . . . X X X 0 1 0 0 0 0 0 . . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0*

Before Rounding

After Rounding

X X . . X X X X X . . . X X X 0 1 0 1 1 0 0 0 . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0

1

X X . . X X X X X . . . X X X 0 1 1 0 0 0 0 . . . . . . . . . 0 0 0

35 32 31 16 15 0

A2 A1 A0*

AA0048

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Data Arithmetic Logic Unit

Once the rounding bit has been programmed in the OMR register, there is a delay of one instruction cycle
before the new rounding mode becomes active.

Figure 3-16. Two’s-Complement Rounding

XXXX XX...XX0100 011XXX...XX XXXX XX...XX0100 0000...0000

XXXX XX...XX0100

1110XX...XX XXXX XX...XX0101 0000...0000

Case I: A0 < 0.5 ($8000), then round down

Case II: A0 >= 0.5 ($8000), then round up

Before Rounding

After Rounding

A2 A1 A0 A2 A1 A0*

36 31 15 0 36 31 15 0

A2 A1 A0 A2 A1 A0*

36 31 15 0 36 31 15 0

Before Rounding

After Rounding

AA0050

*A0 is always clear; performed during RND, MPYR, MACR

Condition Code Generation

 Data Arithmetic Logic Unit 3-33

3.6 Condition Code Generation

The DSP core supports many different arithmetic instructions for both word and long-word operations.
The flexible nature of the instruction set means that condition codes must also be generated correctly for
the different combinations allowed. There are three questions to consider when condition codes are
generated for an instruc tion:

• Is the arithmetic opera tion’s destination an accumulator, or a 16-bit register or memory location?

• Does the instruction operate on the whole accumulator or only on the upper portion?

• Is the CC bit set in the program controller ’s OMR register?

The CC bit in the OMR register allows condition codes to be generated without an examination of the
contents of the extension register. This sets up a computing environment where there is effectively no
extension register because its contents are ignored. Typically, the extension register is most useful in DSP
operations. For the case of general-purpose computing, the CC bit is often set when the program is not
performing DSP tasks. However, it is possible to execute any instruction with the CC bit set or cleared,
except for instructions that use one of the unsigned condition codes (HS, LS, HI, or LO).

This section covers different aspects of condition code generation for the different instructions and
configurations on th e DSP core. Note that the L, E, and U bits are co mputed the same reg ardle ss of the size
of the destination or the value of the CC bit:

• L is set if overflow occurs or limiting occurs in a parallel move.

• E is set if the extension register is in use (that is, if bits 35–31 are not all the same).

• U is set according to the standard definition of the U bit.

3.6.1 36-Bit Destinations—CC Bit Cleared

Most arithmetic instructions generate a result for a 36-bit accumulator. When condition codes are being
generated for this case and the CC bit is cleared, condition codes are generated using all 36 bits of the
accumulator. Examples of instr uctions in this category are ADC, ADD, ASL, CMP, MAC, MACR, MPY,
MPYR, NEG, NORM, and RND.

The condition codes for 36-bit destinations are computed as follows:

• N is set if bit 35 of the corresponding accumulator is set except during saturation. During a
saturation condition, the V (overflow) bit is set and the N bit is not set.

• Z is set if bit s 35–0 of the corresponding accumulator are all cleared.

• V is set if overflow has occurred in the 36-bit result.

• C is set if a carry (borrow) has occurred out of bit 35 of the result.

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Data Arithmetic Logic Unit

3.6.2 36-Bit Destinations—CC Bit Set

Most arithmetic instructions generate a result for a 36-bit accumulator. When condition codes are being
generated for this case and the CC bit is set, condition codes are generated using only the 32 bits of the
accumulator located in the MSP and LSP. There may be values in the extension registers, but the contents
of the extension regist er are ignor ed. It is eff ectively the same as if ther e is no extens ion regist er. Examples
of instructions in this category are ADC, ADD, ASL, CMP, MAC, MACR, MPY, MPYR, NEG, NORM,
and RND.

The condition codes for 32-bit destinations (CC equals one) are computed as follows:

• N is set if bit 31 of the corresponding accumulator is set.

• Z is set if bit s 31–0 of the corresponding accumulator are all cleared.

• V is set if overflow has occurred in the 32-bit result.

• C is set if a carry (borrow) has occurred out of bit 31 of the result.

3.6.3 20-Bit Destinations—CC Bit Cleared

Two arithmetic instructions generate a result for the upper two portions of an accumulator, the MSP and
the extension register, leaving the LSP of the accumulator unchanged. When condition codes are being
generated for this case and the CC bit is cleared, condition codes are generated using the 20 bits in the
upper two portions of the accumulator. The two instructions in this category are DECW and INCW.

The condition codes for DECW and INCW (CC equals zero) are computed as follows:

• N is set if bit 35 of the corresponding accumulator is set except during saturation. During a
saturation condition, the V (overflow) bit is set and the N bit is not set.

• Z is set if bit s 35–16 of the corresponding accumulator are all cleared.

• V is set if overflow has occurred in the 20-bit result.

• C is set if a carry (borrow) has occurred out of bit 35 of the result.

3.6.4 20-Bit Destinations—CC Bit Set

Two arithmetic instructions generate a result for the upper two portions of an accumulator, the MSP and
the extension register, leaving the LSP of the accumulator unchanged. When condition codes are being
generated for this case and the CC bit is set, the bits in the extension register and the LSP of the
accumulator are not us ed to cal culate c ondition c odes. The t wo instruc tions in t his cat egory are DECW and
INCW.

The condition codes for 16-bit destinations (CC equals one) are computed as follows:

• N is set if bit 31 of the corresponding accumulator is set.

• Z is set if bit s 31–16 of the corresponding accumulator are all cleared.

• V is set if overflow has occurred in the 16-bit result.

• C is set if a carry (borrow) has occurred out of bit 31 of the result.

Condition Code Generation

 Data Arithmetic Logic Unit 3-35

3.6.5 16-Bit Destinations

Some arithmetic i nst ruct ions c an gene ra te a resul t for a 36- bit acc umulato r or a 1 6-bit dest inati on suc h a s a
register or memory locat ion. When cond itio n codes fo r a 16-bi t dest inati on are be ing gene rated, the CC bit
is ignored and co nditi on code s are genera te d usin g the 1 6 bits of the resul t. Ins truct ions i n thi s catego ry are
ADD, CMP, SUB, DECW, INCW, MAC, MACR, MPY, MPYR, ASR, and ASL.

The condition codes for 16-bit destinations are computed as follows:

• N is set if bit 15 of the result is set.

• Z is set if bit s 15–0 of the result are all cleared.

• V is set if overflow has occurred in the 16-bit result.

• C is set if a carry (borrow) has occurred out of bit 15 of the result.

Other instructions only generate results for a 16-bit destination such as the logical instructions. When
condition codes are being generated for this case, the CC bit is ignored and condition codes are generated
using the 16 bits of the result. Instructions in this category are AND, EOR, LSL, LSR, NOT, OR, ROL,
and ROR. The rules for condition code generation are presented for the cases where the destination is a
16-bit register or 16 bits of a 36-bit accumulator.

The condition codes for logical instructions with 16-bit registers as destinations are computed as follows:

• N is set if bit 15 of the corresponding register is set.

• Z is set if bit s 15–0 of the corresponding register are all cleared.

• V is always cleared.

• C—Computation dependent on instruction.

The condition codes for logical instructions with 36-bit accumulators as destinations are computed as
follows:

• N is set if bit 31 of the corresponding accumulator is set.

• Z is set if bit s 31–16 of the corresponding accumulator are all cleared.

• V is always cleared.

• C—Computation dependent on instruction.

3.6.6 Special Instruction Types

Some instructions do not fol low the pr ecedi ng rule s for c onditi on code ge nerat ion, and must be con sider ed
separately. Examples of instructions in this category are the logical and bit-field instructions (ANDC,
EORC, NOTC, ORC, BFCHG, BFCLR, BFSET, BFTSTL, BFTSTH, BRCLR, and BRSET), the CLR
instructio n, the IMPY(1 6) instruction, the multi-bit shifting instructions (ASLL, ASRR, LSLL, LSRR,
ASRAC, and LSRAC), and the DIV instruction.

The bit-field instructions only affect the C and the L bits. The CLR instruction only generates condition
codes when clearing an accumulator. The condition codes are not modified when clearing any other
register. Some of the condition codes are not defined after executing the IMPY(16) and multi-bit shifting
instructions. The DIV instruction only affects a subset of all the condition codes. See Appendix A.4,
“Condition Code Computation,” on page A-6 for details on the condition code computation for each of
these instructions.

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Data Arithmetic Logic Unit

3.6.7 TST and TSTW Instructions

There are two instructions, TST and TSTW, that are useful for checking the value in a register or memory
location.

The condition codes f or the TST i nstru ction ( on a 36-bi t accu mulat or) with CC equ al to zero a re comput ed
as follows:

• L is set if limiting occurs in a parallel move.

• E is set if the extension register is in use—that is, if bits 35–31 are not all the same.

• U is set according to the standard definition of the U bit.

• N is set if bit 35 of the corresponding accumulator is set except during saturation.

• Z is set if bit s 35–0 of the corresponding accumulator are all cleared.

• V is always cleared.

• C is always cleared.

The condition codes for the TST instr uct ion (on a 36-bit accumulator) with CC equal to one are compu ted
as follows:

• L is set if limiting occurs in a parallel move.

• E is set if the extension register is in use, that is, if bits 35–31 are not all the same.

• U is set according to the standard definition of the U bit.

• N is set if bit 31 of the corresponding accumulator is set.

• Z is set if bit s 31–0 of the corresponding accumulator are all cleared.

• V is always cleared.

• C is always cleared.

The condition codes for the TSTW instruction (on a 16-bit value) are computed as follows:

• N is set if the MSB of the 16-bit value is set.

• Z is set if all 16 bits of the 16-bit value are cleared.

• V is always cleared.

• C is always cleared.

3.6.8 Unsigned Arithmetic

When arithmetic on unsigned operands is being performed, the condition codes used to compare two
values differ from those used for signed arithmetic. See Section 3.3.7, “Unsigned Arithmetic,” for a
discussion of condition code usage for unsigned arithmetic.

 Address Generation Unit 4-1

Chapter 4

Address Generation Unit

This chapter describes the architecture and the operation of the address generation unit (AGU). The
address generation unit is the block where all address calculations are performed. It contains two
arithmetic units—a modulo arithmetic unit for complex address calculations and an
incrementer/decrementer for simple calculations. The modulo arithmetic unit can be used to calculate
addresses in a modulo fashion, automatically wrapping around when necessary. A set of pointer registers,
special-purpose regi st ers , and mult iple buses within the unit allo w up to two addre ss updates or a memory
transfer to or from the AGU in a single cycle.

The capabilities of the address generation unit include the following operations:

• Provide one address to X data memory on the XAB1 bus

• Post-update an address after providing the original address value on XAB1 bus

• Calculate an effective address which is then provided on the XAB1 bus

• Provide two addresses to X data memory on the XAB1 and XAB2 buses and post-update both

addresses

• Provide one address to program memory for program memory data accesses and post-update the
address

• Increment or decrement a counter during normalization operations

• Provide a conditional register move (Tcc instruction)

Note that in the cas es where the address gen eration u nit is gene rating on e or two addre sses t o access X dat a
memory, the program controller generates a second or third address used to concurrently fetch the next
instruction.

The AGU provides many different addressing modes, which include the following:

• Indirect addressing with no update

• Indirect addressing with post-increment

• Indirect addressing with post-decrement

• Indirect addressing with post-update by a

register

• Indirect addressing with index by a 16-bit
offset

• Indirect addressing with index by a 6-bit
offset

• Indirect addressing with index by a register

• Immediate data

• Immediate short data

• Absolute addressing

• Absolute short addressing

• Peripheral short addressing

• Register direct

• Implicit

4-2 DSP56800 Family Manual 

Address Generation Unit

This chapter covers the arc hit ecture and programming mode l of the addr ess generation unit, it s add ressing
modes, and a discussion of the linear and modulo arithmetic capabilities of this unit. It concludes with a
discussion of pipeline dependencies related to the address generation unit.

4.1 Architecture and Programming Model

The major components of the address generation unit are as follows:

• Four address registers (R0-R3)

• A stack pointer register (SP)

• An offset register (N)

• A modifier register (M01)

• A modulo arithmetic unit

• An incrementer/decrementer unit

The AGU uses integer arithmetic to perform the effective address calculations necessary to address data
operands in memory. The AGU also contains the registers used to generate the addresses. It implements
linear and modulo arithmetic and operates in parallel with other chip resources to minimize
address-generation overhead.

Two ALUs are present within the AGU: the modulo ari th meti c uni t and t he i ncr ement er /de cr ement er uni t.
The two arithmetic unit s can genera te up to two 16-bi t addresse s and two addres s updates eve ry instruc tion
cycle: one for XAB1 and one f o r XAB2 for in st ructions performing two para llel memory reads. The AGU
can directly address 65,536 locations on XAB1 and 65,536 locations on the PAB. The AGU can directly
address up to 65,536 locations on XAB2, but can only generate addresses to on-chip memory. The two
ALUs work with the data memor y to ac cess u p to two loc ation s and pr ovide two oper ands t o the d ata ALU
in a single cycle. The primary operand is addressed with the XAB1, and the second operand is addressed
with the XAB2. The data memory, in turn, places its data on the core global data bus (CGDB) and the
second external data bus ( XDB2), respectively ( see Figure 4-1 on page 4-3). See Section 6.1, “Introduction
to Moves and Parallel Moves,” on page 6-1 for more discussion on parallel memory moves.

Architecture and Programming Model

 Address Generation Unit 4-3

All four address pointer registers and the SP are used in generating addresses in the register indirect
addressing modes. The of fset register can be used by all four addre ss poi nter registers and th e SP, whereas
the modulo register can be used by the R0 or by both the R0 and R1 pointer registers.

Whereas all the address point er regist ers and the SP can be use d in many addressi ng modes, there are some
instructions that only work with a specific address pointer register. These cases are presented in Table 4-5
on page 4-9.

The address generation unit is connected to four major buses: CGDB, XAB1, XAB2, and PAB. The
CGDB is used to read or write any of the address generation unit registers. The XAB1 and XAB2 provide
a primary and secondary address, respectively, to the X data memory, and the PAB provides the address
when accessing the program memory.

A block diagram of the addr ess gener ation uni t is shown i n Figure 4-1, and its corr esponding p rogrammi ng
model is shown in Figure 4-2. The blocks and registers are explained in the following subsections.

Figure 4-1. Address Generation Unit Block Diagram

Figure 4-2. Address Generation Unit Programming Model

R0

R2
R3

N

XAB2(15:0)PAB(15:0) XAB1(15:0)

R3 Only

Inc./Dec.

R1

SP

Modulo

Arithmetic

Unit

M01

CGDB(15:0)

AA0014

N M01

SP

R3

R2

R1

R0

Pointer
Registers

Offset

Register

Modifier
Register

AA0015

15 0 15 0 15 0

4-4 DSP56800 Family Manual 

Address Generation Unit

4.1.1 Address Registers (R0-R3)

The address registe r file con sists of four 16-b it reg ister s R0-R3 (Rn) that us ually contai n addres ses use d as
pointers to memory. Each register may be read or written by the CGDB. High speed access to the XAB1,
XAB2, and PAB buses is required to allow maximum access time for the internal and external X data
memory and program memory. Each address register may be used as input for the modulo arithmetic unit
for a register update calculation. Each register may be written by the output of the modulo arithmetic unit.

The R3 register may be used as input to a separate incrementer/decrementer unit for an independent
register update calculation. This unit is used in the case of any instruction that performs two data memory
reads in its parallel move field. For instructions where two reads are performed from the X data memory,
the second read using the R3 pointer must always access on-chip memory.

NOTE:

Due to pipelining, if an address register (Rn, SP, or M01) is changed with
a MOVE or bit-field instruction, the new contents will not be available for
use as a pointer unt il the second f ollowing instructi on. If the SP i s changed,
no LEA or POP instructions are permitted until the second following
instruction.

4.1.2 Stack Pointer Register (SP)

The stack pointer register (SP) is a single 16-bit register that is used implicitly in all PUSH instruction
macros and POP instructions. The SP is used explicitly for memory references when used with the
address-register-indirect modes. It is post-decremented on all POPs from the software stack. The SP
register may be read or written by the CGDB.

NOTE:

This register must be initialized explicitly by the programmer after coming
out of reset.

Due to pipelining, if an address register (Rn, SP, or M01) is changed with
a MOVE or bit-field instruction, the new contents will not be available for
use as a pointer unt il the second f ollowing instructi on. If the SP i s changed,
no LEA or POP instructions are permitted until the second following
instruction.

4.1.3 Offset Register (N)

The offset register (N) usually contains offset values used to update address pointers. This single register
can be used to update or index with any of the address registers (R0-R3, SP). This offset register may be
read or written by the CGDB. The offset register is used as input to the modulo arithmetic unit. It is often
used for array indexing or indexing into a table, as discussed in Section 8.7, “Array Indexes,” on page
8-26.

Architecture and Programming Model

 Address Generation Unit 4-5

NOTE:

If the N address register is changed with a MOVE instruction, this
register’s contents will be available for use on the immediately following
instruction. In this case the instruction that writes the N address register
will be stretched one additional instruction cycle. This is true for the case
when the N register is used by the immediately f ol lowi ng i n st ru ct ion; if N
is not used, then the instruction is not stretched an additional cycle. If the
N address register is change d with a bit- fiel d instr ucti on, the new cont ents
will not be available for use until the second following instruction.

4.1.4 Modifier Register (M01)

The modifier register (M01) specifies whether linear or modulo arithmetic is used when calculating a new
address and may be read or written by t he CGDB. This modifier re gister is automatica lly read when the R0
address register is used in an address calculation and can optionally be used also when R1 is used. This
register has no effec t on address calculation s done with the R2, R3, or SP regist ers. It is used as input to the
modulo arithmetic unit. This modifier register is preset during a processor reset to $FFFF (linear
arithmetic).

NOTE:

Due to pipelining, if an address register (Rn, SP, or M01) is changed with
a MOVE or bit-field instruction, the new contents will not be available for
use as a pointer unt il the second f ollowing instructi on. If the SP i s changed,
no LEA or POP instructions are permitted until the following instruction.

4.1.5 Modulo Arithmetic Unit

The modulo arithmetic unit can update one address register or the SP during one instruction cycle. It is
capable of performing linear and modulo arithmetic, as described in Section 4.3, “AGU Address
Arithmetic.” The contents of the modifier register specifies the type of ar ithmetic to be performed in an
address register update calculation. The modifier value is decoded in the modulo arithmetic unit and
affects the unit’s operation. The modulo arithmetic unit’s operation is data-dependent and requires
execution cycle dec oding of the selected modifier regi ster cont ents. Note th at the modulo capabili ty is only
allowed for R0 or R1 updates; it is not allowed fo r R2, R3, or SP updates.

The modulo arithmetic uni t first ca lcula tes the result of linear ar ithmet ic (for exam ple, Rn+1, Rn-1, Rn +N)
which is selected as the modulo arithmetic unit’s output for linear arithmetic. For modulo arithmetic, the
modulo arithmetic unit will perform the function (Rn+N) modulo (M01+1), where N can be 1, -1, or the
contents of the of fset re giste r N. I f the modulo o perat ion re quire s “wraparound” for modulo arith metic, the
summed output of the modulo adder will give the correct, updated address register value; otherwise, if
wraparound is not necessary, the linear arithmetic calculation gives the correct result.

4.1.6 Incrementer/Decrementer Unit

The incrementer/decrementer unit is used for address-update calculations during dual data-memory read
instructions. It is used either to increment or decrement the R3 register. This adder performs only linear
arithmetic; it performs no modulo arithmetic.

4-6 DSP56800 Family Manual 

Address Generation Unit

4.2 Addressing Modes

The DSP56800 instruction set contains a full set of operand addressing modes, optimized for
high-performance signal processing as well as efficient controller code. All address calculations are
performed in the address generation unit to minimize execution time.

Addressing modes specify where the operand or operands for an instruction can be found—whether an
immediate value, loca ted in a register, or in me mory—and provide the exact address of the operand(s).

The addressing modes are grouped into four categories:

• Register direct—directly references the processor registers as operands

• Address register indirect—uses an address register as a pointer to reference a location in memory

as an operand

• Immediate—the operand is contained as a value within the instruction itself

• Absolute—uses an address cont ained within the instr uction to referenc e a location in memory as an

operand

An effective address in an instruction will specify an addressing mode (that is, where the operands can be
found), and for some addressing modes the effective address will further specify an address register that
points to a location in memory, how the address is calculated, and how the register is updated.

These addressing modes are referred to extensively in Section 6.5.2, “LSLL Alias,” on page 6-13.
Several of the examples in the follo wing sections demonstr ate the use of assembler forcing op erators.

These can be used in an instruction to force a desired addressing mode, as shown in Table 4-1.

Other assembler forcing operators are available for jump and branch instructions, as shown in Table 4-2.

Table 4-1. Addressing Mode Forcing Operators

Desired Action Forcing Operator Syntax Example

Force immediate short data #<xx #<$07
Force 16-bit immediate data #>xxxx #>$07
Force absolute short address X:<xx X:<$02
Force I/O short address X:<<xx X:<<$FFE3
Force 16-bit absolute address X:>xxxx X:>$02
Force short offset X:(SP-<xx) X:(SP-<$02)
Force 16-bit offset X:(Rn+>xxxx) X:(R0+>$03)

Table 4-2. Jump and Branch Forcing Operators

Desired Action Forcing Operator Syntax Example

Force 7-bit relative branch offset <xx <LABEL1
Force 16-bit absolute jump address >xxxx >LABEL5
Force 16-bit absolute loop address >xxxx >LABEL4

Addressing Modes

 Address Generation Unit 4-7

4.2.1 Register-Direct Modes

The register-direct addressing modes specify that the operand is in one (or more) of the nine data ALU
registers, seven address registers, or four control registers. The various options are shown in Table 4-3 on
page 4-7.

4.2.1.1 Data or Control Register Direct

The operand is in one , two, or three data ALU registe r( s) as spec if ied in the operands or i n a portion of the
data bus movement field in the instruction. This addressing mode is also used to specify a control register
operand. This reference is classified as a register reference.

4.2.1.2 Address Register Direct

The operand is in one of the seven address registers (R0-R3, N, M01, or SP) specified by an effective
address in the instruction. This reference is classified as a register reference.

NOTE:

Due to pipelining, if any address register is changed with a MOVE or
bit-field instruction, the new contents will not be available for use as a
pointer until the second following instruction. If the SP is changed, no
LEA or POP instructions are permitted until the second following
instruction.

4.2.2 Address-Register-Indirect Modes

When an address register is used to point to a memory location, the addressing mode is called address
register indirect. The term indirect is used because the operand is not the address register itself, but the
contents of the memory location pointed to by the address register. The eff ec ti ve a ddr ess in the instructi on
specifies the address register Rn or SP and the address calculation to be performed. These addressing

Table 4-3. Addressing Mode—Register Direct

Addressing Mode:

Register Direct

Notation for Register Direct in the

Instruction Set Summary

1

1. The register field notations found in the middle column are explained in more detail
in Table 6-16 on page 6-16 and Table 6-15 on page 6-15.

Examples

Any register DD

DDDDD

HHH

HHHH

F

F1

F1DD

FDD

Rj

Rn

A, A2, A1, A0
B, B2, B1, B0

Y, Y1, Y0

X0

R0, R1, R2, R3

SP

N

M01

PC

OMR, SR

LA, LC

HWS

4-8 DSP56800 Family Manual 

Address Generation Unit

modes specify that the operand is (or operands are) in memory and provide the specific address(es) of the
operand(s). A portion of the data bus movement field in the instruction specifies the memory reference to
be performed. The type of address arithmetic used is specified by the address modifier register.

Address-register-indirect modes may require an offset and a modifier register for use in address
calculations. The address register (Rn or SP) is used as the address register, the shared offset register is
used to specify an optional offset from this pointer, and the modifier register is used to specify the type of
arithmetic performed.

Some addressing modes are only available with certain address registers (Rn). For example, although all
address registers support the “indexed by long displacement” addressing mode, only the R2 address
register supports the “indexed by short displacement” addressing mode. For instructions where two reads
are performed from th e X dat a memory, t he se cond re ad usi ng the R3 point er mus t always b e from on-chi p
memory. The addressed register sets are summarized in Table 4-5.

Table 4-4. Addressing Mode—Address Register Indirect

Addressing Mode:

Address Re gister Indirect

Notation in the Instruction

Set Summary

1

1. Rj represents one of the four pointer registers R0-R3; Rn is any of the AGU address
registers R0-R3 or SP.

Examples

Accessing Program (P) Memory

Post-increment P:(Rj)+ P:(R0)+
Post-update by offset N P:(Rj)+N P:(R3)+N

Accessing Data (X) Memory

No update X:(Rn) X:(R3)

X:(N)

X:(SP)

Post-increment X:(Rn)+ X:(R1)+

X:(SP)+

Post-decrement X:(Rn)- X:(R3)-

X:(N)-

Post-update by offset N or N3
available for word accesses only

X:(Rn)+N X:(R1)+N

Indexed by offset N X:(Rn+N) X:(R2+N)

X:(SP+N)

Indexed by 6-bit displacement
R2 and SP registers only

X:(R2+xx)

X:(SP-xx)

X:(R2+15)

X:(SP-$1E)

Indexed by 16-bit displacement X:(Rn+xxxx) X:(R0-97)

X:(N+1234)

X:(SP+$03F7)

Addressing Modes

 Address Generation Unit 4-9

The type of arithmetic to be performed is not encoded in the instruction, but it is specified by the address
modifier register (M01 for the DSP56800 core). It indicates whether linear or modulo arithmetic is
performed when doing address calculations. In the case where there is not a modifier register for a
particular regis ter set (R2 or R3), l inear ad dressing is always performed. For addr ess calc ulations using R0,
the modifier register is always used; for calculations using R1, the modifier register is optionally used.

Each address-register-indirect addressing mode is illustrated in the following subsections.

4.2.2.1 No Update: (Rn), (SP)

The address of the operand is in the address register Rn or SP. The contents of the Rn register are
unchanged. The M01 and N registers are ignored. This reference is classified as a memory reference. See
Figure 4-3.

Table 4-5. Address-Register-Indirect Addressing Modes Available

Register

Set

Arithmetic

Types

Addressing Modes Allowed Notes

R0/M01/N Linear or modulo (R0)

(R0)+
(R0)­(R0)+N
(R0+N)
(R0+xxxx)

R0 always uses the M01 register
to specify modulo or linear arith­metic. R0 can optiona ll y be use d
as a source register for the Tcc
instruction. R0 is the on ly register
allowed as a counter for the
NORM instruction.

R1/M01/N Linear or modulo (R1)

(R1)+
(R1)­(R1)+N
(R1+N)
(R1+xxxx)

R1 optionally uses the M01 reg­ister to specify modulo or linear
arithmetic. R1 can optionally be
used as a destination register for
the Tcc instruction.

R2/N Linear (R2)

(R2)+
(R2)­(R2)+N
(R2+N)
(R2+xx)
(R2+xxxx)

R2 supports a one-word indexed
addressing mode. R2 is not
allowed as either pointer for
instructions that perform two
reads from X data memory. No
modulo arithmetic is allowed.

R3/N Linear (R3)

(R3)+
(R3)­(R3)+N
(R3+N)
(R3+xxxx)

R3 provides a second address
for instructions with two reads
from data memory. This second
address can only acce ss inte rnal
memory. It can also be used for
instructions that perform one
access to data memo ry. No m od ­ulo arithmetic is allowed.

SP/N Linear (SP)

(SP)­(SP)+
(SP)+N
(SP+N)
(SP-xx)
(SP+xxxx)

The SP supports a one-word
indexed addressing m ode, which
is useful for accessing local vari­ables and passed parameters.
No modulo arithmetic is allowed.

4-10 DSP56800 Family Manual 

Address Generation Unit

Figure 4-3. Address Register Indirect: No Update

$1000

Before Execut i on

X Memory

XXXX

$1000R0

(n/a)N

(n/a)M01

12340

A2 A1

5678

A0

A

After Execution

$1000R0

(n/a)N

(n/a)M01

12340

A2 A1

5678

A0

A

Assembler syntax: X:(Rn), X:(SP)
Additional instruction execution cycles: 0
Additional effective address program words: 0

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0016

No Update Example: MOVE A1,X: (R0)

$1000

X Memory

1234

15 0

Addressing Modes

 Address Generation Unit 4-11

4.2.2.2 Post-Increment by 1: (Rn)+, (SP)+

The address of the operand is in the address register Rn or SP. After the operand address is used, it is
incremented by o ne and stored in th e same address regi st er . The type of ari thme ti c (l inear or modulo) us ed
to increment Rn is determined by M01 for R0 and R1 and is always linear for R2, R3, and SP. The N
register is ignored. This reference is classified as a memory reference. See Figure 4-4.

Figure 4-4. Address Register Indirect: Post-Increment

$2500

Before Execut i on

X Memory

XXXX

$2500R1

(n/a)N

$FFFFM01

6543A

B2 B1

FEDC

B0

B

After Execution

$2501R1

(n/a)N

$FFFFM01

6543A

B2 B1

FEDC

B0

B

Assembler syntax: X:(Rn)+, X:(SP)+, P:(Rn)+
Additional instruction execution cycles: 0
Additional effective address program words: 0

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0017

Post-Increment Example: MOVE B0,X:(R1)+

$2500

X Memory

FEDC

15 0

$2501 XXXX $2501 X X X X

4-12 DSP56800 Family Manual 

Address Generation Unit

4.2.2.3 Post-Decrement by 1: (Rn)-, (SP)-

The address of the operand is in the address register Rn or SP. After the operand address is used, it is
decremented by one and stored in the same address re gister. The ty pe of arithmet ic (linear or modulo) used
to increment Rn is determined by M01 for R0 and R1 and is always linear for R2, R3, and SP. The N
register is ignored. This reference is classified as a memory reference. See Figure 4-5.

Figure 4-5. Address Register Indirect: Post-Decrement

$4734

Before Execut i on

X Memory

XXXX

$4735R1

(n/a)N

$FFFFM01

65430

B2 B1

FEDC

B0

B

After Execution

$4734R1

(n/a)N

$FFFFM01

65430

B2 B1

FEDC

B0

B

Assembler syntax: X:(Rn)-, X:(SP)­Additional instruction execution cycles: 0
Additional effective address program words: 0

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0018

Post-Decrement Example: MOVE B,X:(R 1)-

$4734

X Memory

XXXX

15 0

$4735 XXXX $4735 6 5 4 3

Addressing Modes

 Address Generation Unit 4-13

4.2.2.4 Post-Update by Offset N: (Rn)+N, (SP)+N

The address of the operand is in the address register Rn or SP. After the operand address is used, the
contents of the N register are added to Rn and stored in the same address register. The content of N is
treated as a two’s-complement signed number. The contents of the N register are unchanged. The type of
arithmetic (linear or mo dulo) used to update Rn is determined by M01 for R0 and R1 and is always linear
for R2, R3, and SP. This reference is classified as a memory reference. See Figure 4-6.

Figure 4-6. Address Register Indirect: Post-Update by Offset N

$3200

Before Execut i on

X Memory

XXXX

$3200R2

$0004N

$FFFFM01

5555Y1AAAA

Y0

Y

After Execution

$3204R2

$0004N

$FFFFM01

5555Y1AAAA

Y0

Y

Assembler syntax: X:(Rn)+N, X:(SP)+N, P:(Rn)+N
Additional instruction execution cycles: 0
Additional effective address program words: 0

31 16 15 0

15 0

31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0019

Post-Update by Offset N Example: MOVE Y1,X:(R2)+N

$3200

X Memory

5555

15 0

$3204 XXXX $3204 X X X X

4-14 DSP56800 Family Manual 

Address Generation Unit

4.2.2.5 Index by Offset N: (Rn+N), (SP+N)

The address of the operand is the sum of the contents of the address register Rn or SP and the contents of
the address offset register N. This addition occurs before the operand can be accessed and, therefore,
inserts an extra instruction cycle. The content of N is treated as a two’s-complement sig ned number . The
contents of the Rn and N r egister s are uncha nged by this a ddressing mode. The t ype of ari thmetic (li near or
modulo) used to add N to Rn is determined by M01 for R0 and R1 and is always linear for R2, R3, and SP.
This reference is classified as a memory reference. See Figure 4-7.

Figure 4-7. Address Register Indirect: Indexed by Offset N

$7000

Before Execut i on

X Memory

XXXX

$7000R0

$0003N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

After Execution

$7000R0

$0003N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

Assembler syntax: X:(Rn+N), X:(SP+N)
Additional instruction execution cycles: 1
Additional effective address program words: 0

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0020

Indexed by Offset N Example: MO VE A1,X:(R0+N)

$7000

X Memory

XXXX

15 0

$7003 XXXX $7003 E D C B

+

Addressing Modes

 Address Generation Unit 4-15

4.2.2.6 Index by Short Displacement: (SP-xx), (R2+xx)

This addressing mode contains the 6-bit short immediate index within the instruction word. This field is
always one-extended t o f or m a negative offset when t he SP register is used an d i s a lway s z er o-extended to
form a positive offset when the R2 register is used. The type of arithmetic used to add the short
displacement to R2 or SP is always linear; modulo arithmetic is not allowed. This addressing mode
requires an extra instruction cycle. This reference is classified as an X memory reference. See Figure 4-8.

Figure 4-8. Address Register Indirect: Indexed by Short Displacement

$7000

Before Execution

X Memory

XXXX

$7000R2

$4567N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

After Execution

$7000R2

$4567N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

Assembler syntax: X:(Rn+xx), X:(SP-xx)
Additional instruction execution cycles: 1
Additional effective address program words: 0

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0021

Indexed by Short Di splacement Example: MOVE A1,X:(R2+3)

$7000

X Memory

XXXX

15 0

$7003XXXX $7003 E D C B

+

Short Immediate Value

from the Instruction Word

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Address Generation Unit

4.2.2.7 Index by Long Displacement: (Rn+xxxx), (SP+xx xx)

This addressing mode contains the 16-bit long immediate index within the instruction word. This second
word is treated as a signed two’s-complement value. The type of arithmeti c ( li nea r or modulo) used to add
the long displacement to Rn is dete rmi ned by M01 for R0 and R1 and is alwa ys li nea r for R2, R3, and SP.
This addressing mode requires t wo extra i nstruct ion cycle s. This add ressing mod e is avai lable f or MOVEC
instructions. This reference is classified as an X memory reference. See Figure 4-9.

Figure 4-9. Address Register Indirect: Indexed by Long Displacement

Before Execution

X Memory

$7000R0

$4567N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

After Execution

$7000R0

$4567N

$FFFFM01

EDCBF

A2 A1

A987

A0

A

Assembler syntax: X:(Rn+xxxx ), X:(SP+xxxx)
Additional instruction execution cycles: 2
Additional effective address program words: 1

35 32 31 16 15 0

15 0

35 32 31 16 15 0

15 0 15 0

15 0 15 0

15 0 15 0

AA0022

Indexed by Long Displacement Example : MOV E A1,X:(R0+$10CF)

X Memory

+

Long Immediate Value

from the Instruction Word

15 0

$80CF XXXX $80CFEDCB

$7000XXXX $7000 X X X X

Addressing Modes

 Address Generation Unit 4-17

4.2.3 Immediate Data Modes

The immediate data modes specify the operand directly in a field of the instruction. That is, the operand
value to be used is contained within the instruction word itself (or words themselves). There are two types
of immediate data modes: immediate data, which uses an extension word to contain the operand, and
immediate short data, where the operand is contained within the instruction word. Table 4-6 summarizes
these two modes.

Table 4-6. Addressing Mode—Immediate

Addressing Mode:

Immediate

Notation in the Instruction

Set Summary

Examples

Immediate short data—5, 6, 7-bit
(unsigned and signed)

#xx #14

#<3

Immediate data—16-bit
(unsigned and signed)

#xxxx #$369C

#>1234

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Address Generation Unit

4.2.3.1 Immediate Data: #xxxx

This addressing mode requires one word of instr uction extension. This ad dit io n al word c ont ai ns t h e 16- bi t
immediate data used by the instruction. This reference is classified as a program reference. Examples of
the use and effects of immediate-data mode are shown in Figure 4-10 on page 4-18.

Figure 4-10. Special Addressing: Immediate Data

Assembler syntax: #xxxx
Additional instruction execution cycles: 1
Additional effective address program words: 1

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

A987X

B2 B1

XXXX

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Immediate into 16-Bit Register Example: MOVE #$A9 87,B1

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

12340

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Positive Immediate into 36-Bit Accumulator Example: M OVE #$1234,B

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

A987F

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Negative Immediate into 36-Bit Accumulator Example: M OVE #$A987,B

AA0023

Addressing Modes

 Address Generation Unit 4-19

Figure 4-11. Special Addressing: Immediate Short Data

Assembler syntax: #xx
Additional instruction execution cycles: 0
Additional effective address program words: 0

Before Execution

XXXXN

After Execution

15 0

Immediate Short into 16-Bit Address Register Example: MOVE #$0027, N

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Exec ution

001CX

B2 B1

XXXX

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Immediate Short into 16-Bit Accumulator Register Example: MOVE #$001C,B1

AA0024

$0027N

15 0

Before Execution

XXXXX0

After Execution

15 0

Immediate Short into 16-Bit Data Register Example: MOVE #$FFC6,X0

$FFC6X0

15 0

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

001C0

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Positive Immediate Short into 36-Bit Accumulator Example: MOVE #$001C,B

Before Execution

XXXXX

B2 B1

XXXX

B0

B

After Execution

FFC6F

B2 B1

0000

B0

B

35 32 31 16 15 0 35 32 31 16 15 0

Negative Immediate Short into 36-Bit Accumulator Example: MOVE #$FFC 6,B

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Address Generation Unit

4.2.3.2 Immediate Short Data: #xx

The immediate-short-data operand is located within the instruction operation word. A 6-bit unsigned
positive operan d i s use d f or DO and REP instruction s, and a 7-bit signed oper an d i s used for an immediate
move to an on-core register instruction. This reference is classified as a program reference. See
Figure 4-11 on page 4-19.

4.2.4 Absolute Addressing Modes

Similar to the direct addressin g modes, the absolu te address ing modes sp ecify th e operand val ue within t he
instruction or instruction-extension words. Unlike the direct modes, these values are not used as the
operands themselves, but are interpreted as absolute data memory addresses for the operand values. The
different absolute addressing modes are shown in Table 4-7.

Table 4-7. Addressing Mode—Absolute

Addressing Mode:

Absolute

Notation in the Instruction

Set Summary

Examples

Absolute short address—6 bit
(direct addressing)

X:aa X:$0002

X:<$02

I/O short address—6 bit
(direct addressing)

X:pp X:$00FFE3

X:<<$FFE3

Absolute address—16-bit
(extended addressing)

X:xxxx X:$00F001

X:>$C002