Motorola DSP56367 User Manual

Revision 1.0

Published 02/01

DSP56367UM/D

(Motorola Order Number)

DSP56367

24-Bit Digital Signal Processor

User’s Manual

Motorola, Incorporated
Semiconductor Products Sector
6501 William Cannon Drive West
Austin, TX 78735-8598

This document (and other documents) can be viewed on the World Wide
Web at http://www.motorola-dsp.com.

This manual is one of a set of three documents. You need the following

manuals to have complete product information: Family Manual, User’s
Manual, and Technical Data.

OnCE is a trademark of Motorola, Inc.
 MOTOROLA INC. 2001

Rev. 1.0; published 02/01
Order this document by DSP56367UM/D

Motorola reserves the right to make changes without further notice to any products herein to improve
reliability, funct io n, or d esi gn. Mot oro la does not assume any liability arising out of the appli cation or
use of any product or ci rcui t desc ribed herei n; nei ther doe s it convey a ny lic ense u nder i ts pat ent r ights
nor the rights of others. Motorola products are not authorized for use as components in life support
devices or systems intended for surgical implant into the body or intended to support or sustain life.
Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine
availability and suitability of its product or products for the use intended. Motorola and

 are

registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity
/Affirmative Action Employer.

MOTOROLA iii

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Section 1 DSP56367 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 DSP56300 Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 DSP56367 Audio Processor Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.4 DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4.1 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.4.1.2 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.4.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.4.3 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.4.4 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.4.5 Direct Memory Access (DMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.4.6 PLL-based Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.4.7 JTAG TAP and OnCE Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.4.8 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.4.9 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.5 Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.5.1 Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.5.2 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.5.3 Triple Timer (TEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.5.4 Enhanced Serial Audio Interface (ESAI) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.5.5 Enhanced Serial Audio Interface 1 (ESAI_1). . . . . . . . . . . . . . . . . . . . . . . 1-13

1.5.6 Serial Host Interface (SHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.5.7 Digital Audio Transmitter (DAX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Section 2 Signal/Connection Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Signal Groupings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4 Clock and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.5 External Memory Expansion Port (Port A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.1 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.2 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5.3 External Bus Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.6 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.7 Parallel Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.8 Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.9 Enhanced Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.10 Enhanced Serial Audio Interface_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.11 SPDIF Transmitter Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.12 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.13 JTAG/OnCE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

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Section 3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

3.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

3.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

3.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

3.6 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

3.7 External Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3.8 Phase Lock Loop (PLL) Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

3.9 Reset, Stop, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . .3-9

3.10 External Memory Expansion Port (Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.10.1 SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3.10.2 DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

3.10.3 Arbitration Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

3.11 Parallel Host Interface (HDI08) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

3.12 Serial Host Interface SPI Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-55

3.13 Serial Host Interface (SHI) I2C Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . .3-62

3.13.1 Programming the Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63

3.14 Enhanced Serial Audio Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-66

3.15 Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

3.16 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73

3.17 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-74

3.18 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

Section 4 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

4.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

4.2 Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4.3 Power Consumption Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.4 PLL Performance Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4.4.1 Input (EXTAL) Jitter Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

Section 5 Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5.1 Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5.1.1 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.2 Program ROM Area Reserved for Motorola Use. . . . . . . . . . . . . . . . . . . . .5-12

5.1.3 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.4 Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.1.5 External Memory Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

5.2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

Section 6 Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

6.2 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

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6.2.1 Asynchronous Bus Arbitration Enable (ABE) - Bit 13. . . . . . . . . . . . . . . . . 6-2

6.2.2 Address Attribute Priority Disable (APD) - Bit 14. . . . . . . . . . . . . . . . . . . . 6-2

6.2.3 Address Tracing Enable (ATE) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.4 Patch Enable (PEN) - Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.4 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.6 PLL Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.1 PLL Multiplication Factor (MF0-MF11) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.2 PLL Pre-Divider Factor (PD0-PD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.3 Crystal Range Bit (XTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.4 XTAL Disable Bit (XTLD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.7 Device Identification (ID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.8 JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

6.9 JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

Section 7 General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2.1 Port B Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2.2 Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.3 Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.4 Port E Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.5 Timer/Event Counter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Section 8 Host Interface (HDI08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 HDI08 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2.1 Interface - DSP side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2.2 Interface - Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.3 HDI08 Host Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.4 HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

8.5 HDI08 – DSP-Side Programmer’s Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.5.1 Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.5.2 Host Transmit Data Register (HOTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.5.3 Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7

8.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0. . . . . . . . . . . . . . . . . 8-7

8.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . . . . . . . . . . . . . . 8-8

8.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2 . . . . . . . . . . . . . . . 8-8

8.5.3.4 HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.5.3.5 HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7 8-8

8.5.3.6 HCR Reserved Bits 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

8.5.4 Host Status Register (HSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10

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8.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0. . . . . . . . . . . . . . . . . . . . . .8-10

8.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1. . . . . . . . . . . . . . . . . . .8-11

8.5.4.3 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . . . . . . . . . . . . . . .8-11

8.5.4.4 HSR Host Flags 0,1 (HF0,HF1) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . .8-11

8.5.4.5 HSR Reserved Bits 5-6, 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11

8.5.4.6 HSR DMA Status (DMA) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11

8.5.5 Host Base Address Register (HBAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12

8.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . . . . . . . . . . . . . .8-12

8.5.5.2 HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12

8.5.6 Host Port Control Register (HPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

8.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . . . . . . . . . . . . . .8-13

8.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . . . . . . . . . . . . . .8-13

8.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . . . . . . . . . . . . . .8-13

8.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . . . . . . . . . . . . . .8-13

8.5.6.5 HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . . . . . . . . . . . . . . .8-14

8.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5 . . . . . . . . . . . . . . . . .8-14

8.5.6.7 HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14

8.5.6.8 HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-14

8.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 . . . . . . . . . . . . . . . . . .8-14

8.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . . . . . . . . . . . . . .8-14

8.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10. . . . . . . . . . . . . . .8-15

8.5.6.12 HPCR Host Multiplexed bus (HMUX) Bit 11. . . . . . . . . . . . . . . . . . . .8-15

8.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12. . . . . . . . . . . . . . . . . . . .8-15

8.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . . . . . . . . . . . . . .8-16

8.5.6.15 HPCR Host Request Polarity (HRP) Bit 14. . . . . . . . . . . . . . . . . . . . . .8-16

8.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . . . . . . . . . . . . .8-16

8.5.7 Data direction register (HDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16

8.5.8 Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17

8.5.9 DSP-Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17

8.5.10 Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18

8.6 HDI08 – External Host Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . .8-19

8.6.1 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21

8.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . . . . . . . . . . . . . .8-21

8.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1. . . . . . . . . . . . . . . . . . . . .8-21

8.6.1.3 ICR Double Host Request (HDRQ) Bit 2 . . . . . . . . . . . . . . . . . . . . . . .8-22

8.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

8.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23

8.6.1.6 ICR Host Little Endian (HLEND) Bit 5. . . . . . . . . . . . . . . . . . . . . . . . .8-23

8.6.1.7 ICR Host Mode Control (HM1 and HM0 bits) Bits 5-6 . . . . . . . . . . . .8-23

8.6.1.8 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24

8.6.2 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25

8.6.2.1 CVR Host Vector (HV[6:0]) Bits 0–6 . . . . . . . . . . . . . . . . . . . . . . . . . .8-25

8.6.2.2 CVR Host Command Bit (HC) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25

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8.6.3 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0. . . . . . . . . . . . . . . . . . . 8-26

8.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . . . . . . . . . . . . . 8-26

8.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

8.6.3.4 ISR Host Flag 2 (HF2) Bit 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

8.6.3.5 ISR Host Flag 3 (HF3) Bit 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.6.3.6 ISR Reserved Bits 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.6.3.7 ISR Host Request (HREQ) Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.6.4 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.6.5 Receive Byte Registers (RXH:RXM:RXL) . . . . . . . . . . . . . . . . . . . . . . . . 8-28

8.6.6 Transmit Byte Registers (TXH:TXM:TXL). . . . . . . . . . . . . . . . . . . . . . . . 8-28

8.6.7 Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29

8.6.8 General Purpose INPUT/OUTPUT (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 8-29

8.7 Servicing The Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.7.1 HDI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.7.2 Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.7.3 Servicing Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31

Section 9 Serial Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Serial Host Interface Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.3 Characteristics Of The SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.4 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5 Serial Host Interface Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.5.1 SHI Input/Output Shift Register (IOSR)—Host Side. . . . . . . . . . . . . . . . . . 9-7

9.5.2 SHI Host Transmit Data Register (HTX)—DSP Side . . . . . . . . . . . . . . . . . 9-8

9.5.3 SHI Host Receive Data FIFO (HRX)—DSP Side . . . . . . . . . . . . . . . . . . . . 9-8

9.5.4 SHI Slave Address Register (HSAR)—DSP Side . . . . . . . . . . . . . . . . . . . . 9-9

9.5.4.1 HSAR Reserved Bits—Bits 19, 17–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.5.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18 . . . . . . . . . 9-9

9.5.5 SHI Clock Control Register (HCKR)—DSP Side . . . . . . . . . . . . . . . . . . . . 9-9

9.5.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0. . . . . . . . . . . 9-10

9.5.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 . . . . . . . . . . . . . . . . . . . . . 9-11

9.5.5.3 HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3 . . . . . . . . . . 9-11

9.5.5.4 HCKR Reserved Bits—Bits 23–14, 11. . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.5.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 . . . . . . . . . . . . . . . . . . 9-12

9.5.6 SHI Control/Status Register (HCSR)—DSP Side . . . . . . . . . . . . . . . . . . . 9-13

9.5.6.1 HCSR Host Enable (HEN)—Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

9.5.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . 9-13

9.5.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2. . . . . . . . . . . 9-13

9.5.6.4 HCSR I2C Clock Freeze (HCKFR)—Bit 4 . . . . . . . . . . . . . . . . . . . . . 9-14

9.5.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 . . . . . . . . . . . . . . . . . . . 9-14

9.5.6.6 HCSR Master Mode (HMST)—Bit 6. . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

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9.5.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7. . . . . . . . . . . . . .9-15

9.5.6.8 HCSR Idle (HIDLE)—Bit 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15

9.5.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10. . . . . . . . . . . . . . . .9-16

9.5.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 . . . . . . . . . . . . . . . .9-16

9.5.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12 . . . . . . . . .9-16

9.5.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14 . . . . . . . . . . . .9-17

9.5.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15. . . . . . . . . . . . . . .9-17

9.5.6.14 HCSR Reserved Bits—Bits 23, 18 and 16. . . . . . . . . . . . . . . . . . . . . . .9-17

9.5.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17 . . . . . . . . . . . . . . . . .9-18

9.5.6.16 Host Receive FIFO Full (HRFF)—Bit 19 . . . . . . . . . . . . . . . . . . . . . . .9-18

9.5.6.17 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . . . . . . . . . . . . . .9-18

9.5.6.18 Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-18

9.5.6.19 HCSR Host Busy (HBUSY)—Bit 22. . . . . . . . . . . . . . . . . . . . . . . . . . .9-18

9.6 Characteristics Of The I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19

9.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19

9.6.2 I2C Data Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21

9.7 SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22

9.7.1 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22

9.7.2 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-23

9.7.3 I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-24

9.7.3.1 Receive Data in I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-25

9.7.3.2 Transmit Data In I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-26

9.7.4 I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-27

9.7.4.1 Receive Data in I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28

9.7.4.2 Transmit Data In I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28

9.7.5 SHI Operation During DSP Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-29

Section 10 Enhanced Serial Audio Interface (ESAI). . . . . . . . . . . . . . . . . . . . . . . .10-1

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1

10.2 ESAI Data and Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3

10.2.1 Serial Transmit 0 Data Pin (SDO0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3

10.2.2 Serial Transmit 1 Data Pin (SDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3

10.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) . . . . . . . . . . . . . . . . . .10-3

10.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) . . . . . . . . . . . . . . . . . .10-4

10.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) . . . . . . . . . . . . . . . . . .10-4

10.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) . . . . . . . . . . . . . . . . . .10-5

10.2.7 Receiver Serial Clock (SCKR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5

10.2.8 Transmitter Serial Clock (SCKT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6

10.2.9 Frame Sync for Receiver (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7

10.2.10 Frame Sync for Transmitter (FST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-8

10.2.11 High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . .10-8

10.2.12 High Frequency Clock for Receiver (HCKR) . . . . . . . . . . . . . . . . . . . . . . .10-8

10.3 ESAI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9

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10.3.1 ESAI Transmitter Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . 10-9

10.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 0–7 10-10

10.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-12

10.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13 . 10-12

10.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14–1710-13

10.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 . . . . . . . . . . . . . . . . 10-14

10.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19. . . . . . . . . . . . 10-14

10.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 . 10-14

10.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 . . . . . . . . 10-14

10.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22. . . . . 10-15

10.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 2310-15

10.3.2 ESAI Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0. . . . . . . . . . . . . . . . . . . . 10-15

10.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1. . . . . . . . . . . . . . . . . . . . 10-16

10.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2. . . . . . . . . . . . . . . . . . . . 10-16

10.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3. . . . . . . . . . . . . . . . . . . . 10-17

10.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4. . . . . . . . . . . . . . . . . . . . 10-17

10.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5. . . . . . . . . . . . . . . . . . . . 10-18

10.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6. . . . . . . . . . . . . . . . . 10-18

10.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 . . . . . . . . . . 10-18

10.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-910-19

10.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-1410-21

10.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15. . . . . . . . . . . . . . 10-22

10.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 . . . . . . 10-24

10.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 . . . . . . . . . . . 10-24

10.3.2.14 TCR Reserved Bit - Bits 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24

10.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 . . . . . . . . . . . . 10-24

10.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 . . . . . . . . 10-25

10.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21. . . 10-25

10.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 . . . . . . . . . . . . . . . . . . 10-25

10.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 . . . . . . . . . 10-25

10.3.3 ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . 10-26

10.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0 10-26

10.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 . . . . . . . . . . . . . . . . 10-26

10.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13 . 10-26

10.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-1710-27

10.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18. . . . . . . . . . . . . . . . 10-27

10.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19. . . . . . . . . . . . 10-27

10.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 . 10-28

10.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 . . . . . . . . 10-28

10.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 . . . . 10-28

10.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 2310-29

10.3.4 ESAI Receive Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30

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10.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 . . . . . . . . . . . . . . . . . . . .10-30

10.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 . . . . . . . . . . . . . . . . . . . .10-30

10.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2 . . . . . . . . . . . . . . . . . . . .10-31

10.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 . . . . . . . . . . . . . . . . . . . .10-31

10.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18 . . . . . . . . . . . . . . . . . . . . . . . . . .10-31

10.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 . . . . . . . . . . . . . . . . .10-31

10.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7. . . . . . . . . . .10-31

10.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-910-31

10.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14.10-32

10.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 . . . . . . . . . . . . . .10-33

10.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16. . . . . . .10-33

10.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19. . . . . . . . . . . . .10-33

10.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 . . . . . . . . .10-34

10.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 . . . .10-34

10.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 . . . . . . . . . . . . . . . . . . .10-34

10.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 . . . . . . . . . .10-34

10.3.5 ESAI Common Control Register (SAICR) . . . . . . . . . . . . . . . . . . . . . . . .10-35

10.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0. . . . . . . . . . . . . . . . . . . . . .10-35

10.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1. . . . . . . . . . . . . . . . . . . . . .10-35

10.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2. . . . . . . . . . . . . . . . . . . . . .10-35

10.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23 . . . . . . . . . . . . . . . . . . . . . . . . .10-36

10.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 . . . . . . . . . . . . . .10-36

10.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 . . . . . . . . . .10-36

10.3.5.7 SAICR Alignment Control (ALC) - Bit 8 . . . . . . . . . . . . . . . . . . . . . .10-36

10.3.6 ESAI Status Register (SAISR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-38

10.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . .10-38

10.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . .10-38

10.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . .10-38

10.3.6.4 SAISR Reserved Bits - Bits 3-5, 11-12, 18-23. . . . . . . . . . . . . . . . . . .10-39

10.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6. . . . . . . . . . . . . . . . . .10-39

10.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7. . . . . . . . . . . . . . .10-39

10.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8 . . . . . . . . . . . . . . . .10-39

10.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9 . . . . . . . . . .10-39

10.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10. . . . . . . . . .10-39

10.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13. . . . . . . . . . . . . . . .10-40

10.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14. . . . . . . . . . . . .10-40

10.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15 . . . . . . . . . . . .10-40

10.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 . . . . . .10-40

10.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17. . . . . . .10-41

10.3.7 ESAI Receive Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44

10.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0). . . . . . . . . . . . . . .10-44

10.3.9 ESAI Transmit Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-44

10.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) . . . . . .10-44

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10.3.11 ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45

10.3.12 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . 10-45

10.3.13 Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . . . . . . . . . . . . . 10-46

10.4 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48

10.4.1 ESAI After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48

10.4.2 ESAI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-48

10.4.3 ESAI Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-49

10.4.4 Operating Modes – Normal, Network, and On-Demand . . . . . . . . . . . . . 10-50

10.4.4.1 Normal/Network/On-Demand Mode Selection . . . . . . . . . . . . . . . . . 10-50

10.4.4.2 Synchronous/Asynchronous Operating Modes. . . . . . . . . . . . . . . . . . 10-51

10.4.4.3 Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-51

10.4.4.4 Shift Direction Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52

10.4.5 Serial I/O Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-52

10.5 GPIO - Pins and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-53

10.5.1 Port C Control Register (PCRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-53

10.5.2 Port C Direction Register (PRRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-54

10.5.3 Port C Data register (PDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-55

10.6 ESAI Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-56

10.6.1 Initializing the ESAI Using Individual Reset . . . . . . . . . . . . . . . . . . . . . . 10-56

10.6.2 Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . 10-56

10.6.3 Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . 10-57

Section 11 Enhanced Serial Audio Interface 1 (ESAI_1) . . . . . . . . . . . . . . . . . . . 11-1

11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.2 ESAI_1 Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.1 Serial Transmit 0 Data Pin (SDO0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.2 Serial Transmit 1 Data Pin (SDO1_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1) . . . . . . . . . . . . . 11-3

11.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1) . . . . . . . . . . . . . 11-3

11.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1) . . . . . . . . . . . . . 11-4

11.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1) . . . . . . . . . . . . . 11-4

11.2.7 Receiver Serial Clock (SCKR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.8 Transmitter Serial Clock (SCKT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.9 Frame Sync for Receiver (FSR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.10 Frame Sync for Transmitter (FST_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.3 ESAI_1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.3.1 ESAI_1 Multiplex Control Register (EMUXR) . . . . . . . . . . . . . . . . . . . . . 11-6

11.3.2 ESAI_1 Transmitter Clock Control Register (TCCR_1) . . . . . . . . . . . . . . 11-6

11.3.2.1 TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14–17. . . 11-7

11.3.2.2 TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20 . . . . . . . . . 11-7

11.3.2.3 TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23. . . . . . . . 11-7

11.3.3 ESAI_1 Transmit Control Register (TCR_1) . . . . . . . . . . . . . . . . . . . . . . 11-10

11.3.4 ESAI_1 Receive Clock Control Register (RCCR_1) . . . . . . . . . . . . . . . . 11-10

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11.3.4.1 RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14–17 . .11-11

11.3.4.2 RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20. . . . . . . . .11-11

11.3.4.3 RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23 . . . . . . .11-11

11.3.5 ESAI_1 Receive Control Register (RCR_1) . . . . . . . . . . . . . . . . . . . . . . .11-11

11.3.6 ESAI_1 Common Control Register (SAICR_1) . . . . . . . . . . . . . . . . . . . .11-12

11.3.7 ESAI_1 Status Register (SAISR_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11.3.8 ESAI_1 Receive Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13

11.3.9 ESAI_1 Receive Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13

11.3.10 ESAI_1 Transmit Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13

11.3.11 ESAI_1 Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13

11.3.12 ESAI_1 Time Slot Register (TSR_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14

11.3.13 Transmit Slot Mask Registers (TSMA_1, TSMB_1). . . . . . . . . . . . . . . . .11-14

11.3.14 Receive Slot Mask Registers (RSMA_1, RSMB_1) . . . . . . . . . . . . . . . . .11-15

11.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

11.4.1 ESAI_1 After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

11.5 GPIO - Pins and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

11.5.1 Port E Control Register (PCRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-16

11.5.2 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17

11.5.3 Port E Data register (PDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-18

Section 12 Digital Audio Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

12.2 DAX Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2

12.3 DAX Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3

12.4 DAX Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4

12.5 DAX Internal Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12.5.1 DAX Audio Data Register (XADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12.5.2 DAX Audio Data Buffers (XADBUFA / XADBUFB) . . . . . . . . . . . . . . . .12-6

12.5.3 DAX Audio Data Shift Register (XADSR) . . . . . . . . . . . . . . . . . . . . . . . . .12-6

12.5.4 DAX Non-Audio Data Register (XNADR) . . . . . . . . . . . . . . . . . . . . . . . . .12-6

12.5.4.1 DAX Channel A Validity (XVA)—Bit 10. . . . . . . . . . . . . . . . . . . . . . .12-6

12.5.4.2 DAX Channel A User Data (XUA)—Bit 11 . . . . . . . . . . . . . . . . . . . . .12-6

12.5.4.3 DAX Channel A Channel Status (XCA)—Bit 12 . . . . . . . . . . . . . . . . .12-7

12.5.4.4 DAX Channel B Validity (XVB)—Bit 13 . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.4.5 DAX Channel B User Data (XUB)—Bit 14 . . . . . . . . . . . . . . . . . . . . .12-7

12.5.4.6 DAX Channel B Channel Status (XCB)—Bit 15. . . . . . . . . . . . . . . . . .12-7

12.5.4.7 XNADR Reserved Bits—Bits 0-9, 16–23 . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.5 DAX Non-Audio Data Buffer (XNADBUF) . . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.6 DAX Control Register (XCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7

12.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0 . . . . . . . .12-8

12.5.6.2 Underrun Error Interrupt Enable (XUIE)—Bit 1 . . . . . . . . . . . . . . . . . .12-8

12.5.6.3 Block Transferred Interrupt Enable (XBIE)—Bit 2. . . . . . . . . . . . . . . .12-8

12.5.6.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4 . . . . . . . . . . . . . . . . . .12-8

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12.5.6.5 DAX Start Block (XSB)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.5.6.6 XCTR Reserved Bits—Bits 6-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.5.7 DAX Status Register (XSTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

12.5.7.1 DAX Audio Data Register Empty (XADE)—Bit 0 . . . . . . . . . . . . . . . 12-9

12.5.7.2 DAX Transmit Underrun Error Flag (XAUR)—Bit 1 . . . . . . . . . . . . . 12-9

12.5.7.3 DAX Block Transfer Flag (XBLK)—Bit 2 . . . . . . . . . . . . . . . . . . . . . 12-9

12.5.7.4 XSTR Reserved Bits—Bits 3–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.5.8 DAX Parity Generator (PRTYG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.5.9 DAX Biphase Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.5.10 DAX Preamble Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.5.11 DAX Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.5.12 DAX State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.6 DAX Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.6.1 Initiating A Transmit Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.6.2 Audio Data Register Empty Interrupt Handling . . . . . . . . . . . . . . . . . . . . 12-13

12.6.3 Block Transferred Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.6.4 DAX operation with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.6.5 DAX Operation During Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15

12.7 GPIO (PORT D) - Pins and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15

12.7.1 Port D Control Register (PCRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.7.2 Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.7.3 Port D Data Register (PDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17

Section 13 Timer/ Event Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2 Timer/Event Counter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2.1 Timer/Event Counter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.2.2 Individual Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.3 Timer/Event Counter Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.3.1 Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.3.2 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.3.2.1 TPLR Prescaler Preload Value PL[20:0] Bits 20–0 . . . . . . . . . . . . . . . 13-5

13.3.2.2 TPLR Prescaler Source PS[1:0] Bits 22-21 . . . . . . . . . . . . . . . . . . . . . 13-5

13.3.2.3 TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.3.3 Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.3.3.1 TPCR Prescaler Counter Value PC[20:0] Bits 20–0. . . . . . . . . . . . . . . 13-6

13.3.3.2 TPCR Reserved Bits 23–21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.3.4 Timer Control/Status Register (TCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

13.3.4.1 TCSR Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7

13.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1. . . . . . . . . . . . . 13-7

13.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . . . . . . . . 13-7

13.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4–7 . . . . . . . . . . . . . . . . . . . . . . . 13-7

13.3.4.5 TCSR Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

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13.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . . . . . . . .13-10

13.3.4.7 TCSR Direction (DIR) Bit 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-10

13.3.4.8 TCSR Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11

13.3.4.9 TCSR Data Output (DO) Bit 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-11

13.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . . . . . . . .13-11

13.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20. . . . . . . . . . . . . . . . . . . . . .13-11

13.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . .13-12

13.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) . . . . . . . . . . . . . .13-12

13.3.5 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-12

13.3.6 Timer Compare Register (TCPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13

13.3.7 Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13

13.4 Timer Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-13

13.4.1 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14

13.4.1.1 Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-14

13.4.1.2 Timer Pulse (Mode 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-15

13.4.1.3 Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-16

13.4.1.4 Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17

13.4.2 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-17

13.4.2.1 Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-18

13.4.2.2 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . .13-18

13.4.2.3 Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . .13-19

13.4.2.4 Measurement Capture (Mode 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-20

13.4.3 Pulse Width Modulation (PWM, Mode 7). . . . . . . . . . . . . . . . . . . . . . . . .13-21

13.4.4 Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-22

13.4.4.1 Watchdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-22

13.4.4.2 Watchdog Toggle (Mode 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-23

13.4.5 Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24

13.4.6 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24

13.4.6.1 Timer Behavior during Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24

13.4.6.2 Timer Behavior during Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24

13.4.7 DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-24

Section 14 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.1 Pin-out and Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.1.1 LQFP Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1

14.1.2 LQFP Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-7

14.2 Ordering Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8

Appendix A Bootstrap ROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1 DSP56367 Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

MOTOROLA xv

CONTENTS

Paragraph
Number

Title

Page

Number

Appendix B Equates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C JTAG BSDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1

Appendix D Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1.1 Peripheral Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1.2 Interrupt Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1.3 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1.4 Host Interface Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.1.5 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-1

D.2 Internal I/O Memory MAp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-2

D.3 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7

D.4 Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-10

D.5 Host Interface—Quick Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-12

D.6 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-15

Appendix E Power Consumption Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1

Appendix F IBIS Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

xvi MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

MOTOROLA xvii

List of Figures

Figure
Number

Title

Page

Number

1-1 DSP56367 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

3-1 External Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3-2 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

3-3 External Fast Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

3-4 External Interrupt Timing (Negative Edge-Triggered). . . . . . . . . . . . . . . .3-15

3-5 Operating Mode Select Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15

3-6 Recovery from Stop State Using IRQA Interrupt Service . . . . . . . . . . . . .3-15

3-7 Recovery from Stop State Using IRQA Interrupt Service . . . . . . . . . . . . .3-16

3-8 External Memory Access (DMA Source) Timing . . . . . . . . . . . . . . . . . . .3-16

3-9 SRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20

3-10 SRAM Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

3-11 DRAM Page Mode Wait States Selection Guide . . . . . . . . . . . . . . . . . . . .3-22

3-12 DRAM Page Mode Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31

3-13 DRAM Page Mode Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32

3-14 DRAM Out-of-Page Wait States Selection Guide . . . . . . . . . . . . . . . . . . .3-33

3-15 DRAM Out-of-Page Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42

3-16 DRAM Out-of-Page Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-43

3-17 DRAM Refresh Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44

3-18 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

3-19 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram . . . . . . . . . .3-49

3-21 Read Timing Diagram, Non-Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . .3-50

3-22 Write Timing Diagram, Non-Multiplexed Bus. . . . . . . . . . . . . . . . . . . . . .3-51

3-23 Read Timing Diagram, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . .3-52

3-24 Write Timing Diagram, Multiplexed Bus. . . . . . . . . . . . . . . . . . . . . . . . . .3-53

3-25 Host DMA Write Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54

3-26 Host DMA Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54

3-27 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-58

3-28 SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-59

3-29 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

3-30 SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61

3-31 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-65

3-32 ESAI Transmitter Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-69

3-33 ESAI Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70

3-34 ESAI HCKT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71

3-35 ESAI HCKR Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71

xviii MOTOROLA

List of Figures

Figure
Number

Title

Page

Number

3-36 Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

3-37 TIO Timer Event Input Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73

3-38 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

3-39 Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

3-40 Boundary Scan (JTAG) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . .3-76

3-41 Test Access Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-76

5-1 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0 . . . . . . . . . . . . . . . .5-4

5-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0 . . . . . . . . . . . . . . . .5-4

5-3 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0. . . . . . . . . . . . . . . . . .5-5

5-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-5

5-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-6

5-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-6

5-7 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-7

5-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0 . . . . . . . . . . . . . . . . .5-7

5-9 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1 . . . . . . . . . . . . . . . .5-8

5-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1 . . . . . . . . . . . . . . . .5-8

5-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . .5-9

5-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . .5-9

5-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . .5-10

5-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-10

5-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-11

5-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . .5-11

6-1 Interrupt Priority Register P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

6-2 Interrupt Priority Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

8-1 HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5

8-2 Host Control Register (HCR) (X:$FFFFC2) . . . . . . . . . . . . . . . . . . . . . . . .8-7

8-3 Host Status Register (HSR) (X:FFFFC3). . . . . . . . . . . . . . . . . . . . . . . . . .8-10

8-5 Self Chip Select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12

8-4 Host Base Address Register (HBAR) (X:$FFFFC5) . . . . . . . . . . . . . . . . .8-12

8-6 Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . . . . . . . .8-13

8-7 Single strobe bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15

8-8 Dual strobes bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15

8-9 Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . . . . . . . .8-16

8-10 Host Data Register (HDR) (X:$FFFFC9). . . . . . . . . . . . . . . . . . . . . . . . . .8-17

8-11 HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-19

8-12 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21

8-13 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25

8-14 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-26

MOTOROLA xix

List of Figures

Figure
Number

Title

Page

Number

8-15 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8-16 HDI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-31

9-1 Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

9-2 SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4

9-3 SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5

9-4 SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6

9-5 SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8

9-6 SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10

9-7 I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-19

9-8 I2C Start and Stop Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20

9-9 Acknowledgment on the I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-20

9-10 I2C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .9-21

9-11 I2C Bus Protocol For Host Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22

10-1 ESAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2

10-2 TCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-10

10-3 ESAI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . .10-11

10-4 ESAI Frame Sync Generator Functional Block Diagram. . . . . . . . . . . . .10-13

10-5 TCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-15

10-6 Normal and Network Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-20

10-7 Frame Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-23

10-8 RCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-26

10-9 RCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-30

10-10 SAICR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-35

10-11 SAICR SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-37

10-12 SAISR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-38

10-13 ESAI Data Path Programming Model ([R/T]SHFD=0) . . . . . . . . . . . . . .10-42

10-14 ESAI Data Path Programming Model ([R/T]SHFD=1) . . . . . . . . . . . . . .10-43

10-15 TSMA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45

10-16 TSMB Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-45

10-17 RSMA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47

10-18 RSMB Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-47

10-19 PCRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54

10-20 PRRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54

10-21 PDRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-55

11-1 ESAI_1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2

11-2 EMUXR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6

11-3 TCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7

xx MOTOROLA

List of Figures

Figure
Number

Title

Page

Number

11-4 ESAI_1 Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . .11-8

11-5 ESAI_1 Frame Sync Generator Functional Block Diagram. . . . . . . . . . . .11-9

11-6 TCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10

11-7 RCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-10

11-8 RCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11

11-9 SAICR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11-10 SAISR_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12

11-11 TSMA_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14

11-12 TSMB_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-14

11-13 RSMA_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15

11-14 RSMB_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15

11-15 PCRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17

11-16 PRRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17

11-17 PDRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-18

12-1 Digital Audio Transmitter (DAX) Block Diagram. . . . . . . . . . . . . . . . . . .12-2

12-2 DAX Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5

12-3 DAX Relative Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10

12-4 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11

12-5 Clock Multiplexer Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12

12-6 Examples of data organization in memory . . . . . . . . . . . . . . . . . . . . . . . .12-15

12-7 Port D Control Register (PCRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16

12-8 Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16

12-9 Port D Data Register (PDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-18

13-1 Timer/Event Counter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-2

13-2 Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3

13-3 Timer Module Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-4

13-4 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . .13-5

13-5 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . .13-6

14-1 144-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-2

14-2 DSP56367 144-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-7

D-1 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-16

D-2 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17

D-3 Interrupt Priority Register–Core (IPR–C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18

D-4 Interrupt Priority Register – Peripherals (IPR–P). . . . . . . . . . . . . . . . . . . . . . . . . D-19

D-5 Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20

D-6 Host Receive and Host Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . D-21

D-7 Host Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-22

D-8 Host Base Address and Host Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-23

MOTOROLA xxi

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Figure
Number

Title

Page

Number

D-9 Host Interrupt Control and Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-24

D-10 Host Interrupt Vector and Command Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-25

D-11 Host Receive and Transmit Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-26

D-12 SHI Slave Address and Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . D-27

D-13 SHI Transmit and Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-28

D-14 SHI Host Control/Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-29

D-15 ESAI Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30

D-16 ESAI Transmit Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-31

D-17 ESAI Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-32

D-18 ESAI Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33

D-19 ESAI Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-34

D-20 ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35

D-21 ESAI_1 Multiplex Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-36

D-22 ESAI_1 Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-37

D-23 ESAI_1 Transmit Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-38

D-24 ESAI_1 Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-39

D-25 ESAI_1 Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-40

D-26 ESAI_1 Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-41

D-27 ESAI_1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-42

D-28 DAX Non-Audio Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43

D-29 DAX Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44

D-30 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) . . . . . . . . . D-45

D-31 Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-46

D-32 Timer Load, Compare and Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-47

D-33 GPIO Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-48

D-34 GPIO Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-49

D-35 GPIO Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-50

D-36 GPIO Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-51

xxii MOTOROLA

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Page

Number

MOTOROLA xxiii

List of Tables

Table
Number

Title

Page

Number

2-1 DSP56367 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

2-3 Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

2-4 Clock and PLL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

2-5 External Address Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

2-6 External Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

2-7 External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

2-8 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

2-9 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

2-10 Serial Host Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

2-11 Enhanced Serial Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . .2-15

2-12 Enhanced Serial Audio Interface_1 Signals . . . . . . . . . . . . . . . . . . . . . . .2-19

2-13 Digital Audio Interface (DAX) Signals . . . . . . . . . . . . . . . . . . . . . . . . . .2-20

2-14 Timer Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21

2-15 JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21

3-1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

3-2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2

3-3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

3-4 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

3-5 Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

3-6 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

3-7 Reset, Stop, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . .3-9

3-8 SRAM Read and Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

3-9 DRAM Page Mode Timings, One Wait State (Low-Power Apps). . . . . .3-23

3-10 DRAM Page Mode Timings, Two Wait States . . . . . . . . . . . . . . . . . . . .3-24

3-11 DRAM Page Mode Timings, Three Wait States . . . . . . . . . . . . . . . . . . .3-27

3-12 DRAM Page Mode Timings, Four Wait States . . . . . . . . . . . . . . . . . . . .3-29

3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States . . . . . . . . .3-33

3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States. . . . . . . . .3-35

3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States. . . . . . . .3-38

3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States . . . . . . .3-39

3-17 Asynchronous Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

3-18 Host Interface (HDI08) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

3-19 Serial Host Interface SPI Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . .3-55

3-20 SHI I2C Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62

3-21 SCL Serial Clock Cycle (T

SCL

) Generated as Master . . . . . . . . . . . . . . .3-64

3-22 Enhanced Serial Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . .3-66

3-23 Digital Audio Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

3-24 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73

3-25 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-74

3-26 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

5-1 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

5-2 On-chip RAM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

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5-3 On-chip ROM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

5-4 Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

6-1 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2

6-2 DSP56367 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5

6-3 DSP56367 Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6

6-4 Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

6-5 Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . .6-9

6-6 DSP56367 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10

6-7 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13

6-8 Identification Register Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15

6-9 JTAG Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . .6-15

6-10 DSP56367 BSR Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15

8-1 HDI08 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8-2 Strobe Signals Support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8-3 Host request support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

8-4 HDI08 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8

8-5 HDM[2:0] Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9

8-6 HDR and HDDR Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-17

8-7 DSP-Side Registers after Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-18

8-8 HDI08 Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-20

8-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00) . . . . . .8-22

8-10 TREQ RREQ DMA Mode (HM1¼0 or HM0¼0) . . . . . . . . . . . . . . . . . .8-22

8-11 HDRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22

8-12 Host Mode Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23

8-13 INIT Command Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24

8-14 Host Request Status (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-27

8-15 Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-29

9-1 SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9-2 SHI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7

9-3 SHI Noise Reduction Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12

9-4 SHI Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13

9-5 HREQ Function In SHI Slave Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15

9-6 HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16

10-1 Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . . .10-6

10-2 Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7

10-3 Transmitter High Frequency Clock Divider. . . . . . . . . . . . . . . . . . . . . .10-14

10-4 Transmit Network Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-19

10-5 ESAI Transmit Slot and Word Length Selection . . . . . . . . . . . . . . . . . .10-21

10-6 Receiver High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . . .10-27

10-7 SCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28

10-8 FSR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29

10-9 HCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-29

10-10 ESAI Receive Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . .10-32

MOTOROLA xxv

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Number

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10-11 ESAI Receive Slot and Word Length Selection. . . . . . . . . . . . . . . . . . .10-32

10-12 PCRC and PRRC Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . .10-54

11-1 EMUXR ESAI/ESAI_1 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .11-6

11-2 Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7

11-3 Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . .11-11

11-4 PCRE and PRRE Bits Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . .11-17

12-1 DAX Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4

12-2 DAX Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4

12-3 Clock Source Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-8

12-4 Preamble Bit Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11

12-5 Examples of DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14

12-6 DAX Port GPIO Control Register Functionality . . . . . . . . . . . . . . . . . .12-17

13-1 Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6

13-2 Timer Control Bits for Timer 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-8

13-3 Timer Control Bits for Timers 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . .13-9

13-4 Inverse Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-9

14-1 Signal Identification by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3

14-2 Signal Identification by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . .14-5

D-1 Internal I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2

D-2 DSP56367 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7

D-3 Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . D-10

D-4 HDI08 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12

D-20 EMUXR ESAI/ESAI_1 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . D-36

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MOTOROLA About This Guide i

Preface

This manual describes the DSP56367 24-bit digital signal processor (DSP), its memory, operating
modes, and peripheral modules. The DSP56367 is a member of the DSP56300 family of
programmable CMOS DSPs. Changes in core functionality specific to the DSP56367 are also
described in this manual.

Note: This document contains information on a new product.

Specifications and information herein are subject to change without notice.

The DSP56367 is targeted to applications that require digital audio compression and
decompression, sound field processing, acoustic equalization, and other digital audio algorithms.

This manual is intended to be used with the following publication:

• The

DSP56300 Family Manual (DSP56300FM/AD),

which describes the CPU, core

programming models, and instruction set details.

This document, as well as Motorola’s DSP development tools, can be obtained through a local
Motorola Semiconductor Sales Office or authorized distributor.

To receive the latest information on this DSP, a ccess the Motorola DS P home pa ge at the address
given on the front cover of this document.

This manual contains the following sections and appendices.

SECTION 1—DSP56367 OVERVIEW

– Provides a brief description of the DSP56367, including a features list and block

diagram. Lists related documentation needed to use this chip and describes the
organization of this manual.

SECTION 2—SIGNAL/CONNECTION DESCRIPTIONS

– Describes the signals on the DSP56367 pins and how these signals are grouped into

interfaces.

SECTION 3—SPECIFICATIONS

– Describes the DSP56367 maximum ratings, AC specifications, DC specifications,

thermal specifications, clock operational specifications and timings.

ii About This Guide MOTOROLA

SECTION 4—DESIGN CONSIDERATIONS

– Describes thermal, electrical, and power consumption issues, as wells PLL

performance issues and input jitter requirements for the DSP56367.

SECTION 5—MEMORY CONFIGURATION

– Describes data and program and memory maps for the DSP56367.

SECTION 6—CORE CONFIGURATION

– Describes the registers used to configure the DSP56300 core when programming the

DSP56367, in particular the interrupt vector locations and the operation of the
interrupt priority registers. Explains the operating modes and how they affect the
processor’s program and data memories.

SECTION 7—GENERAL PURPOSE INPUT/OUTPUT (GPIO)

– Describes the DSP56367 GPIO capability and the programming model for the GPIO

signals (operation, registers, and control).

SECTION 8— HOST INTERFACE (HDI08)

– Describes the HDI08 parallel host interface.

SECTION 9—SERIAL HOST INTERFACE (SHI)

– Describes the serial input/output interface providing a path for communication and

program/coefficient data transfers between the DSP and an external host processor.
The SHI can also communicate with other serial peripheral devices.

SECTION 10—ENHANCED SERIAL AUDIO INTERFACE (ESAI)

– Describes one of the full-duplex serial port for serial communication with a variety of

serial devices.

SECTION 11—ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)

– Describes the second full-duplex serial port for serial communication with a variety of

serial devices.

SECTION 12—DIGITAL AUDIO TRANSMITTER (DAX)

– Describes the full-duplex serial port for serial communication with a variety of serial

devices.

SECTION 13—TRIPLE TIMER MODULE (TEC)

– Describes the internal timer/event counter in the DSP56367.

SECTION 14—PACKAGE DESCRIPTION

– Describes the available package for the DSP56367, including diagrams of the package

pinouts and tables describing how the signals are allocated for the package.

APPENDIX A—BOOTSTRAP PROGRAM

– Lists the bootstrap code used for the DSP56367.

APPENDIX B—EQUATES

MOTOROLA About This Gui de iii

– Lists equates for the DSP56367.

APPENDIX C—JTAG/BSDL LISTING

– Provides the BSDL listing for the DSP56367.

APPENDIX D—PROGRAMMING REFERENCE

– Lists peripheral addresses, interrupt addresses, and interrupt priorities for the

DSP56367. Contains programming sheets listing the contents of the major DSP56367
registers for programmer reference.

APPENDIX E—POWER CONSUMPTION BENCHMARK

– Describes the benchmark program that permits evaluation of DSP power usage in a

test situation.

APPENDIX F—IBIS MODEL

– Describes the IBIS model used for the DSP56367.

Manual Conventions

The following conventions are used in this manual:

• Bits within registers are always listed from most significant bit (MSB) to least significant
bit (LSB).

• When several related bits are discussed, they are referenced as AA[n:m], where n>m. For
purposes of description, the bits are presented as if they are contiguous within a register.
However, this is not always the case. Refer to the programming model diagrams or to the
programmer’s sheets to see the exact location of bits within a register.

• When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its
value is 0.

• The word “assert” means that a high true (active high) signal is pulled high to VCC or that
a low true (active low) signal is pulled low to ground. The word “deassert” means that a
high true signal is pulled low to ground or that a low true signal is pulled high to VCC.

High True/Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

PIN

1

True Asserted

Ground

2

PIN False Deasserted

V

CC

3

PIN True Asserted V

CC

PIN False Deasserted Ground

iv About This Guide MOTOROLA

• Pins or signals that are asserted low (made active when pulled to ground)
– In text, have an overbar (e.g., RESET is asserted low).
– In code examples, have a tilde in front of their names. In example below, line 3 refers

to the SS0 pin (shown as ~SS0).

• Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g.,
HA1–HA8).

• Code examples are displayed in a monospaced font, as shown below:

• Hex values are indicated with a dollar sign ($) preceding the hex value, as follows:
$FFFFFF is the X memory address for the core interrupt priority register (IPR-C).

• The word “reset” is used in four different contexts in this manual:
– the reset signal, written as “RESET,”
– the reset instruction, written as “RESET,”
– the reset operating state, written as “Reset,” and
– the reset function, written as “reset.”

Note: 1. PIN is a generic term for any pin on the chip.

2. Ground is an acceptable low voltage level. See the appropriate data sheet for the
range of acceptable low voltage levels (typically a TTL logic low).

3. V

CC

is an acceptable high voltage level. See the appropriate data sheet for the

range of acceptable high voltage levels (typically a TTL logic high).

Example Sample Code Listing

BFSET #$0007,X:PCC; Configure: line 1

; MISO0, MOSI0, SCK0 for SPI master line 2

; ~SS0 as PC3 for GPIO line 3

High True/Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

MOTOROLA DSP56367 1-1

SECTION 1
DSP56367 OVERVIEW

1.1 INTRODUCTION

This manual describes the DSP56367 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56367 is a member of the DSP56300
family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require
digital audio compression/decompression, sound field processing, acoustic equalization and
other digital audio algorithms. The DSP56367 offers 150 million instructions per second
(MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second
(MIPS) using an internal 100 MHz clock at 1.5 V.

Changes in core functionality specific to the DSP56367 are also described in this manual. See
Figure 1-1 for the block diagram of the DSP56367.

MOTOROLA DSP56367 1-2

Figure 1-1 DSP56367 Block Diagram

1.2 DSP56300 CORE DESCRIPTION

The DSP56367 uses the DSP56300 core, a high-performance, single clock cycle per
instruction engine that provides up to twice the performance of Motorola’s popular DSP56000
core family while retaining code compatibility with it.

The DSP56300 core family offers a new level of performance in speed and power, provided
by its rich instruction set and low power dissipation, thus enabling a new generation of
wireless, telecommunications, and multimedia products. For a description of the DSP56300

CLOCK

GENERAT

INTERNAL

DATA

BUS

EXTAL

PROGRAM

RAM
/INSTR.
CACHE
3K x 24

PROGRAM

ROM

40K x 24

Bootstrap

PROGRAM

INTERRUPT

CONTROLLER

PROGRAM

DECODE

CONTROLLE

PROGRAM

ADDRESS

GENERATOR

YAB
XAB
PAB

YDB
XDB
PDB
GDB

MODA/IRQA
MODB/IRQB

DATA ALU

24X24+56->56-BIT MAC

TWO 56-BIT ACCUMULATORS

BARREL SHIFTER

MODC/IRQC

PLL

OnCE™

HOST

INTER-

FACE

DAX

(SPDIF Tx.)

INTER-FA

CE

4

16

X MEMORY

RAM

13K X 24

ROM

32K x 24

Y MEMORY

RAM

7K X 24

ROM

8K x 24

DDB

DAB

SIX CHANNELS

DMA UNIT

MEMORY EXPANSION AREA

PERIPHERAL

YM_EB

XM_EB

PM_EB

PIO_EB

24 BITS BUS

EXPANSION AREA

JTAG

4

5

RESET

POWER

MNGMNT

PINIT/NMI

2

TRIPLE

TIMER

1

MODD/IRQD

DRAM &

SRAM BUS

INTERFACE

&

I - CACHE

EXTERNAL
ADDRESS

BUS

SWITCH

EXTERNAL

DATA BUS

SWITCH

ADDRESS

10

DATA

CONTROL

24

18

ESAI

INTER-

FACE

8

6

ESAI_1

ADDRESS

GENERATION

UNIT

24-BIT

DSP56300

Core

SHI

INTER-

FACE

DSP56367 Overview

DSP56300 Core Description

MOTOROLA DSP56367 1-3

core, see Section 1 DSP56300 Core Functional Blocks on page 1-5. Significant
architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit
addressing, an instruction cache, and direct memory access (DMA).

The DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements such as memories and
peripherals. New modules may be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. Refer to Section 5 -
Memory Configuration.

Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and
peripheral features are described in this manual.

• DSP56300 modular chassis
– 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal

logic supply (QVCCL) of 1.8V.

– 100 Million Instr uctions Per Seco nd (MIPS) with a 100 MHz clock at inte rnal logic supply

(QVCCL) of 1.5V.

– Object Code Compatible with the 56K core.
– Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter.

16-bit arithmetic support.

– Program Control with position independent code support and instruction cache

support.
– Six-channel DMA controller.
– PLL based clocking with a wide range of frequency multiplications (1 to 4096),

predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces

clock noise.
– Internal address tracing support and OnCE for Hardware/Software debugging.
– JTAG port.
– Very low-power CMOS design, fully static design with operating frequencies

down to DC.
– STOP and WAIT low-power standby modes.

• On-chip Memory Configuration
– 7Kx24 Bit Y-Data RAM and 8Kx24 Bit Y-Data ROM.
– 13Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.

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DSP56367 Overview
DSP56367 Audio Processor Architecture

– 40Kx24 Bit Program ROM.
– 3Kx24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM

may be used as Instruction Cache or for Program ROM patching.

– 2Kx24 Bit from Y Data RAM and 5Kx24 Bit from X Data RAM can be switched

to Program RAM resulting in up to 10Kx24 Bit of Program RAM.

• Off-chip memory expansion
– External Memory Expansion Port.
– Off-chip expansion up to two 16M x 24-bit word of Data memory.
– Off-chip expansion up to 16M x 24-bit word of Program memory.
– Simultaneous glueless interface to SRAM and DRAM.

• Peripheral modules
– Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or

slave. I2S, Sony, AC97, network and other programmable protocols.

– Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters,

master or slave. I2S, Sony, AC97, network and other programmable protocols
The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT
support HCKR and HCKT (high frequency clocks)

– Serial Host Interface (SHI): SPI and I2C protocols, multi master capability,

10-word receive FIFO, support for 8, 16 and 24-bit words.
– Byte-wide parallel Host Interface (HDI08) with DMA support.
– Triple Timer module (TEC).
– Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the

SPDIF, IEC958, CP-340 and AES/EBU digital audio formats.
– Pins of unused peripherals (except SHI) may be programmed as GPIO lines.

• 144-pin plastic LQFP package.

1.3 DSP56367 AUDIO PROCESSOR ARCHITECTURE

This section defines the DSP56367 audio processor architecture. The audio processor is
composed of the following units:

• The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program
Controller, Instruction-Cache Controller, DMA Controller, PLL-based clock
oscillator, Memory Module Interface, Peripheral Module Interface and the On-Chip

DSP56367 Overview

DSP56300 Core Functional Blocks

MOTOROLA DSP56367 1-5

Emulator (OnCE). The DSP56300 core is described in the document DSP56300 24-Bit
Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD.

• Memory modules.

• Peripheral modules. The peripheral modules are defined in the following sections.

Memory sizes in the block diagram are defaults. Memory may be differently partitioned,
according to the memory mode of the chip. See Section 1 On-Chip Memory on page 1-10
for more details about memory size.

1.4 DSP56300 CORE FUNCTIONAL BLOCKS

The DSP56300 core provides the following functional blocks:

• Data arithmetic logic unit (Data ALU)

• Address generation unit (AGU)

• Program control unit (PCU)

• Bus interface unit (BIU)

• DMA controller (with six channels)

• Instruction cache controller

• PLL-based clock oscillator

• OnCE module

• JTAG TAP

• Memory

In addition, the DSP56367 provides a set of on-chip peripherals, described in Section 1
Peripheral Overview on page 1-11.

1.4.1 DATA ALU

The Data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. The components of the Data ALU are as follows:

• Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)

• Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)

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DSP56367 Overview
DSP56300 Core Functional Blocks

• Conditional ALU instructions

• 24-bit or 16-bit arithmetic support under software control

• Four 24-bit input general purpose registers: X1, X0, Y1, and Y0

• Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general purpose, 56-bit accumulators (A and B), accumulator shifters

• Two data bus shifter/limiter circuits

1.4.1.1 Data ALU Registers

The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y
memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit
arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16,
32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The
results of all Data ALU operations are stored in an accumulator.

All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a
new instruction can be initiated in every clock, yielding an effective execution rate of one
instruction per clock cycle. The destination of every arithmetic operation can be used as a
source operand for the immediately following arithmetic operation without a time penalty
(i.e., without a pipeline stall).

1.4.1.2 Multiplier-Accumulator (MAC)

The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. In the case of arithmetic instructions, the
unit accepts as many as three input operands and outputs one 56-bit result of the following
form- Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between
two’s-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored
as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is
performed if specified.

1.4.2 ADDRESS GENERATION UNIT (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers used to generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.

DSP56367 Overview

DSP56300 Core Functional Blocks

MOTOROLA DSP56367 1-7

The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has
four sets of register triplets, and each register triplet is composed of an address register, an
offset register, and a modifier register. The two Address ALUs are identical. Each contains a
24-bit full adder (called an offset adder).

A second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs. The
only difference between them is that the carry propagates in opposite directions. Test logic
determines which of the three summed results of the full adders is output.

Each Address ALU can update one address register from its respective address register file
during one instruction cycle. The contents of the associated modifier register specifies the
type of arithmetic to be used in the address register update calculation. The modifier value is
decoded in the Address ALU.

1.4.3 PROGRAM CONTROL UNIT (PCU)

The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and
exception processing. The PCU implements a seven-stage pipeline and controls the different
processing states of the DSP56300 core. The PCU consists of the following three hardware
blocks:

• Program decode controller (PDC)

• Program address generator (PAG)

• Program interrupt controller (PIC)

The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all
signals necessary for pipeline control. The PAG contains all the hardware needed for program
address generation, system stack, and loop control. The PIC arbitrates among all interrupt
requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD,
and NMI), and generates the appropriate interrupt vector address.

PCU features include the following:

• Position independent code support

• Addressing modes optimized for DSP applications (including immediate offsets)

• On-chip instruction cache controller

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DSP56367 Overview
DSP56300 Core Functional Blocks

• On-chip memory-expandable hardware stack

• Nested hardware DO loops

• Fast auto-return interrupts

The PCU implements its functions using the following registers:

• PC—program counter register

• SR—Status register

• LA—loop address register

• LC—loop counter register

• VBA—vector base address register

• SZ—stack size register

• SP—stack pointer

• OMR—operating mode register

• SC—stack counter register

The PCU also includes a hardware system stack (SS).

1.4.4 INTERNAL BUSES

To provide data exchange between blocks, the following buses are implemented:

• Peripheral input/output expansion bus (PIO_EB) to peripherals

• Program memory expansion bus (PM_EB) to program memory

• X memory expansion bus (XM_EB) to X memory

• Y memory expansion bus (YM_EB) to Y memory

• Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and
PCU as well as the memory-mapped registers in the peripherals

• DMA data bus (DDB) for carrying DMA data between memories and/or peripherals

• DMA address bus (DAB) for carrying DMA addresses to memories and peripherals

• Program Data Bus (PDB) for carrying program data throughout the core

• X memory Data Bus (XDB) for carrying X data throughout the core

• Y memory Data Bus (YDB) for carrying Y data throughout the core

DSP56367 Overview

DSP56300 Core Functional Blocks

MOTOROLA DSP56367 1-9

• Program address bus (PAB) for carrying program memory addresses throughout the
core

• X memory address bus (XAB) for carrying X memory addresses throughout the core

• Y memory address bus (YAB) for carrying Y memory addresses throughout the core

All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1-1.

1.4.5 DIRECT MEMORY ACCESS (DMA)

The DMA block has the following features:

• Six DMA channels supporting internal and external accesses

• One-, two-, and three-dimensional transfers (including circular buffering)

• End-of-block-transfer interrupts

• Triggering from interrupt lines and all peripherals

1.4.6 PLL-BASED CLOCK OSCILLATOR

The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator (CLKGEN), which performs low-power division and clock pulse generation.
PLL-based clocking:

• Allows change of low-power divide factor (DF) without loss of lock

• Provides output clock with skew elimination

• Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to

16), and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise

The PLL allows the processor to operate at a high internal clock frequency using a low
frequency clock input. This feature offers two immediate benefits:

• A lower frequency clock input reduces the overall electromagnetic interference
generated by a system.

• The ability to oscillate a t different fre quencies reduces c osts by elimina ting the need to
add additional oscillators to a system.

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DSP56367 Overview
DSP56300 Core Functional Blocks

1.4.7 JTAG TAP AND ONCE MODULE

The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE

1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems associated with

testing high-density circuit boards led to developing this standard under the sponsorship of the
Test Technology Committee of IEEE and JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard.

The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and
three test data registers. A boundary scan register links all device signals into a single shift
register. The test logic, implemented utilizing static logic design, is independent of the device
system logic. More information on the JTAG port is provided in DSP56300 Family Manual,
JTAG Port.

The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and
its peripherals so a user can examine registers, memory, or on-chip peripherals. This
facilitates hardware and software development on the DSP56300 core processor. OnCE
module functions are provided through the JTAG TAP signals. More information on the
OnCE module is provided in DSP56300 Family Manual, On-Chip Emulation Module.

1.4.8 ON-CHIP MEMORY

The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into X
and Y data memory in order to work with the two Address ALUs and to feed two operands
simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can be
expanded off-chip under software control.

There is an instruction cache, made using program RAM. The patch mode (which uses
instruction cache space) is used to patch program ROM. The memory switch mode is used to
increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).

There are on-chip ROMs for program memory (40K x 24-bit), bootstrap memory (192 words
x 24-bit), X ROM (32K x 24-bit), and Y ROM(8K x 24-bit).

More information on the internal memory is provided in Section 5 Internal I/O Memory
Map on page 5-14.

DSP56367 Overview
Peripheral Overview

MOTOROLA DSP56367 1-11

1.4.9 OFF-CHIP MEMORY EXPANSION

Memory can be expanded off-chip as follows:

• Data memory can be expanded to two 16 M × 24-bit word memory spaces in 24-bit
address mode (64K in 16-bit address mode).

• Program memory can be expanded to one 16 M × 24-bit word memory space in 24-bit
address mode (64K in 16-bit address mode).

Other features of external memory expansion include the following:

• External memory expansion port

• Chip-select logic glueless interface to static random access memory (SRAM)

• On-chip dynamic RAM (DRAM) controller for glueless interface to DRAM

• Eighteen external address lines

1.5 PERIPHERAL OVERVIEW

The DSP56367 is designed to perform a wide variety of fixed-point digital signal processing
functions. In addition to the core features previously discussed, the DSP56367 provides the
following peripherals:

• 8-bit parallel host interface (HDI08, with DMA support) to external hosts

• As many as 37 user-configurable general purpose input/output (GPIO) signals

• Timer/event counter (TEC) module, containing three independent timers

• Memory switch mode in on-chip memory

• Four external interrupt/mode control lines and one external non-maskable interrupt
line

• Enhanced serial audio interface (ESAI) with up to four receivers and up to six
transmitters, master or slave, using the I2S, Sony, AC97, network, and other
programmable protocols

• A second enhanced serial audio interface (ESAI_1) with 6 dedicated pins.

• Serial host interface (SHI) using SPI and I2C protocols, with multi-master capability,
10-word receive FIFO, and support for 8-, 16-, and 24-bit words

• Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF,
IEC958, CP-340, and AES/EBU digital audio formats

1-12 DSP56367 MOTOROLA

DSP56367 Overview
Peripheral Overview

1.5.1 HOST INTERFACE (HDI08)

The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can
be connected directly to the data bus of a host processor. The HDI08 supports a variety of
buses and provides glueless connection with a number of industry-standard DSPs,
microcomputers, microprocessors, and DMA hardware.

The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled
or interrupt programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to efficiently transfer data at high speed.
Memory mapping allows DSP core communication with the HDI08 registers to be
accomplished using standard instructions and addressing modes.

Since the host bus may operate asynchronously with the DSP core clock, the HDI08 registers

are divided into 2 banks. The “host side” bank is accessible to the external host, and the “DSP
side” bank is accessible to the DSP core.

The HDI08 supports the following three classes of interfaces:

• Host processor/MCU connection

• DMA controller

• GPIO port

Host port pins not in use may be configured as GPIO pins. The host interface provides up to
16 GPIO pins. These pins can be programmed to function as either GPIO or host interface.

For more information on the HDI08, see Section 8 - Host Interface (HDI08).

1.5.2 GENERAL PURPOSE INPUT/OUTPUT (GPIO)

The GPIO port consists of as many as 37 programmable signals, all of which are also used by
the peripherals (HDI08, ESAI, ESAI_1, DAX, and TEC). There are no dedicated GPIO
signals. The signals are configured as GPIO after hardware reset. Register programming
techniques for all GPIO functionality among these interfaces are very similar.

DSP56367 Overview
Peripheral Overview

MOTOROLA DSP56367 1-13

1.5.3 TRIPLE TIMER (TEC)

This section describes a peripheral module composed of a common 21-bit prescaler and three
independent and identical general purpose 24-bit timer/event counters, each one having its
own register set.

Each timer can use internal or external clocking and can interrupt the DSP after a specified
number of events (clocks). Timer 0 can signal an external device after counting internal
events. Each timer can also be used to trigger DMA transfers after a specified number of
events (clocks) occurred. One timer (Timer 0) connects to the external world through one
bidirectional pin TIO0. When TIO0 is configured as input, the timer functions as an external
event counter or can measure external pulse width/signal period. When TIO0 is used as output
the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When the
TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer
to Section 13 - Timer/ Event Counter.

1.5.4 ENHANCED SERIAL AUDIO INTERFACE (ESAI)

The ESAI provides a full-duplex serial port for serial communication with a variety of serial
devices including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals that implement the Motorola SPI serial protocol. The ESAI consists of
independent transmitter and receiver sections, each with its own clock generator. It is a
superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI
peripheral. For more information on the ESAI, refer to Section 10 Enhanced Serial Audio
Interface (ESAI) on page 10-1.

1.5.5 ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)

The ESAI_1 is a second ESAI interface with just 6 dedicated pins instead of the 12 pins of the
full ESAI. Four data pins are shared with the ESAI, while the two high frequency clock pins
are not available. Other than the available pins, ESAI_1 is functionally identical to ESAI. For
more information on the ESAI_1, refer to Section 11 Enhanced Serial Audio Interface 1
(ESAI_1) on page 11-1.

1-14 DSP56367 MOTOROLA

DSP56367 Overview
Peripheral Overview

1.5.6 SERIAL HOST INTERFACE (SHI)

The SHI is a serial input/output interface providing a path for communication and
program/coefficient data transfers between the DSP and an external host processor. The SHI
can also communicate with other serial peripheral devices. The SHI can interface directly to
either of two well-known and widely used synchronous serial buses: the Motorola serial
peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I2C) bus. The
SHI supports either the SPI or I2C bus protocol, as required, from a slave or a single-master
device. To minimize DSP overhead, the SHI supports single-, double-, and triple-byte data
transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before
generating a receive interrupt, reducing the overhead for data reception. For more information
on the SHI, refer to Section 9 Serial Host Interface on page 9-1.

1.5.7 DIGITAL AUDIO TRANSMITTER (DAX)

The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU,
CP-340 and IEC958 formats. For more information on the DAX, refer to Section 12 Digital
Audio Transmitter on page 12-1.

MOTOROLA DSP56367 2-1

SECTION 2
SIGNAL/CONNECTION DESCRIPTIONS

2.1 SIGNAL GROUPI NG S

The input and output signals of the DSP56367 are organized into functional groups, which are
listed in Table 2-1 and illustrated in Figure 2-1.

The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate

3.3V. A special notice for this feature is added to the signal descriptions of those inputs.

Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal
150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100
MHz clock at 1.3.3V.

Table 2-1 DSP56367 Functional Signal Groupings

Functional Group

Number of

Signals

Detailed

Description

Power (V

CC

) 20 Table 2-2

Ground (GND) 18 Table 2-3

Clock and PLL 3 Table 2-4

Address bus

Port A

1

18 Table 2-5

Data bus 24 Table 2-6

Bus control 10 Table 2-7

Interrupt and mode control 5 Table 2-8

HDI08

Port B

2

16 Table 2-9

SHI 5 Table 2-10

ESAI

Port C

3

12 Table 2-11

ESAI_1

Port E

5

6 Table 2-12

Digital audio transmitter (DAX)

Port D

4

2 Table 2-13

Timer 1 Table 2-14

2-2 DSP56367 MOTOROLA

Signal/Connection Descriptions
Signal Groupings

JTAG/OnCE Port 4 Table 2-15

Note: 1. Port A is the external memory interface port, including the external address bus, data bus, and

control signals.

2. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.

3. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

4. Port D signals are the GPIO port signals which are multiplexed with the DAX signals.

5. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

Table 2-1 DSP56367 Functional Signal Groupings (Continued)

Functional Group

Number of

Signals

Detailed

Description

Signal/Connection Descriptions

Signal Groupings

MOTOROLA DSP56367 2-3

Figure 2-1 Signals Identified by Functional Group

PORT A ADDRESS BUS

A0-A17

VCCA (3)
GNDA (4)

D0-D23

VCCD (4)

GNDD (4)

AA0-AA2/RAS0-RAS2

PORT A BUS CONTROL

PORT A DATA BUS

OnCE ON-CHIP EMULATION/

TCK
TDO

VCCH
GNDH

VCCQL (4)

Port B

Port C

JTAG PORT

PINIT/NMI

VCCQH (3)

VCCC (2)
GNDC (2)

INTERRUPT AND
MODE CONTROL

MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD

RESET

PLL AND CLOCK

EXTAL

PCAP

GNDP

VCCP

Port D

QUIET POWER

GNDQ (4)

SPDIF TRANSMITTER (DAX)

ADO [PD1]
ACI [PD0]

TIMER 0

TIO0 [TIO0]

HREQ

SCK/SCL

MISO/SDA

SS

/HA2

MOSI/HA0

TMS

PARALLEL HOST PORT (HDI08)

DSP56367

HAD(7:0) [PB0-PB7]
HAS/HA0 [PB8]
HA8/HA1 [PB9]
HA9/HA2 [PB10]
HRW/HRD [PB11]
HDS/HWR [PB12]
HCS/HA10 [P B1 3 ]
HOREQ/HTRQ [PB14]
HACK/HRRQ [PB15]

SERIAL AUDIO INTERFACE (ESAI)

TDI

SERIAL HOST INTERFACE (SHI)

GNDS (2)

VCCS (2)

FST [PC4]
HCKT [PC5]
SCKR [PC0]
FSR [PC1]
HCKR [PC2]
SDO0[PC11] / SDO0_1[PE11]
SDO1[PC10] / SDO1_1[PE10 ]
SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9]
SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8]
SDO4/SD I1 [PC7]
SDO5/SD I0 [PC6]

FS

SCKT_1[PE3]

SCKT[PC3]

T_1[PE4]
SCKR_1[PE0]
FSR_1[PE1]
SDO4_1/SDI1_1[PE7]
SDO5_1/SDI0_1[PE6]

BB

BG

BR

TA

WR

RD

CAS

Port E

SERIAL AUDIO INTERFACE(ESAI_1)

2-4 DSP56367 MOTOROLA

Signal/Connection Descriptions
Power

2.2 POWER

2.3 GROUND

Table 2-2 Power Inputs

Power Name Description

V

CCP

PLL Power—V

CCP

is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be

provided with an extremel y low imp ed an ce path to the V

CC

power rail. There is one V

CCP

input.

V

CCQL

(4) Quiet Core (Low) Power—V

CCQL

is an isolated power for the internal processing logic. This input must be tied

externally to all ot her V

CCQL

power pins and the V

CCP

power pin only. Do not tie with other power pins. The user

must provide adequate exte rna l de c oupling capacitors. There are four V

CCQL

inputs.

V

CCQH

(3) Quiet External (High) Power—V

CCQH

is a quiet power source for I/O lines. This input must be tied externally to all

other chip power inputs.The user must provide adeq ua te dec oupling capacitors. There are three V

CCQH

inputs.

V

CCA

(3) Address Bus Power—V

CCA

is an isolated power for sections of the address bus I/O drivers. This input must be tied

externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are
three V

CCA

inputs.

V

CCD

(4) Data Bus Power—V

CCD

is an isolated power for sections of the data bus I/O driver s. Th is in p ut must be tied

externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are
four V

CCD

inputs.

V

CCC

(2) Bus Control Power—V

CCC

is an isolated power for the bus control I/O drivers. This input must be tied externally to

all other chip power inputs. The user must provid e a dequate external decoupling capacitors. There are two V

CCC

inputs.

V

CCH

Host Power—V

CCH

is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other

chip power inputs. The user must provide ade qua te external decouplin g capacitors. There is one V

CCH

input.

V

CCS

(2) SHI, ESAI, ESAI_1, DAX and Timer Power —V

CCS

is an isolated power for the SHI, ESAI, ESAI_1, DAX and

Timer. This input must be ti ed externally to all other chip power inputs. Th e use r must provide adequate ext ernal
decoupling capaci tors. There are two V

CCS

inputs.

Table 2-3 Grounds

Ground Name Description

GND

P

PLL Ground—GNDP is a ground dedicated for PLL u se. The connection shou ld b e pro v i ded with an extremely
low-impedance path to ground. V

CCP

should be bypassed to GNDP by a 0.47 µF capacitor located as close as

possible to the chi p pa ckage. There is one GND

P

connection.

GND

Q

(4) Quiet Ground—GNDQ is an isolated ground for t he internal processing logic. This connection must be tied

externally to all other chi p ground connections. Th e use r must provide adequate ex te rna l de coupling capacitors.
There are four G N D

Q

connections.

Signal/Connection Descriptions

Clock and PLL

MOTOROLA DSP56367 2-5

2.4 CLOCK AND PLL

GNDA (4) Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are four GND

A

connections.

GND

D

(4) Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be

tied externally to all other chip ground connect i ons. The user must provide adequate external decoupling capacitors.
There are four G N D

D

connections.

GND

C

(2) Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied

externally to all other chi p ground connections. Th e user must provide adequate external decoupling ca pacitors.
There are two G ND

C

connections.

GND

H

Host Ground—GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all
other chip ground connecti ons. The user must provide adequat e ex te rnal decoupling capacitors. The re is one GND

H

connection.

GND

S

(2) SHI, ESAI, ESAI_1, DAX and Timer Ground—GNDS is an isolated ground for t he SHI , E S AI , ESA I_1, DAX

and Timer. This connection must be tied externally to a ll other chip ground connections. The user must provide
adequate external decoupling capacitors. There are two GND

S

connections.

Table 2-4 C lock and PLL Signals

Signal Name Type

State

during

Reset

Signal Description

EXTAL Input Input External Clock Input—An external cl ock source must be connecte d t o EXT A L in

order to supply the clock to the int ernal clock generator an d PLL.

PCAP Input Input PLL Capacitor—PCAP is an input connecting an off-chip capacitor to the PLL filter.

Connect one capacitor terminal to PCAP and the other terminal to V

CCP

.

If the PLL is not used, PCAP may be tied to V

CC

, GND, or left floating.

PINIT/NMI

Input Input PLL Initial/Nonmaskable Interrupt— D uri ng a ssert ion of RESET, the valu e of

PINIT/NMI

is written into the PLL Enable (PEN) bit of the PLL control register,

determining whether the P LL is enabled or disabled. Af ter RESET

de assertion and

during normal instruction proc essing, the PINIT/NMI

Schmitt-trigger input is a

negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized
to internal system clock.

Table 2-3 Grounds

Ground Name Description

2-6 DSP56367 MOTOROLA

Signal/Connection Descriptions
External Memory Expansion Port (Port A)

2.5 EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus

mastership and tri-states the relevant port A signals: A0–A17, D0–D23,
AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS.

2.5.1 EXTERNAL ADDRESS BUS

2.5.2 EXTERNAL DATA BUS

2.5.3 EXTERNAL BUS CONTROL

Table 2-5 External Address Bus Signals

Signal Name T ype

State

during

Reset

Signal Description

A0–A17 Output Tri-stated Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs that

specify the addre s s fo r external program and data memory acce s s es . O therwise, the
signals are tri-stated. To minimize power di ssipat ion , A0–A17 do not change state
when external memory spaces are not being accessed.

Table 2-6 External Data Bus Signals

Signal Name Type State during Reset Signal Description

D0–D23 Input/Output Tri-stated Data Bus—When the DSP is the bus master, D0–D23 are

active-high, bidirectional input/outputs that provide the bidirectional
data bus for external program and data memory accesses. Otherwise,
D0–D23 are tri-s tated.

Table 2-7 External Bus Control Signals

Signal
Name

Type

State

during

Reset

Signal Description

AA0–AA2/

RAS0

–RAS

2

Output Tri-stated Address Attribute or Row Address Strobe—When defined as AA, these signals can be

used as chip selects or additional address lines. When defined as RAS

, these signals can

be used as RAS

for DRAM interface. These signals are tri-statable outputs with

programmable polarity.

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 2-7

CAS Output Tri-stated Column Address Strobe— When the DSP is the bus master, C AS is an active-low output

used by DRAM to strobe the column address. Otherw i se, if the bus m aste rship ena bl e
(BME) bit in the DRAM control register is cl ear ed, the signal is tri-stated.

RD

Output Tri-stated Read Enable—When th e D SP is the bus master, RD is an ac tive-low ou tp ut that is

asserted to read external memory on the data bu s (D0-D23). Otherwise, RD

is tri-stated.

WR

Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is

asserted to write external memo r y on the da ta bus (D0 - D23) . Ot h er wise, WR

is tri-stated.

TA

Input Ignored

Input

Transfer Acknowledge—If the DSP is the bus master and there is no external bus
activity, or the DSP is not the bus master, the TA

input is ignored. The TA in p ut is a data
transfer acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any numb er of wa it states (1, 2. . .in finity) may be added to the wait states
inserted by the BCR by keepin g TA

deasserted. In typical operation, TA is deasserted at
the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted
before the next bus cycle. The current bus cycle completes one clock period after TA

is
asserted synchronous to the internal system clock. The number of wait states is
determined by the TA

input or by the bus control register (BCR), whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus cycles.
In order to use the TA

functionality, the BCR m ust be programmed to at least one wait

state. A zero wait st ate access cannot be ext en de d b y TA

deassertion, otherwise improper

operation may result. TA

can operate synchronously or asynchronously, depending on the
setting of the TAS bit in the operating mode register (OMR).
TA

functionality may not be used while pe rforming DRAM type accesses, otherw i se

improper operation may result.

BR

Output Output

(deasserted)

Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the DSP
requests bus mastership. BR

is deasserte d when th e DSP no longe r n eeds th e bu s. BR may
be asserted or deasserted independe nt of w het he r th e D SP56367 is a bus master or a bus
slave. Bus “parking” allows BR

to be deasserted even though the DSP56367 is the bus

master. (See the description of bus “ parking” in the BB

signal description.) The bus

request hold (BRH) bit in the BC R allows BR

to be asserted under software control even

though the DSP does not need the bus. BR

is typically sent to an external bus arbitrator
that controls the priority, parking, and tenure of each master on the same external bus. BR
is only affected by DSP requests for th e external bus, never for the intern al bus. During
hardware reset, BR

is deasserted and the arbitration is reset to the bus slave state.

BG

Input Ignored

Input

Bus Grant—BG is an active-low input. BG is ass erted by an extern al bus arbitratio n
circuit when th e D S P 56367 becomes the next bus master. W hen BG

is asserted, the

DSP56367 must wait until BB

is deasserted before taking bus master sh ip . W he n BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle. This
may occur in the middle o f an instruction that requi res more than one external bus cycle
for execution.

For proper BG

operation, the asynchron ous bus arbitration enable bit (AB E) in the OMR

register must be set.

Table 2-7 External Bus Control Signals (Continued)

Signal

Name

Type

State

during

Reset

Signal Description

2-8 DSP56367 MOTOROLA

Signal/Connection Descriptions
Interrupt and Mode Control

2.6 INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.

BB Input/

Output

Input Bus Busy—BB is a bi d irectional active-low input/output. BB indicates that the bus is

active. Only after BB

is deasserted can the pending bus ma ster be come the bus master

(and then asser t the signal again). The bus master may keep BB

asserted after ceasing bus

activity regardless of whether BR

is asserted or deasserted. This is called “bus parking”
and allows the curren t bus m ast er to reuse the bus without rearbi tr ation until another
device requires the bus. The deassertion of BB

is done by an “active pull-up” method (i.e.,

BB

is driven high and then released and held high by an external pull-up resistor).

For proper BB

operation, the asynchro nous bus arbitration enable bit (ABE) in the OMR

register must be set.

BB

requires an external pull-up resi sto r.

Table 2-8 Interrupt and Mode Control

Signal Name Type

State

during

Reset

Signal Description

MODA/IRQA

Input Input Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA

selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-tri gge re d, ma skable interrupt request input duri ng normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latched into the OMR wh en the RESE T

signal is deasserted. If the processor is in the

stop standby state and the MODA/IRQA

pin is pulled to GND, the processor will exit the
stop state.
This input is 3.3V tolerant.

MODB/IRQB

Input Input Mode Select B/External Interrupt Request B—MODB/IRQB i s an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODB /IRQB

selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-tri gge re d, ma skable interrupt request input duri ng normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latc h ed into OMR wh en the RESET

signal is deasserted.

This input is 3.3V tolerant.

Table 2-7 External Bus Control Signals (Continued)

Signal
Name

Type

State

during

Reset

Signal Description

Signal/Connection Descriptions

Parallel Host Interface (HDI08)

MOTOROLA DSP56367 2-9

2.7 PARALLEL HOST INTERFACE (HDI08)

The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host
bus. The HDI08 supports a variety of standard buses and can be directly connected to a
number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.

MODC/IRQC Input Input Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low

Schmitt-trigger input, interna lly sync hronized to the DSP clock. MODC/IRQC

selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-tri gge re d, ma skable interrupt request input duri ng normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latc h ed into OMR wh en the RESET

signal is deasserted.

This input is 3.3V tolerant.

MODD/IRQD

Input Input Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low

Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD

selects the
initial chip operating mode during hardware reset and becomes a level-sensitive or
negative-edge-tri gge re d, ma skable interrupt request input duri ng normal instruction
processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating
modes, latc h ed into OMR wh en the RESET

signal is deasserted.

This input is 3.3V tolerant.

RESET

Input Input Reset—RESET is an acti ve-lo w, Sch mitt- tr igger input. Wh en asser ted , the chip is plac ed in

the Reset state and the in ternal phase g enerator is reset. The Sch mitt-trigg er input allows a
slowly rising input (such as a capacitor charging) to reset the chip reliably. When the
RESET

signal is deasserted, the initial chip operating mode is latched from the MODA,

MODB, MODC, and MODD inputs. The RESET

signal must be asserted during power up.

A stable EXTAL signal must be supplied while RESET

is being asserted.

This input is 3.3V tolerant.

Table 2-8 Interrupt and Mode Control (Continued)

Signal Name Type

State

during

Reset

Signal Description

2-10 DSP56367 MOTOROLA

Signal/Connection Descriptions
Parallel Host Interface (HDI08)

Table 2-9 Host Interface

Signal Name Type

State during

Reset

Signal Description

H0–H7 Input/

output

Host Data—When HDI08 is programmed to interface a nonmultiplexed

host bus and the HI function is sele ct ed, these signals are lines 0–7 of the
bidirectional, tri-state data bus.

HAD0–HAD7 Input/

output

Host Address/Data—When HDI08 is programmed to interfa ce a
multiplexed host bu s and the HI function is selected, these signals ar e lines

0–7 of the address/data bidirectional, multiplexed, tri-state bus.

PB0–PB7 Input, output, or

disconnected

GPIO

disconnected

Port B 0–7—When the HDI08 is configured as GPIO, these signals are
individually programm abl e as input, output, or internally discon nec t ed.

The default state after reset for these signals is GPIO disconnected.

These inputs are 3.3V tole rant.

HA0 Input GPIO

disconnected

Host Address Input 0—When the HDI08 is programmed to interface a
nonmultiplexed host bus and the HI function is selected, this signal is line 0
of the host address input bus.

HAS/

HAS Input Host Address Strobe—When HDI08 is pro grammed to interface a

multiplexed host bus and the HI function is selected, this signal is the host
address strobe (HAS) Schmitt -t rig ger input. The polarity of the addr ess
strobe is programmable, but is configured active-low (HAS

) following

reset.

PB8 Input, output, or

disconnected

Port B 8—When the HDI08 is configured as GPIO , thi s si gnal is
individually programmed as input, output, or internally disconnected.

The default state after reset f or th is sig na l is GPIO di sco n ne cte d.

This input is 3.3V tolerant.

HA1 Input GPIO

disconnected

Host Address Input 1—When the HDI08 is programmed to interface a
nonmultiplexed host bus and the HI function is selected, this signal is line 1
of the host address (HA1) input bus.

HA8 Input Host Address 8—When HDI08 is programmed to interface a multiplexed

host bus and the HI function is selected, this signal is line 8 of the host
address (HA8) input bus.

PB9 Input, output, or

disconnected

Port B 9—When the HDI08 is configured as GPIO , thi s si gnal is
individually programmed as input, output, or internally disconnected.

The default state after reset f or th is sig na l is GPIO di sco n ne cte d.

This input is 3.3V tolerant.

Signal/Connection Descriptions

Parallel Host Interface (HDI08)

MOTOROLA DSP56367 2-11

HA2 Input GPIO

disconnected

Host Address Input 2—When the HDI08 is programmed to interface a
non-multiplexed host bus and the H I func ti on is sel ec ted, this signa l is line
2 of the host address (HA2) input bus.

HA9 Input Host Address 9—When HDI08 is programmed to interface a multiplexed

host bus and the HI function is selected, this signal is line 9 of the host
address (HA9) input bus.

PB10 Input, Output, or

Disconnected

Port B 10—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V tolerant.

HRW Input GPIO

disconnected

Host Read/Write—When HDI08 is programmed to interfa ce a
single-data-strobe host bus and the HI function is selected, this signal is the
Host Read/Wr ite

(HRW) input.

HRD

/

HRD

Input Host Read Data—When HDI08 is programmed t o int e rface a

double-data-strobe host bus and the HI function is selected, this signal is
the host read data strobe (HRD) Schmitt-trigger input. The polarit y of th e
data strobe is programma bl e, but is configured as active-low (H RD

) after

reset.

PB11 Input, Output, or

Disconnected

Port B 11—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V tolerant.

HDS

/

HDS

Input GPIO

disconnected

Host Data Strobe—When HDI08 is programmed to interface a
single-data-strobe host bus and the HI function is selected, this signal is the
host data strobe (HDS) Schmitt -t r ig ger input. The polarity of the data
strobe is programmable, but is configured as active-low (HDS

) following

reset.

HWR

/

HWR

Input Host Write Data—When HDI08 is programmed to interface a

double-data-strobe host bus and the HI function is selected, this signal is
the host write data strobe (HWR) Schmitt-trigger input. The polarity of the
data strobe is programma bl e, but is configured as active-low (H WR

)

following reset.

PB12 In put, output, or

disconnected

Port B 12—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset for this signal is GPIO disconnected.

This input is 3.3V tolerant.

Table 2-9 Host Interface (Con tinued)

Signal Name Type

State during

Reset

Signal Description

2-12 DSP56367 MOTOROLA

Signal/Connection Descriptions
Parallel Host Interface (HDI08)

HCS Input GPIO

disconnected

Host Chip Select—When HDI08 is prog ra mmed to interface a
nonmultiplexed ho st bu s and the HI function is select ed, this signal is the
host chip select (HCS) input. The polarity of the chip select is
programmable, but is configured active-low (HCS

) after reset.

HA10 Input Host Address 10—When HDI08 is programmed to interface a multiplexed

host bus and the HI function is sel ected, this signal is line 10 of th e host
address (HA10) input bus.

PB13 In put, output, or

disconnected

Port B 13—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset f or th is sig na l is GPIO di sco n ne cte d.

This input is 3.3V tolerant.

HOREQ

/HOREQ Output GPIO

disconnected

Host Request—When HDI08 is programmed t o inter fac e a single host
request host bus and the HI function is sele ct ed, this signal is the host
request (HOREQ) output. The polarity of the host request is
programmable, bu t is c onfigured as active-lo w (H O REQ

) following reset.

The host request may be programmed as a driven or open-drain output.

HTRQ

/

HTRQ

Output Transmit Host Request—When HDI08 is programmed to in te rface a

double host request host bus and the HI fun ction is selected, this signal is
the transmit host reque st (HTR Q) out put. The pola rity of t he host requ est is
programmable, but is configured as acti ve-low (HTRQ

) following reset.

The host request may be programmed as a driven or open-drain output.

PB14 In put, output, or

disconnected

Port B 14—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset f or th is sig na l is GPIO di sco n ne cte d.

This input is 3.3V tolerant.

HACK

/

HACK

Input GPIO

disconnected

Host Acknowledge—When HDI08 is progra mm e d to interface a single
host request host bus and the HI function is selec ted, th is sign al is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is program mable, but is configured as ac t ive -low (HACK

)

after reset.

HRRQ

/

HRRQ

Output Receive Host Request—When HDI08 is programmed to interface a

double host request host bus and the HI fun ction is selected, this signal is
the receive host request (HRR Q ) out put. The polarity of the host request is
programmable, bu t is c onfigured as active-lo w (H RRQ

) after reset. The

host request may be programm ed as a dri ven or open-drain output.

PB15 In put, output, or

disconnected

Port B 15—When the HDI08 is configu r ed as GPIO, this signal is
individually programmed as input, output, or internally disconnected.

The default state after reset f or th is sig na l is GPIO di sco n ne cte d.

This input is 3.3V tolerant.

Table 2-9 Host Interface (Con tinued)

Signal Name Type

State during

Reset

Signal Description

Signal/Connection Descriptions

Serial Host Interface

MOTOROLA DSP56367 2-13

2.8 SERIAL HOST INTERFACE

The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or
I2C mode.

Table 2-10 Serial Host Interface Signals

Signal
Name

Signal Type

State

during

Reset

Signal Description

SCK Input or

output

Tri-stated SPI Serial Clock—The SCK s ignal is an output when the SPI is configured as a master and

a Schmitt-tri gg er input when th e SPI is configu r ed as a slave. When the SPI is con f igured as
a master, the SCK signal is derived fr om the internal SHI clock gener ator. When the SPI is
configured as a slav e, the SCK signal is an input, an d th e clock signal from the external
master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as
a slave and the slave select (SS

) signal is not asse rted. In both the master and slave SPI
devices, data is shifted on one edge of th e SCK signal and is sampled on the opposite edge
where data is stable. Edge pol arity is determined by the SPI transfe r protocol.

SCL Input or

output

I

2

C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a

Schmitt-trigger input when configured as a slave and an open-drain output when configured
as a master. SCL should be connected to V

CC

through a pull-up resistor.

This signal is tri-stated during hardware, software, and individual reset . Thus, there is no
need for an external pull-up in this state.

This input is 3.3V tolerant.

MISO Input or

output

Tri-stated SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is the master

data input line. The MISO signa l is used i n conjunction with the MOSI signal fo r
transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured
for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if
configured for the SPI S lave mode when SS

is deasserted. An external pull-up resistor is not

required for SPI operation .

SDA Input or

open-drain

output

I

2

C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when receiving

and an open-drain outpu t whe n transmitting. SDA should be connected to V

CC

through a

pull-up resistor. SDA carries the data for I

2

C transactions. The data in SDA must be stable
during the high period of SCL. The data in SDA is only allowed to change when SCL is low.
When the bus is free, SDA is high. The SDA line is only allowed to change during the time
SCL is high in the case of start an d stop eve nt s . A hi gh-t o-low transition of the SDA line
while SCL is high is a unique situat ion, and is defined as the start event. A lo w -to -high
transition of SDA while SCL is high is a uni que situation defined as the stop eve nt .

This signal is tri-stated during hardware, software, and individual reset . Thus, there is no
need for an external pull-up in this state.

This input is 3.3V tolerant.

2-14 DSP56367 MOTOROLA

Signal/Connection Descriptions
Serial Host Interface

MOSI Input or

output

Tri-stated SPI Master-Out-Slave-In— W he n the SPI is configured as a master, MOSI is th e m ast er

data output line. The MOSI signal is used in conjunction wi th the MISO signal for
transmitting and receiving serial data. MOSI is t he slave data input line whe n the SPI is
configured as a slave. This signa l is a Schmi tt -t rig ger input when configured for the SPI
Slave mode.

HA0 Input

I

2

C Slave Address 0—This signal uses a Schmitt-trigger input when configured for the I2C

mode. When con fi gur e d for I

2

C slave mode, the HA0 sig nal is us ed to for m th e slave dev ice

address. HA0 is ignored when configured for the I

2

C master mode.

This signal is tri-stated during hardware, software, and individual reset . Thus, there is no
need for an external pull-up in this state.

This input is 3.3V tolerant.

SS

Input Tri-st ated SPI Slave Select—T his signal is an active low Schmitt-trigger input when configured for

the SPI mode. When con fig ure d for th e SPI Slav e mode , thi s si gna l is u sed to enabl e the S PI
slave for transfer. When configured for the SPI master mode, this signal should be kept
deasserted (pulled high). If it is asse rte d while configured as SPI master, a bus error
condition is flagged. If SS

is deasserted, the SHI ignores SCK clocks and keeps the MISO

output signal in the high-i m pedance state.

HA2 Input

I

2

C Slave Address 2—This signal uses a Schmitt-trigger input when configured for the I2C

mode. When configured for the I

2

C Slave mode, the HA2 signal is used to form the slave

device address. HA2 is ignored in the I

2

C master mode.

This signal is tri-stated during hardware, software, and individual reset . Thus, there is no
need for an external pull-up in this state.

This input is 3.3V tolerant.

HREQ

Input or

Output

Tri-stated Host Request—T his signal is an active low Schmitt-trigg er input when configured for the

master mode but an active low output when configured for the slave mode.

When configured for the slave mode, HREQ

is asserted to indicate that the SHI is read y for
the next data word transfer and deasserted at the first clock pulse of the new data word
transfer. When configured for the master mode, HREQ

is an input. When asserted by the
external slave device, it will trigger the start of the data word transfer by the master. After
finishing the data word transfer, the master will await the next assertion of HREQ

to proceed

to the next transfer.

This signal is tri-stated during hardware, soft ware, personal reset, or when the
HREQ1–HREQ 0 bit s in th e H CSR are cleared. Ther e is no ne ed for external pull-up i n thi s
state.

This input is 3.3V tolerant.

Table 2-10 Serial Host Interface Signals (Continued)

Signal

Name

Signal Type

State

during

Reset

Signal Description

Signal/Connection Descriptions

Enhanced Serial Audio Interface

MOTOROLA DSP56367 2-15

2.9 ENHANCED SERIAL AUDIO INTERFACE

Table 2-11 Enhanced Serial Audio Interface Signals

Signal

Name

Signal Type State during Reset Signal Description

HCKR Inp ut or output GPIO discon nected High Frequency Clock for Receiver—When program me d a s an in put , this

signal provides a high frequency clock source for the ESAI receiver as an
alternate to the D S P core clock. When p rogrammed as an ou tput, this signal
can serve as a high-frequenc y sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.

PC2 Input, output, or

disconnected

Port C 2—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

HCKT Input or output GPIO di sconnected High Frequency Clock for Transmitter—When programmed as an input,

this signal provides a high frequency clock source for the ESAI transmitter as
an alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high frequency sa mp le cl oc k (e. g. , for ext e rnal DACs) or as an
additional system clock.

PC5 Input, output, or

disconnected

Port C 5—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

FSR Input or outp ut GPIO disconnected Frame Sync for Re ceiver—This is the receive r fra m e sync in put /output

signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame
sync input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).

When this pi n is configured as serial fl ag pin, its direction is d etermined by the
RFSD bit in the RCCR register. When configure d as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR registe r, a nd t he da ta in
the OF1 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mo de. When configured as the input flag IF1, the
data value at the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.

PC1 Input, output, or

disconnected

Port C 1—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

2-16 DSP56367 MOTOROLA

Signal/Connection Descriptions
Enhanced Serial Audio Interface

FST Input or output GPIO disconnected Frame Sync for Transmitter—This is the transmitter frame sync input/output

signal. For synchronous mode, this sig nal is th e fra m e sync for both
transmitters and receivers. For asynchronous mode, FST is the frame sync for
the transmitters onl y. The direc tion is dete rmined by the transmitte r frame syn c
direction (TFSD) bit in the ESAI tran smit c lo ck c ont rol register (TCCR).

PC4 Input, output, or

disconnected

Port C 4—When the ESAI is configured as GPIO , this signa l is individually
programmable as in put , ou tput, or internally disconne ct ed.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SCKR Input or output GPIO disconnected Receiver Serial Clock—SCKR provides the r eceiver serial bit clock for the

ESAI. The SCKR ope ra te s as a cl oc k input or output used by al l th e enabled
receivers in the asynchronous m ode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its dire ction is deter mined by the
RCKD bit in the RCCR register. When configured as the output flag OF0, this
pin will reflect the value of th e OF0 bit in th e S AIC R r eg ister, and the data in
the OF0 bit will show up at the pin synchronized to the frame sync in norm al
mode or the slot in network mode. When configured as the inp ut fl ag IF0, the
data value at the pin will be stored in the IF0 bi t in the SA ISR re gist e r,
synchronized by the frame sync in normal mode or the slot in network mode.

PC0 Input, output, or

disconnected

Port C 0—When the ESAI is configured as GPIO , this signa l is individually
programmable as in put , ou tput, or internally disconne ct ed.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SCKT Input or output GPIO disconnected Transmitte r Ser i al Clock—This signal provides the serial bit rate clock for

the ESAI. SCKT is a clock input or output used by all enabled transmitters and
receivers in synchronous mode, or by all enabled transmitters in asynchronous
mode.

PC3 Input, output, or

disconnected

Port C 3—When the ESAI is configured as GPIO , this signa l is individually
programmable as in put , ou tput, or internally disconne ct ed.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SDO5 Output GPIO disconnected Serial Data Output 5—When programmed as a transmitter, SDO5 is used to

transmit data from the TX5 serial transmit shift register.

SDI0 Input Serial Data Input 0—When programmed as a receiver, SDI0 is used to

receive serial data into the RX0 serial receive shift register.

PC6 Input, output, or

disconnected

Port C 6—When the ESAI is configured as GPIO , this signa l is individually
programmable as in put , ou tput, or internally disconne ct ed.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

Table 2-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type State during Reset Signal Description

Signal/Connection Descriptions

Enhanced Serial Audio Interface

MOTOROLA DSP56367 2-17

SDO4 Output GPIO disconnected Serial Data Output 4—When programmed as a transmitter, SDO4 is used to

transmit data from the TX4 serial transmit shift register.

SDI1 Input Serial Data Input 1—When programmed as a receiver, SDI1 is used to

receive serial data into the RX 1 seri al receive shift register.

PC7 Input, output, or

disconnected

Port C 7—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SDO3/SD

O3_1

Output G PIO disconnected Serial Data Output 3—When programmed as a transmitter, SDO3 is used to

transmit data from the TX3 serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3.

SDI2/SDI

2_1

Input Serial Data Input 2—When programmed as a receiver, SDI2 is used to

receive serial data into the RX 2 seri al receive shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2.

PC8/PE8 Input, output, or

disconnected

Port C 8—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 8 signal.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SDO2/SD

O2_1

Output G PIO disconnected Serial Data Output 2—When programmed as a transmitter, SDO2 is used to

transmit data from the TX2 serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2.

SDI3/SDI

3_1

Input Serial Data Input 3—When programmed as a receiver, SDI3 is used to

receive serial data into the RX 3 seri al receive shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3.

PC9/PE9 Input, output, or

disconnected

Port C 9—When the ESAI is configured as G PIO , thi s signa l is i ndi vidually
programmable as input, out put, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 9 signal.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

SDO1/SD

O1_1

Output G PIO disconnected Serial Data Output 1—SDO1 is used to transmit data from the TX1 serial

transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1.

PC10/PE10Input, output, or

disconnected

Port C 10—When the ESAI is config ured as GPIO, th is sig na l is in di v id ua lly
programmable as input, out put, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 10 signal.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

Table 2-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type State during Reset Signal Description

2-18 DSP56367 MOTOROLA

Signal/Connection Descriptions
Enhanced Serial Audio Interface

SDO0/SD

O0_1

Output G PIO disconnected Serial Data Output 0—SDO0 is used to transmit data from the TX0 serial

transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0.

PC11/PE11Input, output, or

disconnected

Port C 11—When the ESAI is config ured as GPIO, this signal is individually
programmable as input, out put, or internally disconnect ed.
When enabled for ESAI_1 GPIO, this is the Port E 11 signal.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

Table 2-11 Enhanced Serial Audio Interface Signals (Continued)

Signal
Name

Signal Type State during Reset Signal Description

Signal/Connection Descriptions

Enhanced Serial Audio Interface_1

MOTOROLA DSP56367 2-19

2.10 ENHANCED SERIAL AUDIO INTERFACE_1

Table 2-12 Enhanced Serial Audio Interface_1 Signals

Signal
Name

Signal Type State during Reset Signal Description

FSR_1 Input or ou tpu t GPIO disconnected Frame Sync for Receiver_1—This is the receiver fram e sync input/output

signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame
sync input or output used by al l th e enabled receivers. In the sync hronous
mode (SYN=1), it operat es as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1 , RFSD=1).

When this pin is configur ed as serial fl ag p in, its direction is deter mined by
the RFSD bit in the RCCR register. When configured as the output flag O F 1,
this pin will reflect the value of the OF1 bi t in the SAICR register, and the
data in the OF1 bit will show up a t the pin synchronized to the frame sync in
normal mode or the slot in networ k mode. When configured as the inpu t fl ag
IF1, the data value at the pin will be stored in the IF1 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in
network mode.

PE1 Input, output, or

disconnected

Port E 1—When the ESAI is configu red as GPIO, this signal is individua lly
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input cannot tolerate 3.3V.

FST_1 Input or output GPIO discon nected Frame Sync for Transmitter_1— This is the transmitter frame sync

input/output signal. For synchrono us mo de, this signal is the frame sync for
both transmitters and rece i vers. For asynchronous mode, FST is the frame
sync for the transmitters only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESA I tra nsm it clock control register
(TCCR).

PE4 Input, output, or

disconnected

Port E 4—When the ESAI is configu red as GPIO, this signal is individua lly
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input cannot tolerate 3.3V.

SCKR_1 Input or output GPIO disconnected Receiver Serial Clock_1—SCKR provides the receiver serial bit clock for

the ESAI. The SCKR oper ates as a clock input or output used by a ll the
enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin
in the synchronous mode (SYN=1).

When this pin is configur ed as serial fl ag p in, its direction is deter mined by
the RCKD bit in the RCCR register. When configured as the output flag OF0,
this pin will reflect the value of the OF0 bi t in the SAICR register, and the
data in the OF0 bit will show up a t the pin synchronized to the frame sync in
normal mode or the slot in networ k mode. When configured as the inpu t fl ag
IF0, the data value at the pin will be stored in the IF0 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in
network mode.

PE0 Input, output, or

disconnected

Port E 0—When the ESAI is configu red as GPIO, this signal is individua lly
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input cannot tolerate 3.3V.

2-20 DSP56367 MOTOROLA

Signal/Connection Descriptions
SPDIF Transmitter Digital Audio Interface

2.11 SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE

SCKT_1 Input or output GPIO disconnected Transmitter Serial Clock_1—This signal provides the serial bit rate clock

for the ESAI. SCKT is a clock input or output used by all enabled transmitters
and receivers in synchron ous m ode, or by all enabled transmi tters i n
asynchronous mode.

PE3 Input, output, or

disconnected

Port E 3—When the ESAI is configu red as GPIO, this signal is individuall y
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input cannot tolerate 3.3V.

SDO5_1 Output GPIO disconnected Serial Data Output 5_1—When programmed as a transmitter, SDO5 is used

to transmit data from the TX5 serial transmit shift register.

SDI0_1 Input Serial Data Input 0_1—When programmed as a receiver, SDI0 is used to

receive serial da ta into the RX0 seri al receive shift reg is ter.

PE6 Input, output, or

disconnected

Port E 6—When the ESAI is configu red as GPIO, this signal is individuall y
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input cannot tolerate 3.3V.

SDO4_1 Output GPIO disconnected Serial Data Output 4_1—When programmed as a transmitter, SDO4 is used

to transmit data from the TX4 serial transmit shift register.

SDI1_1 Input Serial Data Input 1_1—When programmed as a receiver, SDI1 is used to

receive serial da ta into the RX1 seri al receive shift reg is ter.

PE7 Input, output, or

disconnected

Port E 7—When the ESAI is configu red as GPIO, this signal is individuall y
programmable as input, output, or internally disconnected.

The default state after reset is G PIO di sconnected.

This input is 3.3V toleran t.

Table 2-13 Digital Audio Interface (DAX) Signals

Signal

Name

Type State During Reset Signal Description

ACI Input GPIO Disconnected Audio Clock Input—This is the DAX clock input. When programmed to use

an external clock, this input supplies the DAX clock. The external clock
frequency must be 256, 384, or 512 times the audio sampling frequency (256 ×
Fs, 384 × Fs or 512 × Fs, respectively).

PD0 Input,

output, or

disconnected

Port D 0—When the DAX is configured as GPIO, this signal is individually
programmable as input , output, or internally disconnect ed.

The default state after reset is G P IO disc onnected.

This input is 3.3V tolerant.

Table 2-12 Enhanced Serial Audio Interface_1 Signals

Signal

Name

Signal Type State during Re set S ignal Description

Signal/Connection Descriptions

Timer

MOTOROLA DSP56367 2-21

2.12 TIMER

2.13 JTAG/OnCE INTERFACE

ADO Output GPIO Disconnected Digital Audio Data Output—This signal is an audio and non-audio output in

the form of AES/EBU, CP340 a nd IE C958 data in a biphase mark format .

PD1 Input,

output, or

disconnected

Port D 1—When the DAX is configured as GPIO, this signal is individually
programmable as input , outp ut, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 3.3V tolerant.

Table 2-14 Timer Signal

Signal Name Type

State during

Reset

Signal Description

TIO0 Input or Output Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an externa l

event counter or in measur ement mode, TIO0 is used as input. Whe n t imer 0 functions
in watchdog, timer, or pulse modulation mode, TIO0 is use d as out put.

The default mode after reset is G PIO input. This can be changed to output or
configured as a timer input/output through the timer 0 control/status register (TCSR0).
If TIO0 is not being used, it is recommended to either define it as G P IO output
immediately at the beginning of operation or leave it defined as GPIO input but
connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this
input.

This input is 3.3V toleran t.

Table 2-15 JTAG/OnCE Interface

Signal
Name

Signal

Type

State

during

Reset

Signal Description

TCK Input Input Test Clock—TCK is a test clock input sign al us ed t o sync hronize the JTAG test logic. It

has an internal pull-up resistor.

This input is 3.3V tolerant.

Table 2-13 Digital Audio Interface (DAX) Signals (Continued)

Signal

Name

Type State During Reset Signal Description

2-22 DSP56367 MOTOROLA

Signal/Connection Descriptions
JTAG/OnCE Interface

TDI Input Input Test Data Input—TDI is a test data serial input signal used for test instructions and data.

TDI is sampled on the rising edge of TCK and has an internal pull-up resistor .

This input is 3.3V tolerant.

TDO Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test instructions and

data. TDO is tri-statable and is acti vely drive n in the shif t-IR and shif t-DR cont rol ler sta tes.
TDO changes on the fal li ng edge of TCK.

TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state

machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor.

This input is 3.3V tolerant.

Table 2-15 JTAG/OnCE Interface (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

MOTOROLA DSP56367 3-1

SECTION 3
SPECIFICATIONS

3.1 INTRODUCTION

The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL)
compatible inputs and outputs.

Note: This document contains information on a new product.

Specifications and information herein are subject to change without notice.

Finalized specifications may be published after further characterization and device
qualifications are completed.

3.2 MAXIMUM RATINGS

Note: In the calculation of timing requirements, adding a maximum value of one

specification to a minimum value of another specification does not yield a
reasonable sum. A maximum specification is calculated using a worst case
variation of process parameter values in one direction. The minimum specification

CAUTION

This device contains circuitry protecting
against damage due to high static voltage
or electrical fields. However, normal
precautions should be taken to avoid
exceeding maximum voltage ratings.
Reliability of operation is enhanced if
unused inputs are pulled to an
appropriate logic voltage level (e.g., either
GND or VCC). The suggested value for a
pullup or pulldown resistor is 10 kΩ.

3-2 DSP56367 MOTOROLA

Specifications
Thermal Characteristics

is calculated using the worst case for the same parameters in the opposite direction.

Therefore, a “maximum” value for a specification will never occur in the same
device that has a “minimum” value for another specification; adding a maximum
to a minimum represents a condition that can never exist.

3.3 THERMAL CHARACTERISTICS

Table 3-1 Maximum Ratings

Rating

1

Symbol

Value

1, 2

Unit

Supply Voltage V

CCQL, VCCP

−0.3 to + 2.0

V

V

CCQH, VCCA,

V

CCD, VCCC,

V

CCH, VCCS,

−0.3 to + 4.0

V

All “3.3V tolerant” inp u t voltages

V

IN

GND − 0.3 to V

CC

+ 0.7

V

Current drain per pin excluding V

CC

and GND I 10 mA

Operating temperature range T

J

0 to + 95

°C

Storage temperature T

STG

−55 to +125 °C

Note: 1. GND = 0 V, V

CCP, VCCQL

= 1.8 V ±5%, TJ = –0°C to +95°C, CL = 50 pF

All other V

CC

= 3.3 V ± 5%, TJ = –0°C to +95°C, CL = 50 pF

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is
not guaranteed. Stress beyond the maximum rating may affect device reliability or cause
permanent damage to the device.

Table 3-2 Thermal Characteristics

Characteristic Symbol TQFP Value Unit

Junction-to-ambient thermal resistance

1

R

θJA or θJA

49.87

°C/W

Junction-to-case ther mal resistance

2

R

θJC or θJC

9.26

°C/W

Thermal characterization parameter Ψ

JT

2.0

°C/W

Specifications

Thermal Characteristics

MOTOROLA DSP56367 3-3

Note: 1. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sid ed

printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor
Equipment and Materials International , 805 East Middlefi eld Rd., Mountai n View, CA 94043 ,
[phone].)
Measurements were done with parts mounted on thermal test boards conforming to
specification EIA/JESD51-3.

2. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI
G30-88, with the exception that the cold plate temperature is used for the case temperature.

Table 3-2 Thermal Characteristics (Continued)

Characteristic Symbol TQFP Value Unit

3-4 DSP56367 MOTOROLA

Specifications
DC Electrical Characteristics

3.4 DC ELECTRICAL CHARACTERISTICS

Table 3-3 DC Electrical Characteristics

Characteristics Symbol Min Typ Max Unit

Supply voltage V

CCQL,

V

CCP

1.71 1.8 1.89 V

V

CCQH,

V

CCA,

V

CCD,

V

CCC,

V

CCH,

V

CCS,

3.14 3.3 3.46 V

Input high voltage
D(0:23), BG

, BB, TA, ESAI_1

(except SDO4_1)

V

IH

2.0 —V

CC

V

MOD

1

/IRQ1, RESET, PINIT/NMI and all

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1

(only

SDO4_1)

/SHI

(SPI mode)

V

IHP

2.0 — V

CC

+ 0.7

SHI

(I2C mode)

V

IHP

1.5 — V

CC

+ 0.7

EXTAL

V

IHX

0.8 × V

CC

—V

CC

Input low voltage
D(0:23), BG

, BB, TA, ESAI_1

(except SDO4_1)

V

IL

–0.3 — 0.8

V

MOD

1

/IRQ1, RESET, PINIT/NMI and all

JTAG/ESAI/Timer/HDI08/DAX/ESAI_1

(only

SDO4_1)

/SHI

(SPI mode)

V

ILP

–0.3 — 0.8

SHI

(I2C mode)

V

ILP

–0.3 — 0.3 x V

CC

EXTAL

V

ILX

–0.3 — 0.2 x V

CC

Input leakage cu rrent I

IN

–10 — 1 0 µA

High impedance (off-state) input current (@ 2.4 V / 0.4 V)I

TSI

–10 — 10 µA

Output high voltag e

V

OH

2.4 — — V

Output low voltage

V

OL

— — 0.4

V

Internal supply current

2

at internal clock of 150MH z

In Normal mode

I

CCI

— 58.0 115 mA

In Wait mode I

CCW

—7.3 20mA

In Stop mode

4

I

CCS

—1.0 4 mA

PLL supply current — 1 2.5 mA

Input capacitance

5

C

IN

— — 10 pF

Specifications

AC Electrical Characteristics

MOTOROLA DSP56367 3-5

3.5 AC ELECTRICAL CHARACTERISTICS

The timing waveforms shown in the AC ele ctrical c haracterist ics sec tion are te sted with a VIL
maximum of 0.4 V and a VIH minimum of 2.4 V for all pins except EXTAL. AC timing
specifications, which are referenced to a device input signal, are measured in production with

respect to the 50% point of the respective input signal’s transition. DSP56367 output levels
are measured with the production test machine VOL and VOH reference levels set at 0.4 V and

2.4 V, respectively.

Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device

AC test conditions are 15 MHz and rated speed.

Note: 1. Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins

2. The Power Consumption Considerations section provides a formula to compute the estimated

current requirements in Normal mode. In order to obtain these results, all inputs must be
terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP
benchmarks. The power consumption numbers in this specification are 90% of the measured
results of this benchmark. This reflects typical DSP applications. Typical internal supply current
is measured with V

CC

= 3.3 V at TJ = 95°C. Maximum internal supply current is measured with

V

CC

= 3.46 V at TJ = 95°C.

3. Deleted.

4. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be
terminated (i.e., not allowed to float).

5. Periodi cally sampled and not 100% tested

6. V

CCQL

= 1.8 V ± 5%, TJ = –0°C to +95°C, CL = 50 pF

All other V

CC

= 3.3 V ± 5%, TJ = –0°C to +95°C, CL = 50 pF

7. This characteristic does not apply to PCAP.

Table 3-3 DC Electrical Characteristics (Continued)

Characteristics Symbol Min Typ Max Unit

3-6 DSP56367 MOTOROLA

Specifications
Internal Clocks

3.6 INTERNAL CLOCKS

Table 3-4 Internal Clocks

Characteristics Symbol

Expression

1, 2

Min Typ Max

Internal operation frequency with PLL
enabled

f —(Ef × MF)/

(PDF × DF)

—

Internal operation frequency with PLL
disabled

f— Ef/2 —

Internal clock high peri od

T

H

• With PLL disabled

—ETC—

• With PLL enabled and

MF ≤ 4

0.49 × ETC ×

PDF × DF/MF

— 0.51 × ETC ×

PDF × DF/MF

• With PLL enabled and
MF > 4

0.47 × ETC ×

PDF × DF/MF

— 0.53 × ETC ×

PDF × DF/MF

Internal clock low period

T

L

• With PLL disabled

—ETC—

• With PLL enabled and
MF ≤ 4

0.49 × ETC ×
PDF × DF/MF

—

0.51 × ETC ×
PDF × DF/MF

• With PLL enabled and
MF > 4

0.47 × ETC ×
PDF × DF/MF

—

0.53 × ETC ×
PDF × DF/MF

Internal clock cycle time with PLL
enabled

T

C

—ET

C

× PDF ×

DF/MF

—

Internal clock cycle time with PLL
disabled

T

C

—2 × ET

C

—

Instructio n cycle time I

CYC

—TC—

Note: 1. DF = Division Factor

Ef = External frequency
ET

C

= External clock cycle
MF = Multiplication Factor
PDF = Predivision Factor
T

C

= internal clock cycle

2. Refer to the

DSP56300 Family Manual for a detailed discussion of the PLL.

Specifications

External Clock Operation

MOTOROLA DSP56367 3-7

3.7 EXTERNAL CLOCK OPERATION

The DSP56367 system clock is an externally supplied square wave voltage source connected
to EXTAL(Figure 3-1).

Figure 3-1 External Clock Timing

Table 3-5 Clock Operation

No. Characteristics Symbol Min Max

1 Frequency of EXTAL (EXTAL Pin F r eq uency)

The rise and fall time of this external clo ck shoul d be 3 ns
maximum.

Ef 0 120.0

2

EXTAL input high

1, 2

• With PLL disabled (46.7%–53.3% duty
cycle

6

)

ET

H

3.89 ns ∞

• With PLL enabled (42.5%–57.5% duty
cycle

6

)

3.54 ns 157. 0 µs

3

EXTAL input low

1, 2

• With PLL disabled (46.7%–53.3% duty
cycle

6

)

ET

L

3.89 ns ∞

• With PLL enabled (42.5%–57.5% duty
cycle

6

)

3.54 ns 157. 0 µs

4

EXTAL cycle time

2

• With PLL disabled

ET

C

8.33 ns ∞

• With PLL enabled

8.33 ns 273. 1 µs

7

Instruction cycle time = I

CYC

= T

C

4

• With PLL disabled

I

CYC

16.66 ns ∞

• With PLL enabled

8.33 ns 8.53 µs

EXTAL

V

ILC

V

IHC

Midpoint

Note: The midpoint is 0.5 (V

IHC

+ V

ILC

).

ET

H

ET

L

ET

C

3

4

2

3-8 DSP56367 MOTOROLA

Specifications
Phase Lock Loop (PLL) Characteristics

3.8 PHASE LOCK LOOP (PLL) CHARACTERISTICS

Note: 1. Measured at 50% of the input transition

2. The maximum value for PLL enabled is given for minimum V

CO

and maximum

MF.

3. The maximum value for PLL enabled is given for minimum VCO and maximum
DF.

4. The indicated duty cycle is for the specified maximum frequency for which a part
is rated. The minimum clock high or low time required for correct operation,
however, remains the same at lower operating frequen cies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty
cycle as long as the minimum high time and low time requirements are met.

Table 3-6 PL L Characteristics

Characteristics Min Max Unit

V

CO

frequency when PLL enabled

(MF × E

f

× 2/PDF)

30 240 MHz

PLL external capacitor (PCAP pin to V

CCP

) (C

PCAP

1)

pF

•@ MF ≤ 4

(MF × 580) − 100 (MF × 780) − 140

•@ MF > 4

MF × 830 MF × 1470

Note: 1. C

PCAP

is the value of the PLL capacitor (connected between the PCAP pin and V

CCP

). The

recommended value in pF for C

PCAP

can be computed from one of the following equatio ns:

(MF x 680)-120, for MF ≤ 4, or
MF x 1100, for MF > 4.

Table 3-5 Clock Operation (Continued)

No. Characteristics Symbol Min Max

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA DSP56367 3-9

3.9 RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No. Characteristics Expression Min Max Unit

8

Delay from RESET

assertion to all pins at reset value

3

— — 26.0 ns

9

Required RESET

duration

4

• Power on, external clock generator,
PLL disabled

50 × ET

C

416.7 —ns

• Power on, external clock generator,
PLL enabled

1000 × ET

C

8.3 — µs

• During normal operation

2.5 × T

C

20.8 —ns

10 Delay from asynchronous RESET

deassertion to first

external address output (interna l reset deassertion)

5

• Minimum

3.25 × TC + 2.0 29.1 —ns

•Maximum

20.25 TC + 7.50 —176.2ns

13 Mode select setup time 30.0 — ns

14 Mode select ho ld time 0.0 — ns

15 Minimum edge-triggered interrupt request assertion width 5.5 — ns

16 Minimum ed ge-triggered interrupt request deassertion width 5.5 — ns

17 Delay from IRQA

, IRQB, IRQC, IRQ D, NMI assertion to

external memory acces s address out v alid

• Caused by first interrupt instruction
fetch

4.25 × TC + 2.0 37.4 —ns

• Caused by first interrupt instruction
execution

7.25 × TC + 2.0 62.4 —ns

18 Delay from IRQA

, IRQB, IRQC, IRQ D, NMI assertion to
general-purpose transfer out put valid caused by first
interrupt in struction ex ecution

10 × TC + 5.0 88.3 — ns

19 Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for le ve l
sensitive fa s t interrupts

1

3.75 × T

C

+ WS × TC – 10.94 — No te 7 ns

20 Delay from RD

assertion to interrupt request deassertion for

level sensitive fast interrupts

1

3.25 × TC + WS × TC – 10.94 — No te 7 ns

3-10 DSP56367 MOTOROLA

Specifications
Reset, Stop, Mode Select, and Interrupt Timing

21 Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts

1

ns

• DRAM for all WS

(WS + 3.5) × TC – 10.94 — Note 7

• SRAM WS = 1

(WS + 3.5) × TC – 10.94 — Note 7

• SRAM WS = 2, 3

(WS + 3) × TC – 10.94 — Note 7

• SRAM WS ≥ 4

(WS + 2.5) × TC – 10.94 — Note 7

24 Duration for IRQA

assertion to recover from Stop state 4.9 —

25 Delay from IRQA

assertion to fetch of first instruction

(when exiting Stop)

2, 3

• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
enabled
(OMR Bit 6 = 0)

PLC × ETC × PDF + (128 K −
PLC/2) × T

C

——ms

• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
not enabled (OMR Bit 6 = 1)

PLC × ETC × PDF + (23.75 ± 0.5)
× T

C

——ms

• PLL is active during Stop (PCTL
Bit 17 = 1) (Implies No Stop Delay)

(8.25 ± 0.5) × T

C

64.6 72.9 ns

26 Duration of level sensitive IRQA

assertion to ensure

interrupt service (when ex i ting Stop)

2, 3

• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
enabled
(OMR Bit 6 = 0)

PLC × ETC × PDF + (128K −

PLC/2) × T

C

——ms

• PLL is not active during Stop
(PCTL Bit 17 = 0) and Stop delay is
not enabled
(OMR Bit 6 = 1)

PLC × ETC × PDF + (20.5 ± 0.5)

× T

C

——ms

• PLL is active during Stop (PCTL
Bit 17 = 1) (implies no Stop delay)

5.5 × T

C

45.8 —ns

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No. Characteristics Expression Min Max Unit

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA DSP56367 3-11

27 Interrupt Reque sts Ra te

• HDI08, ESAI, ESAI_1, SHI, DAX,
Timer

12T

C

—100.0ns

•DMA

8T

C

— 66.7 ns

•IRQ, NMI (edge trigger)

8T

C

— 66.7 ns

•IRQ (level trigger)

12T

C

—100.0ns

28 DMA Requests Rate

• Data read from HDI08, ESAI,
ESAI_1, SHI, DAX

6T

C

— 50.0 ns

• Data write to HDI08, ESAI,
ESAI_1, SHI, DAX

7T

C

— 58.0 ns

•Timer

2T

C

16.7

•IRQ, NMI (edge trigger)

3T

C

— 25.0 ns

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No. Characteristics Expression Min Max Unit

3-12 DSP56367 MOTOROLA

Specifications
Reset, Stop, Mode Select, and Interrupt Timing

29 Delay from IRQA , I RQB, IRQC, IRQD , NMI assertion to

external memory (DMA source) access address out valid

4.25 × TC + 2.0 37.4 —ns

Note: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive,

timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing
restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts.
Long interrupts are recommended when using Level-sensitive mode.

2. This timing depends on several settings:

For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and
recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 s ettings.

For PLL enable, if P CTL B i t 17 is 0, the PLL is shutdo w n du ring Stop. Recovering from St o p
requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC),
may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay
counter, and stop recovery will end when the last of these two events occurs: the stop delay
counter completes count or PLL lock procedure completion.

PLC value for PLL disable is 0.

The maximum value for ET

C

is 4096 (maximum MF) divided by the desired internal

frequency (i.e., for 150 MHz it is 4096/150 MHz = 27.3 µs). During the stabilization period,
T

C

, TH, and TL will not be constant, and their width may vary, so timing may vary as well.

3. Periodically sampled and not 100% tested

4. RESET

duration is measured during the time in which RESET is asserted, VCC is valid, and

the EXTAL input is active and valid. When the V

CC

is valid, but the other “required RESET
duration” conditions (as specified above) have not been yet met, the device circuitry will be in
an uninitialized state that can result in significant power consumption and heat-up. Designs
should minimize this state to the shortest possible duration.

5. If PLL does not lose lock

6. V

CC

= 1.8 V ± 5%; TJ = 0°C to + 95°C, CL = 50 pF

7. WS = number of wait states (measured in clock cycles, number of T

C

). Use expression to

compute maximum value.

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing

No. Characteristics Expression Min Max Unit

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA DSP56367 3-13

Figure 3-2 Reset Timing

V

IH

RESET

Reset Value

First Fetch

All Pins

A0–A17

8

9 10

AA0460

3-14 DSP56367 MOTOROLA

Specifications
Reset, Stop, Mode Select, and Interrupt Timing

Figure 3-3 External Fast Interrupt Timing

A0–A17

RD

a) First Interrupt Instruction Execution

General

Purpose

I/O

IRQA

, IRQB,

IRQC

, IRQD,

NMI

b) General Purpose I/O

IRQA, IRQB,

IRQC

, IRQD,

NMI

WR

20

21

1917

18

First Interrupt Instruction

Execution/Fetch

Specifications

Reset, Stop, Mode Select, and Interrupt Timing

MOTOROLA DSP56367 3-15

Figure 3-4 External Interrupt Timing (Negative Edge-Triggered)

Figure 3-5 Operating Mode Select Timing

Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service

IRQA, IRQB,
IRQC,

IRQD,

NMI

IRQA, IRQB,

I

RQC, IRQD,

NMI

15

16

AA0463

RESET

MODA, MODB,

MODC, MODD,

PINIT

V

IH

IRQA, IRQB,
IRQD

, NMI

V

IH

V

IL

V

IH

V

IL

13

14

AA0465

First Instruction Fetch

IRQA

A0–A17

24

25

AA0466

3-16 DSP56367 MOTOROLA

Specifications
Reset, Stop, Mode Select, and Interrupt Timing

Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service

Figure 3-8 External Memory Access (DMA Source) Timing

IRQA

A0–A17

First IRQA Interrupt

Instruction Fetch

26

25

AA0467

29

DMA Source Address

First Interrupt Instruction Execution

A0–A17

RD

WR

IRQA, IRQB,

IRQC,

IRQD,

NMI

AA11

0

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-17

3.10 EXTERNAL MEMORY EXPANSION PORT (PORT A)

3.10.1 SRAM TIMING

Table 3-8 SRAM Read and Write Accesses

No. Characteristics Symbol

Expression

1

Min Max

Uni

t

100 Address valid and AA assertion pulse width t

RC

, t

WC

(WS + 1) × TC − 4.0

[1 ≤ WS ≤ 3]

12.0 —ns

(WS + 2) × T

C

− 4.0

[4 ≤ WS ≤ 7]

46.0 — ns

(WS + 3) × T

C

− 4.0

[WS ≥ 8]

87.0 — ns

101 Address and AA valid to W R

assertion t

AS

0.25 × TC − 2.0
[WS = 1]

0.1 — ns

1.25 × T

C

− 2.0

[WS ≥ 4]

8.4 — ns

102 WR

assertion pulse width t

WP

1.5 × TC − 4.0 [WS = 1] 8.5 — ns

All frequencies:

WS × T

C

− 4.0

[2 ≤ WS ≤ 3]

12.7 — ns

(WS − 0.5) × T

C

[WS ≥ 4]

19.0 — ns

103 WR

deassertion to address not valid t

WR

0.25 × TC − 2.0
[1 ≤ WS ≤ 3]

0.1 — ns

1.25 × T

C

− 2.0

[4 ≤ WS ≤ 7]

8.4 — ns

2.25 × T

C

[WS ≥ 8]

14.7 — ns

All frequencies:

1.75 × T

C

12.0 — ns

2.25 × T

C

[WS ≥ 8]

14.7 — ns

104 Address and AA valid to inp ut da ta va li d t

AA

, t

AC

(WS + 0.75) × TC − 7.0

[WS ≥ 1]

—7.6ns

3-18 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

105 RD assertion to input data valid t

OE

(WS + 0.25) × TC − 7.0

[WS ≥ 1]

—3.4ns

106 RD

deassertion to data not valid (data hold ti m e) t

OHZ

0.0 — ns

107

Address valid to WR

deassertion

2

t

AW

(WS + 0.75) × TC − 4.0

[WS ≥ 1]

10.6 — ns

108 Data valid to WR

deassertion (data setup time) tDS (tDW)(WS − 0.25) × TC − 3.0

[WS ≥ 1]

3.2 — ns

109 Data hold t im e from WR

deassertion t

DH

0.25 × TC − 2.0
[1 ≤ WS ≤ 3]

0.1 — ns

1.25 × T

C

− 2.0

[4 ≤ WS ≤ 7]

8.4 — ns

2.25 × T

C

− 2.0

[WS ≥ 8]

16.7 — ns

110 WR

assertion to data active — 0.75 × TC − 3.7

[WS = 1]

2.5 — ns

0.25 × T

C

− 3.7

[2 ≤ WS ≤ 3]

0.0 —

−0.25 × T

C

− 3.7

[WS ≥ 4]

0.0 —

111 WR

deassertion to data high impedance — 0.25 × TC + 0.2

[1 ≤ WS ≤ 3]

—2.3ns

1.25 × T

C

+ 0.2

[4 ≤ WS ≤ 7]

—10.6

2.25 × T

C

+ 0.2

[WS ≥ 8]

—18.9

112 Previous RD

deassertion to data active (write) — 1.25 × TC − 4.0

[1 ≤ WS ≤ 3]

6.4 — ns

2.25 × T

C

− 4.0

[4 ≤ WS ≤ 7]

14.7 —

3.25 × T

C

− 4.0

[WS ≥ 8]

23.1 —

Table 3-8 SRAM Read and Write Accesses (Continued)

No. Characteristics Symbol

Expression

1

Min Max

Uni

t

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-19

113 RD deassertion time 0.75 × TC − 4.0

[1 ≤ WS ≤ 3]

2.2 —ns

1.75 × T

C

− 4.0

[4 ≤ WS ≤ 7]

10.6 — ns

2.75 × T

C

− 4.0

[WS ≥ 8]

18.9 — ns

114 WR

deassertion time 0.5 × TC − 4.0

[WS = 1]

0.2 — ns

T

C

− 2.0

[2 ≤ WS ≤ 3]

6.3 — ns

2.5 × T

C

− 4.0

[4 ≤ WS ≤ 7]

16.8 — ns

3.5 × T

C

− 4.0

[WS ≥ 8]

25.2 — ns

115 Address valid to RD

assertion 0.5 × TC − 4.0 0.2 — ns

116 RD

assertion pulse width (WS + 0.25) × TC −4.0 6.4 — ns

117 RD

deassertion to address not valid 0.25 × TC − 2.0

[1 ≤ WS ≤ 3]

0.1 — ns

1.25 × T

C

− 2.0

[4 ≤ WS ≤ 7]

8.4 — ns

2.25 × T

C

− 2.0

[WS ≥ 8]

16.7 — ns

118

TA

setup before RD or WR deassertion

4

0.25 × TC + 2.0 4.1 — ns

119 TA

hold after RD or WR deassertion 0.0 — ns

Note: 1. WS is the number of wait states specified in the BCR.

2. Timings 100, 107 are guaranteed by design, not tested.

3. All timings for 100 MHz are measured from 0.5

· Vcc to .05 · Vcc

4. In the case of TA

negation: timing 118 is relative to the deassertion edge of RD or WR were

TA

to remain active

Table 3-8 SRAM Read and Write Accesses (Continued)

No. Characteristics Symbol

Expression

1

Min Max

Uni

t

3-20 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

Figure 3-9 SRAM Read Access

A0–A17

RD

WR

D0–D23

AA0–AA2

115 105 106

113

104

116

117

100

AA0468

TA

119

Data

In

118

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-21

Figure 3-10 SRAM Write Access

A0–A17

WR

RD

Data

Out

D0–D23

AA0–AA2

100

102101

107

114

108

109

103

TA

119

118

3-22 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

3.10.2 DRAM TIMING

The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary
selection only. Final selection should be based on the timing provided in the following tables.
As an example, the selection guide suggests that 4 wait states must be used for 100 MHz
operation when using Page Mode DRAM. However, by using the information in the
appropriate table, a designer may choose to evaluate whether fewer wait states might be used
by determining which timing prevents operation at 100 MHz, running the chip at a slightly
lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control
factors such as capacitive and resistive load to improve overall system performance.

Figure 3-11 DRAM Page Mode Wait States Selection Guide

Chip Frequency
(MHz)

DRAM Type

(t

RAC

ns)

100

80

70

60

40 66 80 100

1 Wait States

2 Wait States

3 Wait States

4 Wait States

Note: This figure should be use for primary selection.

For exact and detailed timings see the
following tables.

AA04

7

50

120

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-23

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Apps)

No. Characteristics Symbol Expression

20 MHz

6

30 MHz

6

Unit

Min Max Min Max

131 Page mode cycle time for two

consecutive accesses of the same
direction

t

PC

2 × T

C

100.0 —66.7—ns

Page mode cycle time fo r mi xed (read
and write) accesses

1.25 × T

C

62.5 — 41.7 —

132 CAS

assertion to data valid (read) t

CAC

TC − 7.5 — 42.5 — 25.8 ns

133 Column address valid to data val id

(read)

t

AA

1.5 × TC − 7.5 — 67.5 — 42.5 ns

134 CAS

deassertion to data not valid (read

hold time)

t

OFF

0.0 — 0.0 — ns

135 Last CAS

assertion to RAS deassertion t

RSH

0.75 × TC − 4.0 33.5 — 21.0 — ns

136 Previous CAS

deassertion to RAS

deassertion

t

RHCP

2 × TC − 4.0 96.0 — 62.7 — ns

137 CAS

assertion pulse width t

CAS

0.75 × TC − 4.0 33.5 — 21.0 — ns

138 Last CAS

deassertion to RAS

deassertion

4

• BRW[1:0] = 00

t

CRP

1.75 × TC − 6.0 81.5 —52.3—ns

• BRW[1:0] = 01

3.25 × TC − 6.0 156.5 102.2 —ns

• BRW[1:0] = 10

4.25 × TC − 6.0 206.5 135.5 —ns

• BRW[1:0] = 11

6.25 × TC – 6.0 306.5 — 202.1 — ns

139 CAS

deassertion pulse width t

CP

0.5 × TC − 4.0 21.0 — 12.7 — ns

140 Column address valid to CAS

assertion t

ASC

0.5 × TC − 4.0 21.0 — 12.7 — ns

141 CAS

assertion to column address not

valid

t

CAH

0.75 × TC − 4.0 33.5 — 21.0 — ns

142 Last column address valid to RAS

deassertion

t

RAL

2 × TC − 4.0 96.0 — 62.7 — ns

143 WR

deassertio n to CAS assertion t

RCS

0.75 × TC − 3.8 33.7 — 21.2 — ns

144 CAS

deassertion to WR assertion t

RCH

0.25 × TC − 3.7 8.8 — 4.6 — ns

145 CAS

assertion to WR deassertion t

WCH

0.5 × TC − 4.2 20.8 — 12.5 — ns

146

WR

assertion pulse width

tWP 1.5 × TC − 4.5 70.5 — 45.5 — ns

3-24 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

147 Last WR assertion to RAS deassertion t

RWL

1.75 × TC − 4.3 83.2 —54.0—ns

148 WR

assertion to CAS deassertion t

CWL

1.75 × TC − 4.3 83.2 — 54.0 — ns

149 Data valid to CAS

assertion (Write) t

DS

0.25 × TC − 4.0 8.5 — 4.3 — ns

150 CAS

assertion to data not valid (write) t

DH

0.75 × TC − 4.0 33.5 — 21.0 — ns

151 WR

assertion to CAS assertion t

WCS

TC − 4.3 45.7 — 29.0 — ns

152 Last RD

assertion to RAS deassertion t

ROH

1.5 × TC − 4.0 71.0 — 46.0 — ns

153 RD

assertion to data valid tGA T

C

− 7.5 — 42.5 — 25.8 ns

154

RD

deassertion to data not valid

5

t

GZ

0.0 — 0.0 — ns

155 WR

assertion to data active 0.75 × TC − 0.3 37.2 — 24.7 — ns

156 WR

deassertion to data high

impedance

0.25 × T

C

— 12.5 — 8.3 ns

Note: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. All the timings are calculated for the worst case. Some of the timings are b etter for specific cases
(e.g., t

PC

equals 2 × TC for read-after-read or write-after-write sequences).

4. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be
inserted in each DRAM out-of-page access.

5. RD

deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ

.

6. Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state see Figur e 3-11.

Table 3-10 DRAM Page Mode Timings, Two Wait States

No. C haracteristics Symbol Expression

66 MHz 80 MHz

Unit

Min Max Min Max

131 Page mode cycle time for two

consecutive accesses of the
same direction

t

PC

2 × T

C

45.4—37.5— ns

Page mode cycle ti me for
mixed (read and write)
accesses

1.25 × T

C

41.1—34.4—

Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Apps)

No. Characteristics Symbol Expression

20 MHz

6

30 MHz

6

Unit

Min Max Min Max

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-25

132 CAS assertion to data valid

(read)

t

CAC

1.5 × TC − 7.5 — 15.2 — — ns

1.5 × T

C

− 6.5 — — — 12.3 ns

133 Column address valid to da ta

valid (read)

t

AA

2.5 × TC − 7.5 — 30.4 — — ns

2.5 × T

C

− 6.5 — — — 24.8 ns

134 CAS

deassertion to data not

valid (read hold time)

t

OFF

0.0—0.0— ns

135 Last CAS

assertion to RAS

deassertion

t

RSH

1.75 × TC − 4.0 22.5 — 17.9 — ns

136 Previous CAS

deassertion to

RAS

deassertion

t

RHCP

3.25 × TC − 4.0 45.2 — 36.6 — ns

137 CAS

assertion pulse width t

CAS

1.5 × TC − 4.0 18.7 — 14.8 — ns

138 Last CAS

deassertion to RAS

deassertion

5

• BRW[1:0] =
00

t

CRP

2.0 × TC − 6.0 24.4 —19.0— ns

• BRW[1:0] =
01

3.5 × TC − 6.0 47.2 —37.8— ns

• BRW[1:0] =
10

4.5 × TC − 6.0 62.4 —50.3— ns

• BRW[1:0] =
11

6.5 × TC − 6.0 92.8 —75.3— ns

139 CAS

deassertion pulse width t

CP

1.25 × TC − 4.0 14.9 — 11.6 — ns

140 Column address valid to CAS

assertion

t

ASC

TC − 4.0 11.2 — 8.5 — ns

141 CAS

assertion to column

address not valid

t

CAH

1.75 × TC − 4.0 22.5 — 17.9 — ns

142 Last column ad dress valid to

RAS

deassertion

t

RAL

3 × TC − 4.0 41.5 — 33.5 — ns

143 WR

deassertion to CAS

assertion

t

RCS

1.25 × TC − 3.8 15.1 — 11.8 — ns

144 CAS

deassertion to WR

assertion

t

RCH

0.5 × TC − 3.7 3.9—2.6— ns

Table 3-10 DRAM Page Mode Timings, Two Wait States (Continued)

No. Characteristics Symbol Expression

66 MHz 80 MHz

Unit

Min Max Min Max

3-26 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

145 CAS assertion to WR

deassertion

t

WCH

1.5 × TC − 4.2 18.5 —14.6— ns

146 WR

assertion pulse width tWP 2.5 × TC − 4.5 33.5 — 26.8 — ns

147 Last WR

assertion to RAS

deassertion

t

RWL

2.75 × TC − 4.3 33.4 — 26.8 — ns

148 WR

assertion to CAS

deassertion

t

CWL

2.5 × TC − 4.3 33.6 — 27.0 — ns

149 Data valid to CA S

assertion

(write)

t

DS

0.25 × TC − 3.7 0.1 — — — ns

0.25 × T

C

− 3.0 — — 0.1 — ns

150 CAS

assertion to data not valid

(write)

t

DH

1.75 × TC − 4.0 22.5 — 17.9 — ns

151 WR

assertion to CAS assertion t

WCS

TC − 4.3 10.9 — 8.2 — ns

152 Last RD

assertion to RAS

deassertion

t

ROH

2.5 × TC − 4.0 33.9 — 27.3 — ns

153 RD

assertion to d ata valid t

GA

1.75 × TC − 7.5 — 19.0 — — ns

1.75 × T

C

− 6.5 — — — 15.4 ns

154 RD

deassertion to data not

valid

6

t

GZ

0.0—0.0— ns

155 WR

assertion to data active 0.75 × TC − 0.3 11.1 — 9.1 — ns

156 WR

deassertion to data high

impedance

0.25 × T

C

—3.8—3.1ns

Note: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56367.

4. All the timings are calculated for the worst case. Some of the timings are better for specific
cases (e.g., t

PC

equals 3 × TC for read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be
inserted in each DRAM out-of-page access.

6. RD

deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ.

7. There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See
Figure 3-11)

Table 3-10 DRAM Page Mode Timings, Two Wait States (Continued)

No. C har act eristic s Symbol Expression

66 MHz 80 MHz

Unit

Min Max Min Max

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-27

Table 3-1 1 DRAM Page Mode Timings, Three Wait States

No. Characteristics Symbol Expression Min

Ma

x

Unit

131 Page mode cycle time for two consecuti ve acc e s ses of the same

direction

t

PC

2 × T

C

40.0 —ns

Page mode cycle time fo r mixed (read and write) accesses 1.25 × T

C

35.0 —

132 CAS

assertio n to d ata valid (r ead) t

CAC

2 × TC − 7.0 — 13.0 ns

133 Column addr ess va li d to da t a va lid (read) t

AA

3 × TC − 7.0 — 23.0 ns

134 CAS

deassertion to data not valid (rea d hold time) t

OFF

0.0 — ns

135 Last CAS

assertion to RAS deassertion t

RSH

2.5 × TC − 4.0 21.0 — ns

136 Previous CAS

deassertion to RAS deassertion t

RHCP

4.5 × TC − 4.0 41.0 — ns

137 CAS

assertion pulse width t

CAS

2 × TC − 4.0 16.0 — ns

138

Last CAS

deassertion to RAS assertion

5

• BRW[1:0] = 00

t

CRP

2.25 × TC − 6.0 —— ns

• BRW[1:0] = 01

3.75 × TC − 6.0 —— ns

• BRW[1:0] = 10

4.75 × TC − 6.0 41.5 —ns

• BRW[1:0] = 11

6.75 × TC − 6.0 61.5 —ns

139 CAS

deassertion pulse width t

CP

1.5 × TC − 4.0 11.0 — ns

140 Column address valid to CAS

assertion t

ASC

TC − 4.0 6.0 — ns

141 CAS

assertio n to column add r ess not vali d t

CAH

2.5 × TC − 4.0 21.0 — ns

142 Last column address valid to RAS

deassertion t

RAL

4 × TC − 4.0 36.0 — ns

143 WR

deassertion to CAS assertion t

RCS

1.25 × TC − 4.0 8.5 — ns

144 CAS

deassertion to WR assertion t

RCH

0.75 × TC − 4.0 3.5 — ns

145 CAS

assertion to WR deassertion t

WCH

2.25 × TC − 4.2 18.3 — ns

146 WR

assertion pulse width t

WP

3.5 × TC − 4.5 30.5 — ns

147 Last WR

assertion to RAS deassertion t

RWL

3.75 × TC − 4.3 33.2 — ns

148 WR

assertion to CAS deassertion t

CWL

3.25 × TC − 4.3 28.2 — ns

149 Data valid to CAS

assertion (write) t

DS

0.5 × TC − 4.0 1.0 — ns

3-28 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

150 CAS asse rt io n to da ta not valid (write) t

DH

2.5 × TC − 4.0 21.0 —ns

151 WR

assertion to CAS assertion t

WCS

1.25 × TC − 4.3 8.2 — ns

152 Last RD

assertion to RAS deassertion t

ROH

3.5 × TC − 4.0 31.0 — ns

153 RD

assertion to d ata valid t

GA

2.5 × TC − 7.0 — 18.0 ns

154

RD

deassertion to data not valid6

t

GZ

0.0 — ns

155 WR

assertion to data active 0.75 × TC − 0.3 7.2 — ns

156 WR

deassertion to data high impedance 0.25 × T

C

—2.5ns

Note: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for DSP56367.

4. All the timings are calculated for the worst case. Some of the timings are better for specific
cases (e.g., t

PC

equals 4 × TC for read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defines the number of wait states that should be
inserted in each DRAM out-of page-access.

6. RD

deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ

.

Table 3-11 DRAM Page Mode Timings, Three Wait States (Continued)

No. Characteristics Symbol Expression Min

Ma

x

Unit

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-29

Table 3-1 2 DRAM Page Mode Timings, Four Wait States

No. Characteristics Symbol Expression Min Max

131 Page mode cycle time for two co ns ecutive accesses of the s ame

direction.

t

PC

5 × T

C

41.7 —ns

Page mode cycle time for mixed (read and write ) acc es s es 4.5 × T

C

37.5 —

132 CAS

assertion to data valid (read) t

CAC

2.75 × TC − 7.0 — 15.9 ns

133 Column addre ss val id t o da ta valid (read) t

AA

3.75 × TC − 7.0 — 24.2 ns

134 CAS

deassertion to data not valid (read hold time) t

OFF

0.0—ns

135 Last CAS

assertion to RAS deassertion t

RSH

3.5 × TC − 4.0 25.2 — ns

136 Previous CAS

deassertion to RAS de assertion t

RHCP

6 × TC − 4.0 46.0 — ns

137 CAS

assertion pulse width t

CAS

2.5 × TC − 4.0 16.8 — ns

138

Last CAS

deassertion to RAS assertion

5

• BRW[1:0] = 00

t

CRP

2.75 × TC − 6.0 ——ns

• BRW[1:0] = 01

4.25 × TC − 6.0 ——

• BRW[1:0] = 10

5.25 × TC − 6.0 37.7 —

• BRW[1:0] = 11

7.25 × TC − 6.0 54.4 —

139 CAS

deassertion pulse width t

CP

2 × TC − 4.0 12.7 — ns

140 Column addre ss val id to CA S

assertion t

ASC

TC − 4.0 4.3—ns

141 CAS

assertion to column address not valid t

CAH

3.5 × TC − 4.0 25.2 — ns

142 Last column address valid to RAS

deassertion t

RAL

5 × TC − 4.0 37.7 — ns

143 WR

deassertion to CAS assertion t

RCS

1.25 × TC − 4.0 6.4—ns

144 CAS

deassertion to WR assertion t

RCH

1.25 × TC − 4.0 6.4—ns

145 CAS

assertion to WR deassertion t

WCH

3.25 × TC − 4.2 22.9 — ns

146 WR

assertion pulse width t

WP

4.5 × TC − 4.5 33.0 — ns

147 Last WR

assertion to RAS deassertion t

RWL

4.75 × TC − 4.3 35.3 — ns

148 WR

assertion to CAS deassertion t

CWL

3.75 × TC − 4.3 26.9 — ns

149 Data valid to CAS

assertion (write) t

DS

0.5 × TC − 4.0 0.2—ns

150 CAS

assertion to data not valid (write) t

DH

3.5 × TC − 4.0 25.2 — ns

151 WR

assertion to CAS assertion t

WCS

1.25 × TC − 4.3 6.1—ns

3-30 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

152 Last RD assertion to RAS deassertion t

ROH

4.5 × TC − 4.0 33.5 —ns

153 RD

assertion to data valid t

GA

3.25 × TC − 7.0 — 20.1 ns

154

RD

deassertion to data not valid

6

t

GZ

0.0—ns

155 WR

assertion to data active 0.75 × TC − 0.3 5.9—ns

156 WR

deassertion to data high impedance 0.25 × T

C

—2.1ns

Note: 1. The number of wait states for Page mode access is specified in the DCR.

2. The refresh period is specified in the DCR.

3. The asynchronous delays specified in the expressions are valid for

DSP56367.

4. All the timings are calculated for the worst case. Some of the timings are better for specific

cases (e.g., t

PC

equals 3 × TC for read-after-read or write-after-write sequences).

5. BRW[1:0] (DRAM control register bits) defin e s the number of wait states that should be

inserted in each DRAM out-of-page access.

6. RD

deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF

and not t

GZ

.

Table 3-12 DRAM Page Mode Timings, Four Wait States (Continued)

No. Characteristics Symbol Expression Min Max

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-31

Figure 3-12 DRAM Page Mode Write Access es

RAS

CAS

A0–A17

WR

RD

D0–D23

Column

Row

Data Out Data Out Data Out

Last Column

Column

Add

Address

Address

Address

136

135131

139

141

137

140

142

147

144151

148146

155 156

150

138

145

143

149

AA0473

3-32 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

Figure 3-13 DRAM Page Mode Read Accesses

RAS

CAS

A0–A17

WR

RD

D0–D23

Column

Last Column

Column

Row

Data In Data InData In

Add

Address Address

Address

136

135131

137

140

141 142

143

152133

153

132

138139

134

154

AA0474

Specifications

External Memory Expansion Port (Port A)

MOTOROLA DSP56367 3-33

Figure 3-14 DRAM Out-of-Page Wait States Selection Guide

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

No.

Characteristics

3

Symbol Expression

20 MHz

4

30 MHz

4

Unit

Min Max Min Max

157 Random read or write cycle time t

RC

5 × T

C

250.0 — 166.7 — ns

158 RAS

assertion to data valid (read) t

RAC

2.75 × TC − 7.5 — 130.0 — 84.2 ns

159 CAS

assertion to data valid (read) t

CAC

1.25 × TC − 7.5 — 55.0 — 34.2 ns

160 Column address valid to data valid

(read)

t

AA

1.5 × TC − 7.5 — 67.5 — 42.5 ns

161 CAS

deassertion to data not valid (read

hold time)

t

OFF

0.0 — 0.0 — ns

162 RAS

deassertion to RAS assertion tRP 1.75 × TC − 4.083.5—54.3—ns

Chip Frequency
(MHz)

DRAM Type

(t

RAC

ns)

100

80

70

50

66 80 100

4 Wait States

8 Wait States

11 Wait States

15 Wait States

Note:This figure should be use for primary selection. For

exact and detailed timings see the following tables.

60

40

120

AA04

7

3-34 DSP56367 MOTOROLA

Specifications
External Memory Expansion Port (Port A)

163 RAS assertion pulse width t

RAS

3.25 × TC − 4.0 158.5 — 104.3 — ns

164 CAS

assertion to RAS deassertion t

RSH

1.75 × TC − 4.083.5—54.3—ns

165 RAS

assertion to CAS deassertion t

CSH

2.75 × TC − 4.0 133.5 — 87.7 — ns

166 CAS

assertion pulse width t

CAS

1.25 × TC − 4.058.5—37.7—ns

167 RAS

assertion to CAS assertion t

RCD

1.5 × TC ± 2 73.0 77.0 48.0 52.0 ns

168 RAS

assertion to column address valid t

RAD

1.25 × TC ± 2 60.5 64.5 39.7 43.7 ns

169 CAS

deassertion to RAS assertion t

CRP

2.25 × TC − 4.0 108.5 — 71.0 — ns

170 CAS

deassertion pulse width t

CP

1.75 × TC − 4.083.5—54.3—ns

171 Row address valid to RAS

assertion t

ASR

1.75 × TC − 4.083.5—54.3—ns

172 RAS

assertion to row address not valid t

RAH

1.25 × TC − 4.058.5—37.7—ns

173 Column address valid to CAS

assertion t

ASC

0.25 × TC − 4.0 8.5 — 4.3 — ns

174 CAS

assertion to column address not

valid

t

CAH

1.75 × TC − 4.083.5—54.3—ns

175 RAS

assertion to column address not

valid

t

AR

3.25 × TC − 4.0 158.5 — 104.3 — ns

176 Column address valid to RAS

deassertion

t

RAL

2 × TC − 4.0 96.0—62.7—ns

177 WR

deassertion to CAS assertion t

RCS

1.5 × TC − 3.871.2—46.2—ns

178 CAS

deassertion to WR assertion t

RCH

0.75 × TC − 3.733.8—21.3—ns

179 RAS

deassertion to WR assertion t

RRH

0.25 × TC − 3.7 8.8 — 4.6 — ns

180 CAS

assertion to WR deassertion t

WCH

1.5 × TC − 4.270.8—45.8—ns

181 RAS

assertion to WR deassertion t

WCR

3 × TC − 4.2 145.8 — 95.8 — ns

182 WR

assertion pulse width t

WP

4.5 × TC − 4.5 220.5 — 145.5 — ns

183 WR

assertion to RAS deassertion t

RWL

4.75 × TC − 4.3 233.2 — 154.0 — ns

184 WR

assertion to CAS deassertion t

CWL

4.25 × TC − 4.3 208.2 — 137.4 — ns

185 Data valid to CAS

assertion (write) t

DS

2.25 × TC − 4.0 108.5 — 71.0 — ns

186 CAS

assertion to data not valid (write ) t

DH

1.75 × TC − 4.083.5—54.3—ns

187 RAS

assertion to data not valid (write ) t

DHR

3.25 × TC − 4.0 158.5 — 104.3 — ns

Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States

No.

Characteristics

3

Symbol Expression

20 MHz

4

30 MHz

4

Unit

Min Max Min Max