Motorola DSP56362 User Manual
MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR PRODUCT INFORMATION
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cale Semiconductor,
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Product Brief
DSP56362
24-BIT AUDIO DIGITAL SIGNAL PROCESSOR
The DSP56362 is a high performance DSP optimized for cost-sensative consumer audio
applications. A general purpose DSP56362 is available as well as a multimode, multichannel audio
decoder for consumer applications such as Audio/Video (A/V) receivers, surround sound decoders,
Digital Versatile Disk (DVD) players, digital TV, and other audio applications. The DSP56362
supports all of the popular multichannel audi o decoding formats, including Dolby Digital Surround,
Moving Picture Experts Group Standard 2 (MPEG2), and Digital Theater Systems (DTS), in a single
device with sufficient MIPS resources for customer defined post-processing featur es such as bass
management, 3D virtual surround, Lucasfilm THX5.1, soundfield processing, and advanced
equalization.
The DSP56362, Figure 1,is member of the 56300 Motorola Symphony™ DSP Family. The
DSP56362 utilizes the single-instruction-per-clock-cycle DSP56300 core, while retaining code
compatibility with the DSP5600 0 core family. The DSP56362 c ontains audio-spec ific peripher als and
an on-board software architecture as shown in Figure 2 and is offered in a 100/120 MHz/MIPS
version at a nominal 3.3 V.
EXTAL
CLKOUT
PINIT/NMI
Triple
Timer
RESET
(SPDIF)
Address
Generation
Unit
Six Channel
DMA Unit
Internal
Data
Bus
Switch
Clock
Generator
PLL
2
DAX
Interface
PIO_EB
Program
Interrupt
Controller
1216
Host
ESAI
Perip he ra l
Expansion Area
24-BIT
DSP56300
Core
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
M O D C/IR QC
M O D D/IR QD
5
SHI
Program RAM/
Instruction
Cache
3072 × 24
Program RO M
30K × 24
Bootstrap ROM
PM_EB
DDB
YDB
XDB
PDB
GDB
Program
Address
Generator
X Data
RAM
5632 × 24
ROM
6144 × 24
YAB
XAB
PAB
DAB
24
×
24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5632 × 24
6144 × 24
XM_EB
Da ta A LU
Y Data
RAM
ROM
YM_EB
Memory
Expansion
Area
External
Address
Bus
Switch
DRAM/SRAM
Bus
Interfa ce
&
I - C a ch e
Control
External
Data Bus
Switch
Power
Mgmt.
JTAG
OnCE™
18
Address
11
Control
24
Data
6
AA0456G
Figure 1 DSP56362 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
DSP56362 Product Brief
©1999 MOTOROLA, INC.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DSP56362
24-Bit Audio Digital Signal Processor
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cale Semiconductor,
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DSP5 6362
PCM or
Compresse
d Data
8-b it Data In te r fa c e
2
S
I
Rx
Input
Buffer
Auto
Detector
P a r allel
Host/Data
Inte r fa c e
External
Host CPU/
Dolby
Digital
MPEG2
5.1/7.1
DTS
PLL
System
Clock
Dolby
Pro Logic
Select
Noise
Sequencer
DSP Clock
General
Purpose
I/O
User
Programm able
I/O
Figure 2 DSP56362 Surround Decoder Functionality
Features
• Multimode, multichannel decoder software functionality
– Dolby Digital and Pro Logic
– MPEG2 5.1
– DTS
• Digital audio post-processing capabilities
– Bass management
– 3D Virtual surround sound
– Lucasfilm THX5.1
– Soundfield processing
– Equalization
• Digital Signal Processing Core
– 100/120 Million Instructions Per Second (MIPS) with an 100/120 MHz clock at a
nominal 3.3 V
– Object code compatible with the DSP56000 core with highly parallel instruction set
– Data Arithmetic Logic Unit (Data ALU)
– Program Control Unit (PCU)
– Direct Memory Access (DMA)
– Software programmable PLL-based frequency synthesizer for the core clock
User
Defined
Processing:
—
—
Select
—
—
—
Bass mgt
3D Virtual
Surround
Lucasfilm
THX5.1
Soundfields
Equalization
Serial
Host
Inte rface
SPI/I
Protocol
L/R
2
S
I
Tx
C/Sub
2
I
S
Tx
Sr/Sl
2
S
I
Tx
Output Delay Buffer
L/R
2
I
S
Tx
IEC95 8
Tx
JTAG /OnC E™
Inte rf a c e
2
C
Dedicated
Debugging
Port
Le ft/Righ t
Stereo Out
Center/
Subwoo fer
Out
R ig h t/L e ft
Surround
Sound O ut
Headphone
Mix Down/
Aux. Surrou n d
AA0565G
2 DSP56362 Product Brief MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
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