Motorola DSP56309 User Manual

DatasheetDirect.com

Your dedicated source for free downloadable datasheets.

 Over one million datasheets
 Optimized search function
 Rapid quote option
 Free unlimited downloads

Visit www.datasheetdirect.com

This datasheet has been downloaded by http://www.datasheetdirect.com/

to get your free datasheets.

DSP56309 OVERVIEW

SIGNAL/CONNECTION DESCRIPTIONS

MEMORY CONFIGURATION

CORE CONFIGURATION

GENERAL PURPOSE I/O

HOST INTERFACE (HI08)

ENHANCED SYNCHRONOUS SERIAL INTERFACE

1

2

3

4

5

6

7

SERIAL COMMUNICATION INTERFACE (SCI)

TIMER MODULE

ON-CHIP EMULATION MODULE

JTAG PORT

8

9

10

11

ABOOTSTRAP PROGRAM

BEQUATES

CBSDL LISTING

DPROGRAMMING REFERENCE

IINDEX

1

2

3

4

5

6

7

DSP56309 OVERVIEW

SIGNAL/CONNECTION DESCRIPTIONS

MEMORY CONFIGURATION

CORE CONFIGURATION

GENERAL PURPOSE I/O

HOST INTERFACE (HI08)

ENHANCED SYNCHRONOUS SERIAL INTERFACE

8

9

10

11

A BOOTSTRAP PROGRAM

B EQUATES

C BSDL LISTING

SERIAL COMMUNICATION INTERFACE (SCI)

TIMER MODULE

ON-CHIP EMULATION MODULE

JTAG PORT

D PROGRAMMING REFERENCE

I INDEX

Rev. 0

DSP56309

24-Bit Digital Signal Processor

UserÕs Manual

Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598

ã

Ò

This document (and other documents) can be viewed on the World Wide
Web at http://www.mot.com/SPS/DSP/documentation/

This manual is one of a set of three documents. You need the following
manuals to have complete product information: Family Manual, UserÕs
Manual, and Technical Data.

OnCE
Intel

ä

is a trademark of Motorola, Inc.

Ò

is a registered trademark of the Intel Corporation.

All other trademarks are those of their respective owners.

MOTOROLA INC., 1998

Reg. U.S. Pat. & Tm. Off.

Order this document by DSP56309UM/D

Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function, or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not authorized for use as components in life support
devices or systems intended for surgical implant into the body or intended to
support or sustain life. Buyer agrees to notify Motorola of any such intended end use
whereupon Motorola shall determine availability and suitability of its product or
products for the use intended. Motorola and

are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative
Action Employer.

TABLE OF CONTENTS

SECTION 1 DSP56309 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4 DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.5 DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.2 Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5.3 Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . . 1-8

1.6.1 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.6.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.6.1.2 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . 1-9

1.6.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . 1-9

1.6.3 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . 1-10

1.6.4 PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.6.5 JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . 1-11

1.6.6 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.6.7 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . 1-12

1.7 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.8 DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.9 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15

1.10 DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15

1.10.1 GPIO Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.10.2 Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.10.3 Enhanced Synchronous Serial Interface (ESSI) . . . . . . . 1-16

1.10.4 Serial Communications Interface (SCI) . . . . . . . . . . . . . . 1-16

1.10.5 Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . 2-1

2.1 SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

MOTOROLA DSP56309UM/D iii

2.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5 PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9

2.6.1 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.6.2 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.6.3 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.7 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14

2.8 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.8.1 Host Port Usage Considerations. . . . . . . . . . . . . . . . . . . 2-16

2.8.2 Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24

2.9.1 ESSI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24

2.9.2 ESSI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.10 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32

2.11 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.12 ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

SECTION 3 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . 3-1

3.1 MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.2 Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.2.1 X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.2.2 Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2 RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.1 On-Chip Program Memory (Program RAM) . . . . . . . . . . . 3-6

3.2.2 On-Chip X Data Memory (X Data RAM) . . . . . . . . . . . . . . 3-6

3.2.3 On-Chip Y Data Memory (Y Data RAM) . . . . . . . . . . . . . . 3-7

3.2.4 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.1 Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . 3-7

3.3.2 RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.5 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18

iv DSP56309UM/D MOTOROLA

SECTION 4 CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . 4-1

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3 BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.1 Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.2 Modes 1 to 7: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.3 Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3.4 Mode 9: Boot from Byte-Wide External Memory . . . . . . . . 4-7

4.3.5 Mode A: Boot from SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3.6 Mode B: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3.7 Modes C, D, E, F: Boot from HI08 . . . . . . . . . . . . . . . . . . . 4-8

4.3.7.1 Mode C: In ISA/DSP5630X Mode (8-Bit Bus) . . . . . . . 4-8

4.3.7.2 Mode D: In HC11 Non-multiplexed Mode . . . . . . . . . . 4-8

4.3.7.3 Mode E: In 8051 Multiplexed Bus Mode . . . . . . . . . . . 4-9

4.3.7.4 Mode F: In 68302/68360 Bus Mode . . . . . . . . . . . . . . . 4-9

4.4 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9

4.4.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4.2 Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.3 Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . 4-14

4.5 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16

4.6 OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . 4-17

4.7 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.7.1 PCTL PLL Multiplication Factor Bits 0Ð11 . . . . . . . . . . . . 4-18

4.7.2 PCTL XTAL Disable Bit (XTLD) Bit 16. . . . . . . . . . . . . . . 4-18

4.7.3 PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23. . . . 4-18

4.8 DEVICE IDENTIFICATION REGISTER (IDR) . . . . . . . . . . . 4-18

4.9 AA CONTROL REGISTERS (AAR0ÐAAR3) . . . . . . . . . . . . 4-19

4.10 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20

SECTION 5 GENERAL-PURPOSE I/O . . . . . . . . . . . . . . . . . . . . 5-1

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.1 Port B Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.2 Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2.3 Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.4 Port E Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4

MOTOROLA DSP56309UM/D v

5.2.5 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

SECTION 6 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . 6-1

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2 HI08 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.1 Host to DSP Core Interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.2 HI08-to-Host Processor Interface . . . . . . . . . . . . . . . . . . . 6-4

6.3 HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.4 HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.5 HI08 DSP SIDE PROGRAMMERÕS MODEL. . . . . . . . . . . . . 6-8

6.5.1 Host Receive Data Register (HRX). . . . . . . . . . . . . . . . . . 6-8

6.5.2 Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . 6-9

6.5.3 Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . 6-9

6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . 6-10

6.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . 6-10

6.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2. . 6-10

6.5.3.4 HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 . . . . . . . . . . . 6-10

6.5.3.5 HCR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10

6.5.4 Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 6-11

6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . 6-11

6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . 6-11

6.5.4.3 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . 6-11

6.5.4.4 HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 . . . . . . . . . . . 6-11

6.5.4.5 HSR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11

6.5.5 Host Base Address Register (HBAR) . . . . . . . . . . . . . . . 6-12

6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . 6-12

6.5.5.2 HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12

6.5.6 Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . 6-12

6.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . 6-13

6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . 6-13

6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . 6-13

6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . 6-13

6.5.6.5 HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . 6-14

6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5. . . . . 6-14

6.5.6.7 HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . 6-14

6.5.6.8 HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14

vi DSP56309UM/D MOTOROLA

6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 . . . . . 6-14

6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . 6-14

6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10 . . 6-15

6.5.6.12 HPCR Host Multiplexed Bus (HMUX) Bit 11. . . . . . . . 6-15

6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . 6-15

6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . 6-16

6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14. . . . . . . . . 6-16

6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . 6-16

6.5.7 Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . 6-17

6.5.8 Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . 6-17

6.5.9 DSP Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-18

6.5.10 Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . 6-19

6.6 HI08-EXTERNAL HOST PROGRAMMERÕS MODEL . . . . . 6-20

6.6.1 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . 6-22

6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . 6-23

6.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1. . . . . . . . 6-23

6.6.1.3 ICR Double Host Request (HDRQ) Bit 2. . . . . . . . . . . 6-23

6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . 6-24

6.6.1.7 ICR Reserved Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

6.6.1.8 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . 6-24

6.6.2 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . 6-25

6.6.2.1 CVR Host Vector (HV[6:0]) Bits 0Ð6 . . . . . . . . . . . . . . 6-25

6.6.2.2 CVR Host Command Bit (HC) Bit 7. . . . . . . . . . . . . . . 6-26

6.6.3 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . 6-26

6.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . 6-26

6.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . 6-27

6.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . 6-27

6.6.3.4 ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.5 ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.6 ISR Reserved Bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27

6.6.3.7 ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . 6-27

6.6.4 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . 6-28

6.6.5 Receive Byte Registers (RXH: RXM: RXL) . . . . . . . . . . . 6-28

6.6.6 Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . 6-29

MOTOROLA DSP56309UM/D vii

6.6.7 Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-30

6.6.8 General-Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30

6.7 SERVICING THE HOST INTERFACE . . . . . . . . . . . . . . . . 6-31

6.7.1 HI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . 6-31

6.7.2 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31

6.7.3 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32

6.8 HI08 PROGRAMMING MODEL QUICK REFERENCE. . . . 6-34

SECTION 7 ENHANCED SYNCHRONOUS SERIAL INTERFACE (ESSI)

7-1

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2 ENHANCEMENTS TO THE ESSI . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 ESSI DATA AND CONTROL SIGNALS . . . . . . . . . . . . . . . . 7-4

7.3.1 Serial Transmit Data (STD) Signal . . . . . . . . . . . . . . . . . . 7-4

7.3.2 Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . 7-4

7.3.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.3.4 Serial Control Signal (SC0). . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.3.5 Serial Control Signal (SC1). . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3.6 Serial Control Signal (SC2). . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4 ESSI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4.1 ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . 7-11

7.4.1.1 CRA Prescale Modulus Select PM[7:0] Bits 7Ð0 . . . . 7-11

7.4.1.2 CRA Reserved Bits 8Ð10 . . . . . . . . . . . . . . . . . . . . . . 7-11

7.4.1.3 CRA Prescaler Range (PSR) Bit 11 . . . . . . . . . . . . . . 7-11

7.4.1.4 CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12 7-12

7.4.1.5 CRA Reserved Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

7.4.1.6 CRA Alignment Control (ALC) Bit 18 . . . . . . . . . . . . . 7-13

7.4.1.7 CRA Word-length Control (WL[2:0]) Bits 21Ð19. . . . . 7-14

7.4.1.8 CRA Select SC1 (SSC1) Bit 22 . . . . . . . . . . . . . . . . . 7-14

7.4.1.9 CRA Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.4.2 ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . 7-15

7.4.2.1 CRB Serial Output Flags (OF0, OF1) Bits 0, 1. . . . . . 7-15

7.4.2.1.1 CRB Serial Output Flag 0 (OF0) Bit 0 . . . . . . . . . . 7-15

7.4.2.1.2 CRB Serial Output Flag 1 (OF1) Bit 1 . . . . . . . . . . 7-16

7.4.2.2 CRB Serial Control Direction 0 (SCD0) Bit 2 . . . . . . . 7-16

7.4.2.3 CRB Serial Control Direction 1 (SCD1) Bit 3 . . . . . . . 7-16

viii DSP56309UM/D MOTOROLA

7.4.2.4 CRB Serial Control Direction 2 (SCD2) Bit 4 . . . . . . . 7-16

7.4.2.5 CRB Clock Source Direction (SCKD) Bit 5 . . . . . . . . . 7-16

7.4.2.6 CRB Shift Direction (SHFD) Bit 6 . . . . . . . . . . . . . . . . 7-17

7.4.2.7 CRB Frame Sync Length FSL[1:0] Bits 7 and 8 . . . . . 7-17

7.4.2.8 CRB Frame Sync Relative Timing (FSR) Bit 9 . . . . . . 7-17

7.4.2.9 CRB Frame Sync Polarity (FSP) Bit 10. . . . . . . . . . . . 7-17

7.4.2.10 CRB Clock Polarity (CKP) Bit 11. . . . . . . . . . . . . . . . . 7-18

7.4.2.11 CRB Synchronous /Asynchronous (SYN) Bit 12. . . . . 7-18

7.4.2.12 CRB ESSI Mode Select (MOD) Bit 13 . . . . . . . . . . . . 7-20

7.4.2.13 Enabling, Disabling ESSI Data Transmission . . . . . . . 7-22

7.4.2.14 CRB ESSI Transmit 2 Enable (TE2) Bit 14. . . . . . . . . 7-22

7.4.2.15 CRB ESSI Transmit 1 Enable (TE1) Bit 15. . . . . . . . . 7-23

7.4.2.16 CRB ESSI Transmit 0 Enable (TE0) Bit 16. . . . . . . . . 7-24

7.4.2.17 CRB ESSI Receive Enable (RE) Bit 17. . . . . . . . . . . . 7-26

7.4.2.18 CRB ESSI Transmit Interrupt Enable (TIE) Bit 18. . . . 7-26

7.4.2.19 CRB ESSI Receive Interrupt Enable (RIE) Bit 19 . . . . 7-26

7.4.2.20 Transmit Last Slot Interrupt Enable (TLIE) Bit 20 . . . . 7-26

7.4.2.21 Receive Last Slot Interrupt Enable (RLIE) Bit 21 . . . . 7-27

7.4.2.22 Transmit Exception Interrupt Enable (TEIE) Bit 22 . . . 7-27

7.4.2.23 Receive Exception Interrupt Enable (REIE) Bit 23 . . . 7-27

7.4.3 ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . 7-27

7.4.3.1 SSISR Serial Input Flag 0 (IF0) Bit 0 . . . . . . . . . . . . . 7-28

7.4.3.2 SSISR Serial Input Flag 1 (IF1) Bit 1 . . . . . . . . . . . . . 7-28

7.4.3.3 SSISR Transmit Frame Sync Flag (TFS) Bit 2 . . . . . . 7-28

7.4.3.4 SSISR Receive Frame Sync Flag (RFS) Bit 3 . . . . . . 7-28

7.4.3.5 SSISR Transmitter Underrun Error Flag (TUE) Bit 4 . 7-29

7.4.3.6 SSISR Receiver Overrun Error Flag (ROE) Bit 5 . . . . 7-29

7.4.3.7 ESSI Transmit Data Register Empty (TDE) Bit 6 . . . . 7-29

7.4.3.8 ESSI Receive Data Register Full (RDF) Bit 7 . . . . . . . 7-30

7.4.4 ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . 7-33

7.4.5 ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . 7-33

7.4.6 ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . 7-33

7.4.7 ESSI Transmit Data Registers (TX0-2) . . . . . . . . . . . . . . 7-34

7.4.8 ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . 7-34

7.4.9 Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . 7-34

7.4.10 Receive Slot Mask Registers (RSMA, RSMB). . . . . . . . . 7-35

MOTOROLA DSP56309UM/D ix

7.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.1 ESSI After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.2 ESSI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.5.3 ESSI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37

7.5.4 Operating Modes: Normal, Network, and On-Demand . . 7-40

7.5.4.1 Normal/Network/On-Demand Mode Selection . . . . . . 7-40

7.5.4.2 Synchronous/Asynchronous Operating Modes . . . . . 7-40

7.5.4.3 Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . 7-41

7.5.4.3.1 Frame Sync Signal Format . . . . . . . . . . . . . . . . . . 7-41

7.5.4.3.2 Frame Sync Length for Multiple Devices . . . . . . . . 7-41

7.5.4.3.3 Word-Length Frame Sync and Data-Word Timing 7-41

7.5.4.3.4 Frame Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . 7-42

7.5.4.4 Byte Format (LSB/MSB) for the Transmitter . . . . . . . 7-42

7.5.5 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42

7.6 GPIO SIGNALS AND REGISTERS. . . . . . . . . . . . . . . . . . . 7-43

7.6.1 Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . 7-43

7.6.2 Port Direction Register (PRR). . . . . . . . . . . . . . . . . . . . . 7-44

7.6.3 Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . 7-45

SECTION 8 SERIAL COMMUNICATION INTERFACE (SCI) . . 8-1

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2 SCI I/O SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.1 Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.2 Transmit Data (TXD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.3 SCI Serial Clock (SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3 SCI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.3.1 SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.3.1.1 SCR Word Select (WDS[0:2]) Bits 0Ð2 . . . . . . . . . . . . 8-8

8.3.1.2 SCR SCI Shift Direction (SSFTD) Bit 3 . . . . . . . . . . . . 8-9

8.3.1.3 SCR Send Break (SBK) Bit 4 . . . . . . . . . . . . . . . . . . . . 8-9

8.3.1.4 SCR Wakeup Mode Select (WAKE) Bit 5 . . . . . . . . . . 8-9

8.3.1.5 SCR Receiver Wakeup Enable (RWU) Bit 6 . . . . . . . . 8-9

8.3.1.6 SCR Wired-OR Mode Select (WOMS) Bit 7. . . . . . . . 8-10

8.3.1.7 SCR Receiver Enable (RE) Bit 8 . . . . . . . . . . . . . . . . 8-10

8.3.1.8 SCR Transmitter Enable (TE) Bit 9 . . . . . . . . . . . . . . 8-10

8.3.1.9 SCR Idle Line Interrupt Enable (ILIE) Bit 10. . . . . . . . 8-11

x DSP56309UM/D MOTOROLA

8.3.1.10 SCR SCI Receive Interrupt Enable (RIE) Bit 11 . . . . . 8-11

8.3.1.11 SCR SCI Transmit Interrupt Enable (TIE) Bit 12. . . . . 8-12

8.3.1.12 SCR Timer Interrupt Enable (TMIE) Bit 13 . . . . . . . . . 8-12

8.3.1.13 SCR Timer Interrupt Rate (STIR) Bit 14 . . . . . . . . . . . 8-12

8.3.1.14 SCR SCI Clock Polarity (SCKP) Bit 15 . . . . . . . . . . . . 8-12

8.3.1.15 Receive with Exception Interrupt Enable (REIE) Bit 168-13

8.3.2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.3.2.1 SSR Transmitter Empty (TRNE) Bit 0 . . . . . . . . . . . . . 8-13

8.3.2.2 SSR Transmit Data Register Empty (TDRE) Bit 1 . . . 8-13

8.3.2.3 SSR Receive Data Register Full (RDRF) Bit 2 . . . . . . 8-14

8.3.2.4 SSR Idle Line Flag (IDLE) Bit 3. . . . . . . . . . . . . . . . . . 8-14

8.3.2.5 SSR Overrun Error Flag (OR) Bit 4. . . . . . . . . . . . . . . 8-14

8.3.2.6 SSR Parity Error (PE) Bit 5 . . . . . . . . . . . . . . . . . . . . . 8-14

8.3.2.7 SSR Framing Error Flag (FE) Bit 6 . . . . . . . . . . . . . . . 8-15

8.3.2.8 SSR Received Bit 8 (R8) Address Bit 7 . . . . . . . . . . . 8-15

8.3.3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . 8-15

8.3.3.1 SCCR Clock Divider (CD[11:0]) Bits 11Ð0 . . . . . . . . . 8-16

8.3.3.2 SCCR Clock Out Divider (COD) Bit 12 . . . . . . . . . . . . 8-16

8.3.3.3 SCCR SCI Clock Prescaler (SCP) Bit 13 . . . . . . . . . . 8-17

8.3.3.4 SCCR Receive Clock Mode Source (RCM) Bit 14 . . . 8-17

8.3.3.5 SCCR Transmit Clock Source Bit (TCM) Bit 15 . . . . . 8-18

8.3.4 SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.4.1 SCI Receive Registers (SRX) . . . . . . . . . . . . . . . . . . . 8-19

8.3.4.2 SCI Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.4 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

8.4.1 SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.4.2 SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.4.3 SCI Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . 8-25

8.4.4 Preamble, Break, and Data Transmission Priority. . . . . . 8-26

8.4.5 SCI Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26

8.5 GPIO SIGNALS AND REGISTERS . . . . . . . . . . . . . . . . . . . 8-27

8.5.1 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . 8-27

8.5.2 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . 8-27

8.5.3 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . 8-28

MOTOROLA DSP56309UM/D xi

SECTION 9 TRIPLE TIMER MODULE . . . . . . . . . . . . . . . . . . . . 9-1

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2 TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . 9-3

9.2.1 Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . 9-3

9.2.2 Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.3 TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . 9-5

9.3.1 Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.2 Timer Prescaler Load Register (TPLR). . . . . . . . . . . . . . . 9-7

9.3.2.1 TPLR Prescaler Preload Value (PL[20:0]) Bits 20-0 . . 9-7

9.3.2.2 TPLR Prescaler Source (PS[1:0]) Bits 22-21 . . . . . . . . 9-7

9.3.2.3 TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.3 Timer Prescaler Count Register (TPCR). . . . . . . . . . . . . . 9-8

9.3.3.1 TPCR Prescaler Counter Value (PC[20:0]) Bits 20-0. . 9-9

9.3.3.2 TPCR Reserved Bits 23-21 . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.4 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . 9-9

9.3.4.1 Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.4.2 Timer Overflow Interrupt Enable (TOIE) Bit 1 . . . . . . . 9-9

9.3.4.3 Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . 9-10

9.3.4.4 Timer Control (TC[3:0]) Bits 4-7 . . . . . . . . . . . . . . . . . 9-10

9.3.4.5 Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.4.6 Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . 9-13

9.3.4.7 Direction (DIR) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.8 Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.9 Data Output (DO) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.4.10 Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . 9-14

9.3.4.11 Timer Overflow Flag (TOF) Bit 20 . . . . . . . . . . . . . . . 9-14

9.3.4.12 Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . 9-15

9.3.4.13 TCSR Reserved Bits 3, 10, 14, 16-19, 22, 23 . . . . . . 9-15

9.3.5 Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.3.6 Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . 9-16

9.3.7 Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 9-16

9.4 TIMER OPERATIONAL MODES. . . . . . . . . . . . . . . . . . . . . 9-16

9.4.1 Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.4.1.1 Timer GPIO (Mode 0). . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.4.1.2 Timer Pulse (Mode 1). . . . . . . . . . . . . . . . . . . . . . . . . 9-18

9.4.1.3 Timer Toggle (Mode 2). . . . . . . . . . . . . . . . . . . . . . . . 9-19

xii DSP56309UM/D MOTOROLA

9.4.1.4 Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . 9-20

9.4.2 Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . 9-20

9.4.2.1 Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . 9-21

9.4.2.2 Measurement Input Width (Mode 4) . . . . . . . . . . . . . . 9-21

9.4.2.3 Measurement Input Period (Mode 5) . . . . . . . . . . . . . 9-22

9.4.2.4 Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . 9-23

9.4.3 Pulse Width Modulation (PWM, Mode 7). . . . . . . . . . . . . 9-24

9.4.4 Watchdog Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25

9.4.4.1 Watchdog Pulse (Mode 9). . . . . . . . . . . . . . . . . . . . . . 9-25

9.4.4.2 Watchdog Toggle (Mode 10). . . . . . . . . . . . . . . . . . . . 9-26

9.4.5 Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6 Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6.1 Timer Behavior during Wait. . . . . . . . . . . . . . . . . . . . . 9-27

9.4.6.2 Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . 9-27

9.4.7 DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27

SECTION 10 ON-CHIP EMULATION MODULE . . . . . . . . . . . . . 10-1

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.2 ONCE MODULE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.3 DEBUG EVENT (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4 ONCE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.4.1 OnCE Command Register (OCR) . . . . . . . . . . . . . . . . . . 10-5

10.4.1.1 Register Select (RS4ÐRS0) Bits 0Ð4 . . . . . . . . . . . . . 10-5

10.4.1.2 Exit Command (EX) Bit 5 . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1.3 GO Command (GO) Bit 6 . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4.1.4 Read/Write Command (R/W

) Bit 7 . . . . . . . . . . . . . . . 10-6

10.4.2 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.4.3 OnCE Status and Control Register (OSCR) . . . . . . . . . . 10-8

10.4.3.1 Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . 10-8

10.4.3.2 Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . 10-8

10.4.3.3 Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . 10-8

10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . 10-8

10.4.3.5 Trace Occurrence (TO) Bit 4. . . . . . . . . . . . . . . . . . . . 10-9

10.4.3.6 Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.4.3.7 Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . 10-9

10.4.3.8 Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

MOTOROLA DSP56309UM/D xiii

10.5 ONCE MEMORY BREAKPOINT LOGIC. . . . . . . . . . . . . . . 10-9

10.5.1 OnCE Memory Address Latch (OMAL). . . . . . . . . . . . . 10-11

10.5.2 OnCE Memory Limit Register 0 (OMLR0). . . . . . . . . . . 10-11

10.5.3 OnCE Memory Address Comparator 0 (OMAC0). . . . . 10-11

10.5.4 OnCE Memory Limit Register 1 (OMLR1). . . . . . . . . . . 10-11

10.5.5 OnCE Memory Address Comparator 1 (OMAC1). . . . . 10-11

10.5.6 OnCE Breakpoint Control Register (OBCR) . . . . . . . . . 10-12

10.5.6.1 Memory Breakpoint Select (MBS0ÐMBS1) . . . . . . . 10-12

10.5.6.2 Breakpoint 0 Read/Write Select (RW00ÐRW01) . . . 10-12

10.5.6.3 Breakpoint 0 Condition Code Select (CC00ÐCC01). 10-13

10.5.6.4 Breakpoint 1 Read/Write Select (RW10ÐRW11) . . . 10-13

10.5.6.5 Breakpoint 1 Condition Code Select (CC10ÐCC11). 10-14

10.5.6.6 Breakpoint 0 and 1 Event Select (BT0ÐBT1) . . . . . . 10-14

10.5.6.7 OnCE Memory Breakpoint Counter (OMBC) . . . . . . 10-14

10.5.6.8 Reserved Bits 12-15. . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.6 ONCE TRACE LOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

10.7 METHODS OF ENTERING DEBUG MODE . . . . . . . . . . . 10-16

10.7.1 External Debug Request During RESET Assertion . . . 10-16

10.7.2 External Debug Request During Normal Activity . . . . . 10-16

10.7.3 Executing the JTAG DEBUG_REQUEST Instruction . . 10-17

10.7.4 External Debug Request During Stop. . . . . . . . . . . . . . 10-17

10.7.5 External Debug Request During Wait . . . . . . . . . . . . . . 10-17

10.7.6 Software Request During Normal Activity. . . . . . . . . . . 10-18

10.7.7 Enabling Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18

10.7.8 Enabling Memory Breakpoints . . . . . . . . . . . . . . . . . . . 10-18

10.8 PIPELINE INFORMATION AND OGDB REGISTER. . . . . 10-18

10.8.1 OnCE PDB Register (OPDBR) . . . . . . . . . . . . . . . . . . . 10-19

10.8.2 OnCE PIL Register (OPILR) . . . . . . . . . . . . . . . . . . . . . 10-19

10.8.3 OnCE GDB Register (OGDBR). . . . . . . . . . . . . . . . . . . 10-20

10.9 DEBUGGING RESOURCES. . . . . . . . . . . . . . . . . . . . . . . 10-20

10.9.1 OnCE PAB Register for Fetch (OPABFR) . . . . . . . . . . 10-20

10.9.2 PAB Register for Decode (OPABDR) . . . . . . . . . . . . . . 10-20

10.9.3 OnCE PAB Register for Execute (OPABEX) . . . . . . . . 10-20

10.9.4 Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10.10 SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . 10-22

10.11 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . . 10-23

xiv DSP56309UM/D MOTOROLA

10.12 ONCE MODULE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . 10-23

10.12.1 Checking Whether the Chip Has Entered Debug Mode 10-24

10.12.2 Polling the JTAG Instruction Shift Register . . . . . . . . . . 10-24

10.12.3 Saving Pipeline Information . . . . . . . . . . . . . . . . . . . . . . 10-25

10.12.4 Reading the Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . 10-25

10.12.5 Displaying a Specified Register . . . . . . . . . . . . . . . . . . . 10-26

10.12.6 Displaying X Memory Area Starting at Address $xxxx . 10-26

10.12.7 Returning from Debug to Normal Mode (Same Program)10-28

10.12.8 Returning from Debug to Normal Mode (New Program) 10-28

10.13 JTAG PORT/ONCE MODULE INTERACTION . . . . . . . . . 10-29

SECTION 11 JTAG PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2 JTAG SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

11.2.1 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.2 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.3 Test Data Input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.4 Test Data Output (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.2.5 Test Reset (TRST

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.3 TAP CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

11.3.1 Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . 11-7

11.3.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

11.3.2.1 EXTEST (B[3:0] = 0000) . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.3.2.2 SAMPLE/PRELOAD (B[3:0] = 0001). . . . . . . . . . . . . . 11-9

11.3.2.3 IDCODE (B[3:0] = 0010) . . . . . . . . . . . . . . . . . . . . . . . 11-9

11.3.2.4 CLAMP (B[3:0] = 0011). . . . . . . . . . . . . . . . . . . . . . . 11-10

11.3.2.5 HI-Z (B[3:0] = 0100) . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

11.3.2.6 ENABLE_ONCE(B[3:0] = 0110) . . . . . . . . . . . . . . . . 11-11

11.3.2.7 DEBUG_REQUEST(B[3:0] = 0111) . . . . . . . . . . . . . 11-11

11.3.2.8 BYPASS (B[3:0] = 1111) . . . . . . . . . . . . . . . . . . . . . 11-11

11.4 DSP56300 RESTRICTIONS . . . . . . . . . . . . . . . . . . . . . . . 11-12

11.5 DSP56309 BOUNDARY SCAN REGISTER . . . . . . . . . . . 11-13

MOTOROLA DSP56309UM/D xv

APPENDIX A BOOTSTRAP PROGRAMS . . . . . . . . . . . . . . . . . . A-1

APPENDIX B EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1 I/O EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.2 HOST INTERFACE (HI08) EQUATES . . . . . . . . . . . . . . . . . B-3

B.3 SCI EQUATES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4

B.4 ESSI EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

B.5 EXCEPTION PROCESSING EQUATES . . . . . . . . . . . . . . . B-7

B.6 TIMER MODULE EQUATES . . . . . . . . . . . . . . . . . . . . . . . . B-9

B.7 DIRECT MEMORY ACCESS (DMA) EQUATES . . . . . . . . B-10

B.8 PHASE-LOCKED LOOP (PLL) EQUATES . . . . . . . . . . . . . B-12

B.9 BUS INTERFACE UNIT (BIU) EQUATES . . . . . . . . . . . . . B-13

B.10 INTERRUPT EQUATES . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

APPENDIX C DSP56309 BSDL LISTING . . . . . . . . . . . . . . . . . . . C-1

APPENDIX D PROGRAMMING REFERENCE . . . . . . . . . . . . . . . D-1

D.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.1 Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.2 Interrupt Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.3 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.1.4 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3

D.2 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . D-4

D.3 INTERRUPT ADDRESSES AND SOURCES . . . . . . . . . . . D-11

D.4 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . D-13

xvi DSP56309UM/D MOTOROLA

LIST OF FIGURES

Figure 1-1 DSP56309 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . 2-4

Figure 3-1 Default Settings (0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Figure 3-2 Instruction Cache Enabled (0, 0, 1). . . . . . . . . . . . . . . . . . . . . . 3-11

Figure 3-3 Switched Program RAM (0, 1, 0). . . . . . . . . . . . . . . . . . . . . . . . 3-12

Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1)3-13

Figure 3-5 16-bit Space with Default RAM (1, 0, 0) . . . . . . . . . . . . . . . . . . 3-14

Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1) . . . . . . . 3-15

Figure 3-7 16-bit Space with Switched Program RAM (1, 1, 0) . . . . . . . . . 3-16

Figure 3-8 16-bit Space, Switched Program RAM, Instruction Cache . . . . 3-17

Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . 4-13

Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . 4-13

Figure 4-3 DSP56309 Operating Mode Register (OMR) . . . . . . . . . . . . . . 4-17

Figure 4-4 PLL Control (PCTL) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Figure 4-5 Identification Register Configuration (Revision 0) . . . . . . . . . . . 4-19

Figure 4-6 Address Attribute Registers (AAR0ÐAAR3). . . . . . . . . . . . . . . . 4-20

Figure 6-1 HI08 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Figure 6-2 Host Control Register (HCR) (X:$FFFFC2). . . . . . . . . . . . . . . . . 6-9

Figure 6-3 Host Status Register (HSR) (X:$FFFFC3) . . . . . . . . . . . . . . . . 6-11

MOTOROLA DSP56309UM/D xvii

Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5). . . . . . . . . . 6-12

Figure 6-5 Self Chip Select Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12

Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . 6-13

Figure 6-7 Single Strobe Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

Figure 6-8 Dual Strobe Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . 6-17

Figure 6-10 Host Data Register (HDR) (X:$FFFFC9) . . . . . . . . . . . . . . . . . . 6-17

Figure 6-11 HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

Figure 6-12 Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

Figure 6-13 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . 6-25

Figure 6-14 Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26

Figure 6-15 Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Figure 6-16 HI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33

Figure 7-1 ESSI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

Figure 7-2 ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-3 ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-4 ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Figure 7-5 ESSI Transmit Slot Mask Register A (TSMA) . . . . . . . . . . . . . . 7-10

Figure 7-6 ESSI Transmit Slot Mask Register B (TSMB) . . . . . . . . . . . . . . 7-10

Figure 7-7 ESSI Receive Slot Mask Register A (RSMA). . . . . . . . . . . . . . . 7-10

Figure 7-8 ESSI Receive Slot Mask Register B (RSMB). . . . . . . . . . . . . . . 7-10

Figure 7-9 ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . 7-12

xviii DSP56309UM/D MOTOROLA

Figure 7-10 ESSI Frame Sync Generator Functional Block Diagram. . . . . . 7-13

Figure 7-11 CRB FSL0 and FSL1 Bit Operation (FSR = 0) . . . . . . . . . . . . . 7-19

Figure 7-12 CRB SYN Bit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20

Figure 7-13 CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

Figure 7-14 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . 7-22

Figure 7-15 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) 7-23

Figure 7-16 ESSI Data Path Programming Model (SHFD = 0). . . . . . . . . . . 7-31

Figure 7-17 ESSI Data Path Programming Model (SHFD = 1). . . . . . . . . . . 7-32

Figure 7-18 Port Control Register (PCR) (PCRC X:$FFFFBF). . . . . . . . . . . 7-44

Figure 7-19 Port Direction Register (PRR)(PRRC X:$FFFFBE). . . . . . . . . . 7-44

Figure 7-20 Port Data Register (PDR) (PDRC X:$FFFFBD) . . . . . . . . . . . . 7-45

Figure 8-1 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-2 SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-3 SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . 8-5

Figure 8-4 SCI Data Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Figure 8-5 16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

Figure 8-6 SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

Figure 8-7 SCI Programming Model Data Registers . . . . . . . . . . . . . . . . . 8-19

Figure 8-8 Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . 8-27

Figure 8-9 Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . 8-28

Figure 8-10 Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29

Figure 9-1 Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . 9-4

MOTOROLA DSP56309UM/D xix

Figure 9-2 Timer Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Figure 9-3 Timer Module ProgrammerÕs Model. . . . . . . . . . . . . . . . . . . . . . . 9-6

Figure 9-4 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . 9-7

Figure 9-5 Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . 9-8

Figure 9-6 Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

Figure 10-1 OnCE Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Figure 10-2 OnCE Module Multiprocessor Configuration . . . . . . . . . . . . . . . 10-4

Figure 10-3 OnCE Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Figure 10-4 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

Figure 10-5 OnCE Status and Control Register (OSCR). . . . . . . . . . . . . . . . 10-8

Figure 10-6 OnCE Memory Breakpoint Logic 0. . . . . . . . . . . . . . . . . . . . . . 10-10

Figure 10-7 OnCE Breakpoint Control Register (OBCR). . . . . . . . . . . . . . . 10-12

Figure 10-8 OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . 10-15

Figure 10-9 OnCE Pipeline Information and GDB Registers . . . . . . . . . . . 10-19

Figure 10-10 OnCE Trace Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22

Figure 11-1 TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Figure 11-2 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

Figure 11-3 JTAG Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Figure 11-4 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Figure 11-5 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11

Figure D-1 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-15

Figure D-2 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . .D-16

xx DSP56309UM/D MOTOROLA

Figure D-3 Interrupt Priority RegisterÐCore (IPRÐC). . . . . . . . . . . . . . . . . . D-17

Figure D-4 Interrupt Priority Register Ð Peripherals (IPRÐP). . . . . . . . . . . . D-18

Figure D-5 Phase-Locked Loop Control Register (PCTL) . . . . . . . . . . . . . . D-19

Figure D-6 Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-20

Figure D-7 Host Control and Host Status Registers . . . . . . . . . . . . . . . . . . D-21

Figure D-8 Host Base Address and Host Port Control Registers . . . . . . . . D-22

Figure D-9 Interrupt Control and Interrupt Status Registers . . . . . . . . . . . . D-23

Figure D-10 Interrupt Vector and Command Vector Registers . . . . . . . . . . . D-24

Figure D-11 Host Receive and Host Transmit Data Registers . . . . . . . . . . . D-25

Figure D-12 ESSI Control Register A (CRA). . . . . . . . . . . . . . . . . . . . . . . . . D-26

Figure D-13 ESSI Control Register B (CRB). . . . . . . . . . . . . . . . . . . . . . . . . D-27

Figure D-14 ESSI Status Register (SSISR). . . . . . . . . . . . . . . . . . . . . . . . . . D-28

Figure D-15 ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)D-29

Figure D-16 SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30

Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR). . . . . . . D-31

Figure D-18 SCI Receive and Transmit Data Registers (SRX, TRX) . . . . . . D-32

Figure D-19 Timer Prescaler Load/Count Register (TPLR, TPCR). . . . . . . . D-33

Figure D-20 Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . D-34

Figure D-21 Timer Load, Compare, Count Registers (TLR, TCPR, TCR) . . D-35

Figure D-22 Host Data Direction and Host Data Registers (HDDR, HDR) . . D-36

Figure D-23 Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . D-37

Figure D-24 Port D Registers (PCRD, PRRD, PDRD) . . . . . . . . . . . . . . . . . D-38

MOTOROLA DSP56309UM/D xxi

Figure D-25 Port E Registers (PCRE, PRRE, PDRE) . . . . . . . . . . . . . . . . . D-39

xxii DSP56309UM/D MOTOROLA

LIST OF TABLES

Table 1-1 High True/Low True Signal Conventions . . . . . . . . . . . . . . . . . . 1-5

Table 1-2 On Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Table 2-1 DSP56309 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3

Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-3 Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-4 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-5 Phase-Locked Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-6 External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-7 External Data Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-8 External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-9 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-10 Host Port Usage Considerations . . . . . . . . . . . . . . . . . . . . . . . 2-17

Table 2-11 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) . . . . . . . . . 2-24

Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) . . . . . . . . . 2-28

Table 2-14 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . 2-32

Table 2-15 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34

Table 2-16 OnCE/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Table 3-1 Memory Space Configuration Bit Settings for the DSP56309 . . . 3-5

MOTOROLA DSP56309UM/D xxiii

Table 3-2 RAM Configuration Bit Settings for the DSP56309 . . . . . . . . . . . 3-5

Table 3-3 Memory Space Configurations for the DSP56309 . . . . . . . . . . . . 3-7

Table 3-4 RAM Configurations for the DSP56309 . . . . . . . . . . . . . . . . . . . . 3-8

Table 3-5 Memory Locations for Program RAM and Instruction Cache. . . . 3-8

Table 3-6 Memory Locations for Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Table 4-1 DSP56309 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-3 Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Table 4-4 Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . . 4-14

Table 4-5 DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

Table 6-1 HI08 Signal Definitions for Various Operational Modes . . . . . . . . 6-6

Table 6-2 HI08 Data Strobe Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-3 HI08 Host Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Table 6-4 Host Command Interrupt Priority List . . . . . . . . . . . . . . . . . . . . . 6-10

Table 6-5 HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Table 6-6 DSP Side Registers after Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-19

Table 6-7 Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

Table 6-8 TREQ and RREQ modes (HDRQ = 0). . . . . . . . . . . . . . . . . . . . 6-23

Table 6-9 TREQ and RREQ modes (HDRQ = 1). . . . . . . . . . . . . . . . . . . . 6-23

Table 6-10 INIT Command Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

Table 6-11 HREQ and HDRQ Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28

Table 6-12 Host Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . 6-30

xxiv DSP56309UM/D MOTOROLA

Table 6-13 HI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34

Table 7-1 ESSI Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

Table 7-2 ESSI Word Length Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Table 7-3 FSL1 and FSL0 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

Table 7-4 Mode and Signal Definition Table . . . . . . . . . . . . . . . . . . . . . . 7-24

Table 7-5 Port Control Register and Port Direction Register Bits . . . . . . . 7-45

Table 8-1 Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

Table 8-2 TCM and RCM Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . 8-17

Table 8-3 SCI Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23

Table 8-4 Port Control Register and Port Direction Register Bits . . . . . . . 8-28

Table 9-1 Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

Table 9-2 Timer Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10

Table 9-3 Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

Table 10-1 EX Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-2 GO Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-3 R/W

Table 10-4 OnCE Register Select Encoding . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-5 Core Status Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

Table 10-6 Memory Breakpoint 0 and 1 Select Table . . . . . . . . . . . . . . . . 10-12

Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

Table 10-7 Breakpoint 0 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13

Table 10-8 Breakpoint 0 Condition Select Table . . . . . . . . . . . . . . . . . . . 10-13

Table 10-9 Breakpoint 1 Read/Write Select Table . . . . . . . . . . . . . . . . . . 10-13

MOTOROLA DSP56309UM/D xxv

Table 10-10 Breakpoint 1 Condition Select Table. . . . . . . . . . . . . . . . . . . . 10-14

Table 10-11 Breakpoint 0 and 1 Event Select Table . . . . . . . . . . . . . . . . . . 10-14

Table 10-12 TMS Sequencing for DEBUG_REQUEST . . . . . . . . . . . . . . . 10-29

Table 10-13 TMS Sequencing for ENABLE_ONCE . . . . . . . . . . . . . . . . . . 10-30

Table 10-14 TMS Sequencing for Reading Pipeline Registers . . . . . . . . . 10-31

Table 11-1 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Table 11-2 DSP56309 BSR Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . 11-13

Table D-1 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-4

Table D-2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-11

Table D-3 Interrupt Source Priorities within an IPL . . . . . . . . . . . . . . . . . .D-13

xxvi DSP56309UM/D MOTOROLA

SECTION 1

DSP56309 OVERVIEW

MOTOROLA DSP56309UM/D 1-1

DSP56309 Overview

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.4 DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.5 DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . 1-7

1.6 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . 1-8

1.7 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.8 DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . 1-14

1.9 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15

1.10 DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15

1-2 DSP56309UM/D MOTOROLA

DSP56309 Overview

Introduction

1.1 INTRODUCTION

This manual describes the DSP56309 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56309 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.

This manual is intended to be used with the

DSP56300 Family Manual (DSP56300FM/AD),

which describes the central processing unit (CPU), core programming models, and
instruction set details.

DSP56309 Technical Data (DSP56309/D)

provides electrical

specifications, timing, pinout, and packaging descriptions of the DSP56309.

You can obtain these documents, as well as MotorolaÕs DSP development tools, through
a local Motorola Semiconductor Sales Office or authorized distributor.

To receive the latest information about this DSP, access the Motorola DSP home page at
the address on the back cover of this document.

1.2 MANUAL ORGANIZATION

This manual contains the following sections and appendices:

Section 1ÑDSP56309 Overview

Ð Features list and block diagram

Ð Related documentation needed to use this chip

Ð The organization of this manual

Section 2ÑSignal/Connection Descriptions

Ð Signals on the DSP56309 pins and their functional groupings

Section 3ÑMemory Configuration

Ð DSP56309 memory spaces, RAM configuration, memory configuration bit

settings, memory configurations, and memory maps

Section 4ÑCore Configuration

Ð Registers for configuring the DSP56300 core to program the DSP56309, in

particular the interrupt vector locations and the operation of the interrupt
priority registers

Ð Operating modes and how they affect the processorÕs program and data

memories

MOTOROLA DSP56309UM/D 1-3

DSP56309 Overview

Manual Organization

Section 5ÑGeneral-Purpose I/O

Ð DSP56309 general-purpose input/output (GPIO) capability and the

programming model for the GPIO signals (operation, registers, and control)

Section 6ÑHost Interface (HI08)

Ð 8-bit host interface (HI08), including a quick reference to the HI08

programming model

Section 7ÑEnhanced Synchronous Serial Interface (ESSI)

Ð 24-bit ESSI, which provides two identical full duplex UART-style serial ports

for communications with devices such as codecs, DSPs, microprocessors, and
peripherals implementing the Motorola serial peripheral interface (SPI)

Section 8ÑSerial Communication Interface (SCI)

Ð 24-bit SCI, a full duplex serial port for serial communication to DSPs,

microcontrollers, or other peripherals (such as modems or other RS-232
devices)

Section 9ÑTriple Timer Module

Ð The three identical internal timers/event counter devices

Section 10ÑOn-Chip Emulation Module

Ð The On-Chip Emulation (OnCEª) module, which is accessed through the

JTAG port

Section 11ÑJTAG Port

Ð Specifics of the Joint Test Action Group (JTAG) port on the DSP56309

Appendix AÑBootstrap Programs

Ð Bootstrap code used for the DSP56309

Appendix BÑEquates

Ð Equates (I/O, HI08, SCI, ESSI, exception processing, timer, DMA, PLL, BIU,

and interrupts) for the DSP56309

Appendix CÑDSP56309 BSDL Listing

Ð BSDL listing for the DSP56309

Appendix DÑProgramming Reference

Ð Peripheral addresses, interrupt addresses, and interrupt priorities for the

DSP56309

Ð Programming sheets listing the contents of the major DSP56309 registers for

programmerÕs reference

1-4 DSP56309UM/D MOTOROLA

DSP56309 Overview

Manual Conventions

1.3 MANUAL CONVENTIONS

This manual uses the following conventions:

¥ Bits within registers are always listed from most significant bit (MSB) to least

significant bit (LSB).

¥ Bits within a register are indicated AA[n:m], n>m, when more than one bit is

involved in a description. For purposes of description, the bits are presented as if
they are contiguous within a register. However, this is not always the case. Refer
to the programming model diagrams or to the programmerÕs sheets to see the
exact location of bits within a register.

¥ When a bit is described as Òset,Ó its value is 1. When a bit is described as

Òcleared,Ó its value is 0.

¥ The word ÒassertÓ means that a high true (active high) signal is pulled high to

or that a low true (active low) signal is pulled low to ground. The word

V

CC

ÒdeassertÓ means that a high true signal is pulled low to ground or that a low true
signal is pulled high to V

Table 1-1 High True/Low True Signal Conventions

. See Table 1-1 .

CC

Signal/Symbol Logic State Signal State Voltage

PIN

1

True Asserted

Ground

PIN False Deasserted

PIN True Asserted V

2

3

V

CC

CC

PIN False Deasserted Ground

1. PIN is a generic term for any pin on the chip.

2. Ground is an acceptable low voltage level. See the
appropriate data sheet for the range of acceptable low
voltage levels (typically a TTL logic low).

3. V

is an acceptable high voltage level. See the

CC

appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).

¥ Pins or signals that are asserted low (made active when pulled to ground)

Ð In text, have an overbar. For example, RESET is asserted low.

Ð In code examples, have a tilde in front of their names. In Example 1-1 , line 3

refers to the SS0

signal (shown as ~SS0 ).

MOTOROLA DSP56309UM/D 1-5

DSP56309 Overview

DSP56309 Features

¥ Sets of signals are indicated by the first and last signals in the set, for instance

HA1ÐHA8.

¥ Code examples are displayed in a monospaced font, as shown in Example 1-1.

Example 1-1 Sample Code Listing

BFSET #$0007,X:PCC; Configure: line 1

; MISO0, MOSI0, SCK0 for SPI master line 2

; ~SS0 as PC3 for GPIO line 3

¥ Hex values are indicated with a dollar sign ($) preceding the hex value. For

example, $FFFFFF is the X memory address for the core interrupt priority register
(IPR-C).

¥ The word ÔresetÕ is used in four different contexts in this manual:

Ð the reset signal, written as RESET;

Ð the reset instruction, written as RESET;

Ð the reset operating state, written as Reset; and

Ð the reset function, written as reset.

1.4 DSP56309 FEATURES

The DSP56309 is a member of the DSP56300 family of programmable CMOS DSPs. The
DSP56309 uses the DSP56300 core, a high-performance engine with a single clock cycle
per instruction. The DSP56300 core provides up to twice the performance of Motorola's
popular DSP56000 core family, while retaining code compatibility.

The DSP56300 core family offers a new level of performance in speed and power
provided by its rich instruction set and low-power dissipation, enabling a new
generation of wireless, telecommunications, and multimedia products. The DSP56300
core is composed of the data arithmetic logic unit (Data ALU), address generation unit
(AGU), program controller (PC), instruction cache controller, bus interface unit, direct
memory access (DMA) controller, On-Chip Emulation (OnCE) module, and a PLL-based
clock oscillator. Significant architectural enhancements to the DSP56300 core family
include a barrel shifter, 24-bit addressing, an instruction cache, and DMA.

The DSP56300 core family members contain the DSP56300 core and additional modules.
The modules are chosen from a library of standard pre-designed elements, such as
memories and peripherals. New modules can be added to the library to meet customer

1-6 DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56309 Core Description

specifications. A standard interface between the DSP56300 core and the on-chip memory
and peripherals supports a wide variety of memory and peripheral configurations.

The DSP56309 targets telecommunications applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general
digital signal processing.

1.5 DSP56309 CORE DESCRIPTION

The DSP56300 Family Manual fully describes core features; this manual describes
pinout, memory, and peripheral features.

1.5.1 General Features

¥ 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0 -

3.6 V

¥ Object-code compatible with the DSP56000 core

¥ Highly parallel instruction set

1.5.2 Hardware Debugging Support

¥ On-Chip Emulation (OnCEÔ) module

¥ Joint Test Action Group (JTAG) test access port (TAP)

¥ Address trace mode reflects internal program RAM accesses at the external port

1.5.3 Reduced Power Dissipation

¥ Very low-power CMOS design

¥ Wait and stop low-power standby modes

¥ Fully-static logic, operation frequency down to 0 Hz (dc)

¥ Optimized cycle-by-cycle power management circuitry (instruction-dependent,

peripheral-dependent, and mode-dependent)

MOTOROLA DSP56309UM/D 1-7

DSP56309 Overview

DSP56300 Core Functional Blocks

1.6 DSP56300 CORE FUNCTIONAL BLOCKS

The DSP56300 core provides the following functional blocks:

¥ Data ALU

¥ AGU

¥ PCU

¥ PLL and Clock Oscillator

¥ JTAG TAP and OnCE module

¥ Memory

In addition, the DSP56309 provides a set of on-chip peripherals, described in

Section 1.10.

1.6.1 Data ALU

The Data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. The components of the Data ALU are as follows:

¥ Fully pipelined 24 ´ 24-bit parallel multiplier-accumulator (MAC)

¥ Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and

normalization; bit stream generation and parsing)

¥ Conditional ALU instructions

¥ 24-bit or 16-bit arithmetic support under software control

¥ Four 24-bit input general-purpose registers: X1, X0, Y1, and Y0

¥ Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two

general-purpose, 56-bit accumulators, A and B, accumulator shifters

¥ Two data bus shifter/limiter circuits

1.6.1.1 Data ALU Registers

The Data ALU registers can be read or written over the X data bus (XDB) and the Y data
bus (YDB) as 16- or 32-bit operands. The source operands for the Data ALU, which can
be 16, 32, or 40 bits, always originate from Data ALU registers. The results of all
Data ALU operations are stored in an accumulator.

1-8 DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56300 Core Functional Blocks

All the Data ALU operations are performed in two clock cycles in pipeline fashion so
that a new instruction can be initiated in every clock, yielding an effective execution rate
of one instruction per clock cycle. The destination of every arithmetic operation can be
used as a source operand for the immediately following operation without penalty.

1.6.1.2 Multiplier-Accumulator (MAC)

The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit
accepts as many as three input operands and outputs one 56-bit result of the following
form, Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).

The multiplier executes 24-bit ´ 24-bit, parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is
right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit
result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into
the MSP. Rounding is performed if specified.

1.6.2 Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary
to address data operands in memory and contains the registers that generate the
addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around
modulo, and reverse-carry. The AGU operates in parallel with other chip resources to
minimize address-generation overhead.

The AGU is divided into two halves, each with its own address arithmetic logic unit
(Address ALU). Each Address ALU has four sets of register triplets, and each register
triplet is composed of an address register, an offset register, and a modifier register. The
two Address ALUs are identical. Each contains a 16-bit full adder (called an offset
adder).

A second full adder (called a modulo adder) adds the summed result of the first full
adder to a modulo value that is stored in its respective modifier register. A third full
adder (called a reverse-carry adder) is also provided.

The offset adder and the reverse-carry adder are in parallel and share common inputs.
The only difference between them is that they carry propagates in opposite directions.
Test logic determines which of the three summed results of the full adders is output.

Each Address ALU can update one address register from its respective address register
file during one instruction cycle. The contents of the associated modifier register

MOTOROLA DSP56309UM/D 1-9

DSP56309 Overview

DSP56300 Core Functional Blocks

specifies the type of arithmetic to be used in the address register update calculation. The
modifier value is decoded in the Address ALU.

1.6.3 Program Control Unit (PCU)

The PCU performs instruction prefetch, instruction decoding, hardware DO loop
control, and exception processing. The PCU implements a seven-stage pipeline and
controls the different processing states of the DSP56300 core. The PCU consists of three
hardware blocks:

¥ Program decode controller (PDC)

¥ Program address generator (PAG)

¥ Program interrupt controller

The PDC decodes the 24-bit instruction loaded into the instruction latch and generates
all signals necessary for pipeline control. The PAG contains all the hardware needed for
program address generation, system stack, and loop control. The PIC arbitrates among
all interrupt requests (internal interrupts, as well as the five external requests IRQA

, IRQC, IRQD, and NMI) and generates the appropriate interrupt vector address.

IRQB

,

PCU features include the following:

¥ Position Independent Code (PIC) support

¥ Addressing modes optimized for DSP applications (including immediate offsets)

¥ On-chip instruction cache controller

¥ On-chip memory-expandable hardware stack

¥ Nested hardware DO loops

¥ Fast auto-return interrupts

The PCU implements its functions using the following registers:

¥ PCÑprogram counter register

¥ SRÑstatus register

¥ LAÑloop address register

¥ LCÑloop counter register

¥ VBAÑvector base address register

¥ SZÑsize register

1-10 DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56300 Core Functional Blocks

¥ SPÑstack pointer

¥ OMRÑoperating mode register

¥ SCÑstack counter register

The PCU also includes a hardware system stack (SS).

1.6.4 PLL and Clock Oscillator

The clock generator in the DSP56300 core is composed of two main blocks: the PLL,
which performs clock input division, frequency multiplication, and skew elimination;
and the clock generator (CLKGEN), which performs low-power division and clock pulse
generation.

¥ Allows change of low-power divide factor (DF) without loss of lock

¥ Output clock with skew elimination

The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:

¥ A lower-frequency clock input reduces the overall electromagnetic interference

generated by a system.

¥ The ability to oscillate at different frequencies reduces costs by eliminating the

need to add additional oscillators to a system.

1.6.5 JTAG TAP and OnCE Module

The DSP56300 core provides a dedicated user-accessible Test Access Port (TAP) that is
fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture. Problems associated with testing high density circuit boards have led to
development of this standard under the sponsorship of the Test Technology Committee
of IEEE and the Joint Test Action Group (JTAG). The DSP56300 core implementation
supports circuit-board test strategies based on this standard.

The test logic includes a TAP consisting of four dedicated signals, a 16-state controller,
and three test data registers. A boundary scan register links all device signals into a
single shift register. The test logic, implemented utilizing static logic design, is
independent of the device system logic. More information on the JTAG port is provided
in Section 11ÑJTAG Port

.

MOTOROLA DSP56309UM/D 1-11

DSP56309 Overview

DSP56300 Core Functional Blocks

The OnCE module provides a means of interacting with the DSP56300 core and its
peripherals non-intrusively so that a user can examine registers, memory, or on-chip
peripherals. This facilitates hardware and software development on the DSP56300 core
processor. OnCE module functions are provided through the JTAG TAP signals. More
information about the OnCE module is provided in Section 10ÑOn-Chip Emulation

Module

.

1.6.6 On-Chip Memory

The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into
X data memory and Y data memory in order to work with the two Address ALUs and to
feed two operands simultaneously to the Data ALU. Memory space includes internal
RAM and ROM and can be expanded off-chip under software control. More information
about the internal memory is provided in Section 3ÑMemory Configuration.

Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable,
as indicated in Table 1-2.

Table 1-2 On Chip Memory

Instruction

Cache

disabled disabled 20K ´ 24-bit 0 7K ´ 24-bit 7K ´ 24-bit

enabled disabled 19K´ 24-bit 1K ´ 24-bit 7K ´ 24-bit 7K ´ 24-bit

disabled enabled 24K ´ 24-bit 0 5K ´ 24-bit 5K ´ 24-bit

enabled enabled 23K ´ 24-bit 1K ´ 24-bit 5K ´ 24-bit 5K ´ 24-bit

Switch

Mode

Program RAM

Size

Instruction
Cache Size

X Data RAM

Size

Y Data RAM

Size

There is an on-chip 192 x 24-bit bootstrap ROM.

1.6.7 Off-Chip Memory Expansion

Memory can be expanded off-chip to do the following:

¥ Data memory expansion to two 256K ´ 24-bit word memory spaces (or up to two

M ´ 24-bit word memory spaces by using the address attribute AA0ÐAA3 signals)

4

¥ Program memory expansion to one 256K ´ 24-bit words memory space (or up to

4 M ´ 24-bit word memory space by using the address attribute AA0ÐAA3 signals)

one

Additional features of off-chip memory include the following:

1-12 DSP56309UM/D MOTOROLA

DSP56309 Overview

Internal Buses

¥ External memory expansion port

¥ Simultaneous glueless interface to static random access memory (SRAM) and

dynamic random access memory (DRAM)

¥ Supports interleaved, non-interfering access to both types of memory without

losing

in-page DRAM access, including DMA-driven access

1.7 INTERNAL BUSES

The following buses provide data exchange between the functional blocks of the core:

¥ Peripheral I/O expansion bus (PIO_EB) to peripherals

¥ Program memory expansion bus (PM_EB) to Program RAM

¥ X memory expansion bus (XM_EB) to X memory

¥ Y memory expansion bus (YM_EB) to Y memory

¥ Global data bus (GDB) between PCU and other core structures

¥ Program data bus (PDB) for carrying program data throughout the core

¥ X memory data bus (XDB) for carrying X data throughout the core

¥ Y memory data bus (YDB) for carrying Y data throughout the core

¥ Program address bus (PAB) for carrying program memory addresses throughout

the core

¥ X memory address bus (XAB) for carrying X memory addresses throughout the

core

¥ Y memory address bus (YAB) for carrying Y memory addresses throughout the

core

All internal buses on the DSP56300 family members are 16-bit buses except the PDB,
which is a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56309.

MOTOROLA DSP56309UM/D 1-13

DSP56309 Overview

DSP56309 Block Diagram

1.8 DSP56309 BLOCK DIAGRAM

616

6

3

Memory Expansion Area

EXTAL

XTAL

RESET

PINIT/NMI

Triple

Timer

Address

Generation

Unit

Six Channel

DMA Unit

Boot-

strap

ROM

Internal

Data

Bus

Switch

Clock

Generator

PLL

2

Host

Interface

HI08

Program
Interrupt

Controller

ESSI

Interface

Peripheral

Expansion Area

PIO_EB

MODD/IRQA
MODC/IRQB
MODB/IRQC
MODA/IRQD

Interface

Program

Decode

Controller

SCI

Program

RAM

DSP56300

DDB

YDB

XDB

PDB

GDB

Program

Address

Generator

X Data

RAM

PM_EB

YA B
XAB
PA B

DAB

XM_EB

24-Bit

Core

24 ´ 24 + 56 ® 56-bit MAC

Data ALU

Two 56-bit Accumulators

56-bit Barrel Shifter

Y Data

RAM

YM_EB

External

Address

Bus

Switch

External

Bus

Interface

&

I - Cache

Control

External

Data Bus

Switch

Powe r
Mgmt

JTAG

OnCEª

18

ADDRESS

13

CONTROL

24

DATA

6

AA0456

Figure 1-1 DSP56309 Block Diagram

Note: See Section 1.6.6 On-Chip Memory on page 1-12 for details on memory size.

1-14 DSP56309UM/D MOTOROLA

DSP56309 Overview

Direct Memory Access (DMA)

1.9 DIRECT MEMORY ACCESS (DMA)

The DMA block has the following features:

¥ Six DMA channels supporting internal and external accesses

¥ One-, two-, and three-dimensional transfers (including circular buffering)

¥ End-of-block-transfer interrupts

¥ Triggering from interrupt lines, all peripherals, and DMA channels

1.10 DSP56309 ARCHITECTURE OVERVIEW

The DSP56309 performs a wide variety of fixed-point digital signal processing functions.
In addition to the core features previously discussed, the DSP56309 provides the
following peripherals:

¥ Enhanced DSP56000-like 8-bit parallel host interface (HI08) supports a variety of

buses (e.g., industry standard architecture) and provides glueless connection to a
number of industry standard microcomputers, microprocessors, and DSPs

¥ Two enhanced synchronous serial interfaces (ESSI0 and ESSI1), each with one

receiver and three transmitters (allows six-channel home theater)

¥ Serial communications interface (SCI) with baud rate generator

¥ Triple timer module

¥ Up to 34 programmable general purpose input/output (GPIO) pins, depending

on which peripherals are enabled

1.10.1 GPIO Functionality

The GPIO port consists of as many as thirty-four programmable signals, all of which are
also used by the peripherals (HI08, ESSI, SCI, and timer). There are no dedicated GPIO
signals. Peripheral pins are configured as GPIO inputs after any reset. (Data in the port
data register is not affected by a reset.) The GPIO functionality for each peripheral is
controlled by three memory-mapped registers per peripheral. The techniques for
register programming for all GPIO functionality is very similar between these interfaces.

MOTOROLA DSP56309UM/D 1-15

DSP56309 Overview

DSP56309 Architecture Overview

1.10.2 Host Interface (HI08)

The HI08 is a byte-wide, full-duplex, double-buffered, parallel port that can connect
directly to the data bus of a host processor. The HI08 supports a variety of buses and
connects to a number of industry-standard DSPs, microcomputers, and microprocessors
without requiring additional logic.

The DSP core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in data memory space. The DSP can use the HI08 as a memory-mapped
peripheral, using either standard polled or interrupt programming techniques. Separate
transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Memory mapping allows DSP core
communication with the HI08 registers using standard instructions and addressing
modes.

1.10.3 Enhanced Synchronous Serial Interface (ESSI)

On the DSP56309 are two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement
the Motorola SPI. The ESSI consists of independent transmitter and receiver sections and
a common ESSI clock generator.

The capabilities of the ESSI include the following:

¥ Independent (asynchronous) or shared (synchronous) transmit and receive

sections with separate or shared internal/external clocks and frame syncs

¥ Normal mode operation using frame sync

¥ Network mode operation with as many as 32 time slots

¥ Programmable word length (8, 12, or 16 bits)

¥ Program options for frame synchronization and clock generation

¥ One receiver and three transmitters per ESSI allows six-channel home theater

1.10.4 Serial Communications Interface (SCI)

The DSP56309Õs SCI provides a full-duplex port for serial communication with other
DSPs, microprocessors, or peripherals such as modems. The SCI interfaces without

1-16 DSP56309UM/D MOTOROLA

DSP56309 Overview

DSP56309 Architecture Overview

additional logic to peripherals that use TTL-level signals. With a small amount of
additional logic, the SCI can connect to peripheral interfaces that have non-TTL level
signals, such as the RS-232C, RS-422, etc.

This interface uses three dedicated signals: transmit data (TXD), receive data (RXD), and
SCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and
protocols, as well as high-speed synchronous data transmission (up to 8.25 Mbps for a
66 MHz clock). The asynchronous protocols supported by the SCI include a multidrop
mode for master/slave operation with wakeup on idle line and wakeup on address bit
capability. This mode allows the DSP56309 to share a single serial line efficiently with
other peripherals.

The SCI consists of separate transmit and receive sections that can operate
asynchronously with respect to each other. A programmable baud-rate generator
provides the transmit and receive clocks. An enable vector and an interrupt vector have
been included so that the baud-rate generator can function as a general purpose timer
when it is not being used by the SCI or when the interrupt timing is the same as that
used by the SCI.

1.10.5 Timer Module

The triple timer module is composed of a common 21-bit prescaler and three
independent and identical general-purpose 24-bit timer/event counters, each with its
own memory-mapped register set.

Each timer has a single signal that can function as a GPIO signal or as a timer signal.
Each timer can use internal or external clocking and can interrupt the DSP after a
specified number of events (clocks) or can signal an external device after counting
internal events. Each timer connects to the external world through one bidirectional
signal. When this signal is configured as an input, the timer can function as an external
event counter or measures external pulse width/signal period. When the signal is used
as an output, the timer can function as either a timer, a watchdog, or a Pulse Width
Modulator (PWM).

MOTOROLA DSP56309UM/D 1-17

DSP56309 Overview

DSP56309 Architecture Overview

1-18 DSP56309UM/D MOTOROLA

SECTION 2

SIGNAL/CONNECTION DESCRIPTIONS

MOTOROLA DSP56309UM/D 2-1

Signal/Connection Descriptions

2.1 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5 PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9

2.7 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14

2.8 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24

2.10 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32

2.11 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33

2.12 ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

2-2 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Signal Groupings

2.1 SIGNAL GROUPINGS

The DSP56309 input and output signals are organized into functional groups, as shown
in Table 2-1 and as illustrated in Figure 2-1.

The DSP56309 is operated from a 3 V supply.

Table 2-1 DSP56309 Functional Signal Groupings

Power (V

Functional Group

)20Table 2-2

CC

Number of

Signals

Detailed

Description

Ground (GND) 19 Table 2-3

Clock 2 Table 2-4

PLL 3 Table 2-5

Address Bus

Data Bus

Bus Control

Port A

1

18 Table 2-6

24 Table 2-7

13 Table 2-8

Interrupt and Mode Control 5 Table 2-9

D

2

16 Table 2-11

12 Table 2-12

3

and

Host Interface (HI08)

Enhanced Synchronous Serial Interface
(ESSI)

Port B

Ports C and

Table 2-13

Serial Communication Interface (SCI)

Port E

4

3 Table 2-14

Timer 3 Table 2-15

OnCE/JTAG Port 6 Table 2-16

Note: 1. Port A signals define the external memory interface port, including the external

address bus, data bus, and control signals.

2. Port B signals are the HI08 port signals multiplexed with the GPIO signals.

3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.

4. Port E signals are the SCI port signals multiplexed with the GPIO signals.

Figure 2-1 is a diagram of DSP56309 signals by functional group.

MOTOROLA DSP56309UM/D 2-3

Signal/Connection Descriptions

)

Signal Groupings

PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer

PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer

During
Reset

PINIT

EXTERNAL MEMORY INTERFACE

V

CCP

V

CCQL

V

CCQH

V

CCA

V

CCD

V

CCC

V

CCH

V

CCS

GND

GND

P1

GND

GND
GND
GND
GND
GND

EXTAL

XTAL

CLKOUT

PCAP

After

Reset

NMI

A0ÐA17

D0ÐD23

AA0ÐAA3/

RAS0ÐRAS3

RD

WR

TA
BR
BG
BB

CAS
BCLK
BCLK

4
3
3
4
2

2

P

4

Q

4

A

4

D

2

C

H

2

S

18

24

4

DSP56309

Power Inputs

Grounds

Clock

PLL

Port A

fs

Port B

Port C

Port D

Port E

OnCE/JTAG

During Reset

MODA
MODB
MODC
MODD
RESET

Non-Multiplexed
Bus

8

H0ÐH7
HA0
HA1
HA2
HCS/HCS

Single DS

HRW
HDS/HDS

Single HR

HREQ/HREQ
HACK/HACK

Host Interface (H108)1

After Reset

IRQA
IRQB
IRQC
IRQD
RESET

Multiplexed
Bus

HAD0ÐHAD7
HAS/HAS
HA8
HA9
HA10

Double DS

HRD/HRD
HWR/HWR

Double HR

HTRQ/HTRQ
HRRQ/HRRQ

Port B
GPIO

PB0ÐPB7
PB8
PB9
PB10
PB13

PB11
PB12

PB14
PB15

Enhanced Synchronous Serial Interface (ESSI0)

3

SC00ÐSC02
SCK0
SRD0
STD0

Enhanced Synchronous Serial Interface (ESSI1

3

SC10ÐSC12
SCK1
SRD1
STD1

Serial Communications Interface (SCI)

Port C GPIO

PC0ÐPC2
PC3
PC4
PC5

Port D GPIO

PD0ÐPD2
PD3
PD4
PD5

2

Port E GPIO

RXD

TXD
SCLK

Timers

TIO0
TIO1
TIO2

3

PE0

PE1
PE2

GPIO

TIO0
TIO1
TIO2

TCK
TDI
TDO
TMS
TRST
DE

Notes: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or

double Host Request (HR) configurations. Since each of these modes is configured independently, any combination
of these modes is possible. These HI08 signals can also be configured alternately as GPIO signals (PB0ÐPB15).
Signals with dual designations (e.g., HAS/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0ÐPC5), Port D GPIO signals
(PD0ÐPD5), and Port E GPIO signals (PE0ÐPE2), respectively.

3. TIO0ÐTIO2 can be configured as GPIO signals.

AA0601

Figure 2-1 Signals Identified by Functional Group

2-4 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

2.2 POWER

Power input descriptions for the DSP56309 are listed in Table 2-2.

Table 2-2 Power Inputs

Power Name Description

Power

V

CCP

PLL PowerÑV
The voltage should be well regulated, and the input should be provided

with an extremely low impedance path to the VCC power rail. V
should be bypassed to GNDP by a stabilizing capacitor located as close
as possible to the chip package. There is one V

V

(4) Quiet Core (Low) PowerÑV

CCQL

processing logic. This input must be isolated externally from all other
chip power inputs. The user must provide adequate external decoupling
capacitors. There are four V

V

(3) Quiet External (High) PowerÑV

CCQH

lines. This input must be tied externally to all other chip power inputs,

except V

CCQL

capacitors. There are three V

(3) Address Bus PowerÑV

V

CCA

address bus I/O drivers. This input must be tied externally to all other
chip power inputs except V

external decoupling capacitors. There are three V

(4) Data Bus PowerÑV

V

CCD

I/O drivers. This input must be tied externally to all other chip power
inputs. The user must provide adequate external decoupling capacitors.
There are four V

is power dedicated for phase-locked loop (PLL) use.

CCP

CCP

input.

CCP

is an isolated power for the core

CCQL

inputs.

CCQL

is a quiet power source for I/O

CCQH

. The user must provide adequate external decoupling

inputs.

CCQH

is an isolated power for sections of the

CCA

. The user must provide adequate

CCQL

inputs.

CCA

is an isolated power for sections of the data bus

CCD

inputs.

CCD

(2) Bus Control PowerÑV

V

CCC

is an isolated power for the bus control I/O

CCC

drivers. This input must be tied externally to all other chip power inputs

V

CCH

except V

capacitors. There are two V

Host PowerÑV

. The user must provide adequate external decoupling

CCQL

inputs.

CCC

is an isolated power for the HI08 I/O drivers. This

CCH

input must be tied externally to all other chip power inputs except

V

There is one V

. The user must provide adequate external decoupling capacitors.

CCQL

input.

CCH

MOTOROLA DSP56309UM/D 2-5

Signal/Connection Descriptions

Ground

Table 2-2 Power Inputs (Continued)

Power Name Description

V

(2) ESSI, SCI, and Timer PowerÑV

CCS

SCI, and timer I/O drivers. This input must be tied externally to all
other chip power inputs except V

external decoupling capacitors. There are two V

is an isolated power for the ESSI,

CCS

. The user must provide adequate

CCQL

inputs.

CCS

Note: These designations are package-dependent. Some packages connect all V

each other internally. On those packages, all power input, except V
of connections indicated in this table are minimum values; the total V
package-dependent.

CCP

2.3 GROUND

Ground descriptions for the DSP56309 are listed in Table 2-3.

Table 2-3 Grounds

Ground Name Description

GND

GND

P

P1

PLL GroundÑGNDP is a ground dedicated for PLL use. The connection
should be provided with an extremely low-impedance path to ground.

V

should be bypassed to GNDP by a 0.47 mF capacitor located as

CCP

close as possible to the chip package. There is one GND

PLL Ground 1ÑGNDP1 is a ground dedicated for PLL use. The
connection should be provided with an extremely low-impedance path

to ground. There is one GND

connection.

P1

inputs except V

CC

, are labeled VCC. The number

connections are

CC

connection.

P

CCP

to

GND

(4) Quiet GroundÑGNDQ is an isolated ground for the internal processing

Q

logic. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling

GND

capacitors. There are four GND

(4) Address Bus GroundÑGNDA is an isolated ground for sections of the

A

connections.

Q

address bus I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GND

connections.

A

2-6 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Clock

Table 2-3 Grounds (Continued)

Ground Name Description

GNDD (4) Data Bus GroundÑGNDD is an isolated ground for sections of the data

bus I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors. There are four GND

connections.

D

GND

(2) Bus Control GroundÑGNDC is an isolated ground for the bus control

C

I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external

GND

decoupling capacitors. There are two GND

H

Host GroundÑGNDH is an isolated ground for the HI08 I/O drivers.

connections.

C

This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling

GND

capacitors. There is one GND

(2) ESSI, SCI, and Timer GroundÑGNDS is an isolated ground for the

S

connection.

H

ESSI, SCI, and timer I/O drivers. This connection must be tied externally
to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are two GND

Note: These designations are package-dependent. Some packages connect all GND inputs, except GNDP

and GND
GND
total GND connections are package-dependent.

, to each other internally. On those packages, all ground connections, except GNDP and

P1

, are labeled GND. The number of connections indicated in this table are minimum values; the

P1

connections.

S

2.4 CLOCK

Clock Signal descriptions for the DSP56309 are listed in Table 2-4.

Table 2-4 Clock Signals

Signal

Name

Type

EXTAL Input Input External Clock/Crystal InputÑEXTAL interfaces the

State

During

Reset

Signal Description

internal crystal oscillator input to an external crystal
or an external clock.

MOTOROLA DSP56309UM/D 2-7

Signal/Connection Descriptions

Phase-Locked Loop (PLL)

Table 2-4 Clock Signals (Continued)

Signal

Name

XTAL Output Chip-driven Crystal OutputÑXTAL connects the internal crystal

Type

State

During

Reset

Signal Description

oscillator output to an external crystal. If an external
clock is used, leave XTAL unconnected.

2.5 PHASE-LOCKED LOOP (PLL)

Phase-locked loop signal descriptions are listed in Table 2-5.

Table 2-5 Phase-Locked Loop Signals

Signal

Name

PCAP Input Input PLL CapacitorÑPCAP is an input connecting an

Type

State During

Reset

Signal Description

off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal
to V

CCP

.

If the PLL is not used, PCAP can be tied to VCC,
tied to GND, or left floating.

CLKOUT Output Chip-driven Clock OutputÑCLKOUT provides an output

clock synchronized to the internal core clock
phase.

If the PLL is enabled and both the multiplication
and division factors equal one, then CLKOUT is
also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is
half the frequency of EXTAL.

2-8 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 2-5 Phase-Locked Loop Signals (Continued)

Signal

Name

PINIT/
NMI

Type

Input Input PLL Initial/Non-Maskable InterruptÑDuring

State During

Reset

Signal Description

assertion of RESET
written into the PLL Enable (PEN) bit of the PLL
control register, determining whether the PLL is
enabled or disabled. After RESET
during normal instruction processing, the
PINIT/NMI
negative-edge-triggered Non-Maskable Interrupt
(NMI) request internally synchronized to
CLKOUT.

Schmitt-trigger input is a

, the value of PINIT/NMI is

deassertion and

2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A)

When the DSP56309 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A0ÐA17, D0ÐD23,
AA0/RAS0

ÐAA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.

2.6.1 External Address Bus

External address bus signals for the DSP56309 are listed in Table 2-6.

Table 2-6 External Address Bus Signals

Signal

Name

A0ÐA17 Output Tri-stated Address BusÑWhen the DSP is the bus master,

Type

State

During

Reset

Signal Description

A0ÐA17 are active-high outputs that specify the
address for external program and data memory
accesses. Otherwise, the signals are tri-stated.
To minimize power dissipation, A0ÐA17 do not
change state when external memory spaces are
not being accessed.

MOTOROLA DSP56309UM/D 2-9

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

2.6.2 External Data Bus

External data bus signals for the DSP56309 are listed in Table 2-7.

Table 2-7 External Data Bus Signals

Signal

Name

D0ÐD23 Input/

Type

Output

State

During

Reset

weakly
driven by
bus keeper

Signal Description

Data BusÑWhen the DSP is the bus master,

D0ÐD23 are active-high, bidirectional
input/outputs that provide the bidirectional
data bus for external program and data
memory accesses. Otherwise, D0ÐD23 are
weakly driven by the bus keeper.

2.6.3 External Bus Control

External bus control signal descriptions for the DSP56309 are listed in Table 2-8.

Table 2-8 External Bus Control Signals

Signal

Name

Type

State

During

Reset

Signal Description

AA0Ð
AA3/
RAS0
RAS3

RD

WR

Ð

Output Tri-stated Address Attribute or Row Address StrobeÑWhen

defined as AA, these signals can be used as chip
selects or additional address lines. When defined as
RAS

, these signals can be used as RAS for DRAM
interface. These signals are tri-statable outputs with
programmable polarity.

Output Tri-stated Read EnableÑWhen the DSP is the bus master, RD

is an active-low output that is asserted to read
external memory on the data bus (D0ÐD23).
Otherwise, RD

Output Tri-stated Write EnableÑWhen the DSP is the bus master, WR

is an active-low output that is asserted to write
external memory on the data bus (D0ÐD23).
Otherwise, the signals are tri-stated.

is tri-stated.

2-10 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 2-8 External Bus Control Signals (Continued)

Signal

Name

TA Input Ignored

Type

State

During

Reset

Input

Signal Description

Transfer AcknowledgeÑIf the DSP56309 is the bus

master and there is no external bus activity, or the
DSP56309 is not the bus master, the TA
ignored. The TA
acknowledge (DTACK) function that can extend an
external bus cycle indefinitely. Any number of wait
states (1, 2,..., infinity) can be added to the wait states
inserted by the BCR by keeping TA
typical operation, TA
bus cycle, is asserted to enable completion of the bus
cycle, and is deasserted before the next bus cycle.
The current bus cycle completes one clock period
after TA
number of wait states is determined by the TA
or by the BCR, whichever is longer. The BCR can be
used to set the minimum number of wait states in
external bus cycles.

In order to use the TA
programmed to at least one wait state. A zero wait
state access cannot be extended by TA
otherwise, improper operation can result. TA
operate synchronously or asynchronously
depending on the setting of the TAS bit in the OMR.
You must not use TA
DRAM type accesses; otherwise, improper operation
can result.

is asserted synchronous to CLKOUT. The

input is a data transfer

input is

deasserted. In

is deasserted at the start of a

input

functionality, the BCR must be

deassertion;

can

functionality while performing

MOTOROLA DSP56309UM/D 2-11

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 2-8 External Bus Control Signals (Continued)

Signal

Name

BR Output Output

Type

State

During

Reset

(deasserted)

Signal Description

Bus RequestÑBR is an active-low output, never

tri-stated. BR
mastership. BR
longer needs the bus. BR
deasserted independent of whether the DSP56309 is
a bus master or a bus slave. Bus ÒparkingÓ allows BR
to be deasserted even though the DSP56309 is the
bus master; see the description of bus ÒparkingÓ in
the BB
(BRH) bit in the BCR allows BR
software control even though the DSP does not need
the bus. BR
arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR
only affected by DSP requests for the external bus,
never for the internal bus. During hardware reset,
BR
bus slave state.

signal description. The bus request hole

is deasserted and the arbitration is reset to the

is asserted when the DSP requests bus

is deasserted when the DSP no

can be asserted or

to be asserted under

is typically sent to an external bus

is

BG

Input Ignored

Input

Bus GrantÑBG is an active-low input. BG must be
asserted/deasserted synchronous to CLKOUT for
proper operation. BG
arbitration circuit when the DSP56309 becomes the
next bus master. When BG
must wait until BB
mastership. When BG
is typically given up at the end of the current bus
cycle. This can occur in the middle of an instruction
that requires more than one external bus cycle for
execution.

is asserted by an external bus

is asserted, the DSP56309

is deasserted before taking bus

is deasserted, bus mastership

2-12 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

External Memory Expansion Port (Port A)

Table 2-8 External Bus Control Signals (Continued)

Signal

Name

BB Input/

CAS

Type

Output

Output Tri-stated Column Address StrobeÑWhen the DSP is the bus

State

During

Reset

Input Bus BusyÑBB is a bidirectional active-low

input/output and must be asserted and deasserted
synchronous to CLKOUT. BB
is active. Only after BB
bus master become the bus master (and then assert
the signal again). The bus master can keep BB
asserted after ceasing bus activity regardless of
whether BR
Òbus parkingÓ and allows the current bus master to
reuse the bus without rearbitration until another
device requires the bus. The deassertion of BB
done by an Òactive pull-upÓ method (i.e., BB
driven high and then released and held high by an
external pull-up resistor).

BB

requires an external pull-up resistor.

master, CAS
to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control
Register is cleared, the signal is tri-stated.

Signal Description

indicates that the bus

is deasserted can the pending

is asserted or deasserted. This is called

is an active-low output used by DRAM

is

is

BCLK Output Tri-stated Bus ClockÑWhen the DSP is the bus master, BCLK

is an active-high output. BCLK is active as a
sampling signal when the program address tracing
mode is enabled (by setting the ATE bit in the OMR).
When BCLK is active and synchronized to CLKOUT
by the internal PLL, BCLK precedes CLKOUT by 1/4
of a clock cycle. The BCLK rising edge can be used to
sample the internal program memory access on the
A0ÐA23 address lines.

BCLK

Output Tri-stated Bus Clock NotÑWhen the DSP is the bus master,

BCLK

is an active-low output and is the inverse of

the BCLK signal. Otherwise, the signal is tri-stated.

MOTOROLA DSP56309UM/D 2-13

Signal/Connection Descriptions

Interrupt and Mode Control

2.7 INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the chipÕs operating mode as it comes out
of hardware reset. After RESET
request lines.

Table 2-9 Interrupt and Mode Control

Signal Name Type

is deasserted, these inputs are hardware interrupt

State

During

Reset

Signal Description

RESET

MODA

Input Input ResetÑRESET is an active-low, Schmitt-trigger

input. Deassertion of RESET
synchronized to the clock out (CLKOUT). When
asserted, the chip is placed in the Reset state and
the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input
(such as a capacitor charging) to reset the chip
reliably. If RESET
CLKOUT, exact start-up timing is guaranteed,
allowing multiple processors to start
synchronously and operate together in lock-step.
When the RESET
chip operating mode is latched from the MODA,
MODB, MODC, and MODD inputs. The RESET
signal must be asserted after power up.

Input Input Mode Select AÑMODA is an active-low

Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into the OMR when the RESET
deasserted.

is deasserted synchronous to

signal is deasserted, the initial

is internally

signal is

IRQA

External Interrupt Request AÑAfter reset, this
signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQA
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQA
processor is in the stop standby state and IRQA
asserted, the processor exits the stop state.

is asserted synchronous to

to exit the wait state. If the

is

2-14 DSP56309UM/D MOTOROLA

Table 2-9 Interrupt and Mode Control (Continued)

Signal Name Type

State

During

Reset

Signal/Connection Descriptions

Interrupt and Mode Control

Signal Description

MODB

IRQB

MODC

Input Input Mode Select BÑMODB is an active-low

Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET
deasserted.

External Interrupt Request BÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQB
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQB

Input Input Mode Select CÑMODC is an active-low

Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET
deasserted.

is asserted synchronous to

to exit the wait state.

signal is

signal is

IRQC

External Interrupt Request CÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQC
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQC

is asserted synchronous to

to exit the wait state.

MOTOROLA DSP56309UM/D 2-15

Signal/Connection Descriptions

Host Interface (HI08)

Table 2-9 Interrupt and Mode Control (Continued)

State

Signal Name Type

During

Reset

Signal Description

MODD

IRQD

Input Input Mode Select DÑMODD is an active-low

Schmitt-trigger input, internally synchronized to
CLKOUT. MODA, MODB, MODC, and MODD
select one of 16 initial chip operating modes,
latched into OMR when the RESET
deasserted.

External Interrupt Request DÑAfter hardware
reset, this signal becomes a level-sensitive or
negative-edge-triggered, maskable interrupt
request input during normal instruction
processing. If IRQD
CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and
asserting IRQD

is asserted synchronous to

to exit the wait state.

signal is

2.8 HOST INTERFACE (HI08)

The HI08 provides a fast parallel 8-bit port, which can connect directly to the host bus.

The HI08 supports a variety of standard buses and can be directly connected to a
number of industry standard microcomputers, microprocessors, DSPs, and DMA
hardware.

2.8.1 Host Port Usage Considerations

When reading multiple-bit registers that are written by another asynchronous system,
you must synchronize carefully. This problem commonly occurs when two
asynchronous systems are connected (as they are in the host port). The considerations
for proper operation are discussed in Table 2-10.

2-16 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-10 Host Port Usage Considerations

Action Description

Host Interface (HI08)

Asynchronous read of
receive byte registers

Asynchronous write to
transmit byte registers

Asynchronous write to
host vector

When reading the receive byte registers, receive register high
(RXH), receive register middle (RXM), or receive register low
(RXL), use interrupts or poll the receive register data full
(RXDF) flag which indicates that data is available. This assures
that the data in the receive byte registers is valid.

Do not write to the transmit byte registers, transmit register
high (TXH), transmit register middle (TXM), or transmit
register low (TXL), unless the transmit register data empty
(TXDE) bit is set indicating that the transmit byte registers are
empty. This guarantees that the transmit byte registers transfer
valid data to the host receive (HRX) register.

Change the host vector (HV) register only when the host
command bit (HC) is clear. This guarantees that the DSP
interrupt control logic receives a stable vector.

2.8.2 Host Port Configuration

The functions of the signals associated with the HI08 vary according to the programmed
configuration of the interface as determined by the HI08 Port Control Register (HPCR).
Refer to Section 6ÑHost Interface (HI08) for detailed descriptions of this and the other
configuration registers used with the HI08.

Host interface signal descriptions for the DSP56309 are listed in Table 2-11.

MOTOROLA DSP56309UM/D 2-17

Signal/Connection Descriptions

Host Interface (HI08)

Table 2-11 Host Interface

Signal

Name

H0ÐH7

HAD0Ð
HAD7

PB0ÐPB7

HA0

Type

Input/

Output

Input/

Output

Input or

Output

Input

State

During

Reset

Tri-stated Host DataÑWhen the HI08 is programmed

to interface a non-multiplexed host bus and
the HI function is selected, these signals are
lines 0Ð7 of the data bidirectional, tri-state
bus.

Host AddressÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, these signals are lines
0Ð7 of the address/data bidirectional,
multiplexed, tri-state bus.

Port B 0Ð7ÑWhen the HI08 is configured as
GPIO through the HPCR, these signals are
individually programmed as inputs or
outputs through the HI08 data direction
register (HDDR).

Input Host Address Input 0ÑWhen the HI08 is

programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 0 of the host address input bus.

Signal Description

HAS

PB8

/HAS

Input

Input or

Output

Host Address StrobeÑWhen HI08 is
programmed to interface a multiplexed host
bus and the HI function is selected, this
signal is the host address strobe (HAS)
Schmitt-trigger input. The polarity of the
address strobe is programmable but is
configured active-low (HAS

Port B 8ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

) following reset.

2-18 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-11 Host Interface (Continued)

Host Interface (HI08)

Signal

HA1

HA8

PB9

HA2

Name

Type

Input

Input

Input or

Output

Input

State

During

Reset

Input Host Address Input 1ÑWhen the HI08 is

programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 1 of the host address (HA1)
input bus.

Host Address 8ÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, this signal is line 8 of
the host address (HA8) input bus.

Port B 9ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

Input Host Address Input 2ÑWhen the HI08 is

programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is line 2 of the host address (HA2)
input bus.

Signal Description

HA9

PB10

Input

Input or

Output

Host Address 9ÑWhen HI08 is programmed
to interface a multiplexed host bus and the
HI function is selected, this signal is line 9 of
the host address (HA9) input bus.

Port B 10ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

MOTOROLA DSP56309UM/D 2-19

Signal/Connection Descriptions

Host Interface (HI08)

Table 2-11 Host Interface (Continued)

Signal

Name

HRW

HRD

PB11

/HRD

Type

Input

Input

Input or

Output

State

During

Reset

Input Host Read/WriteÑWhen HI08 is

programmed to interface a single-data-strobe
host bus and the HI function is selected, this
signal is the host read/write

Host Read DataÑWhen HI08 is
programmed to interface a
double-data-strobe host bus and the HI
function is selected, this signal is the host
read data strobe (HRD) Schmitt-trigger
input. The polarity of the data strobe is
programmable, but is configured as
active-low (HRD

Port B 11ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

Signal Description

(HRW) input.

) after reset.

HDS

HWR
HWR

PB12

/HDS

/

Input

Input

Input or

Output

Input Host Data StrobeÑWhen HI08 is

programmed to interface a single-data-strobe
host bus and the HI function is selected, this
signal is the host data strobe (HDS)
Schmitt-trigger input. The polarity of the
data strobe is programmable, but is
configured as active-low (HDS
reset.

Host Write DataÑWhen HI08 is
programmed to interface a
double-data-strobe host bus and the HI
function is selected, this signal is the host
write data strobe (HWR) Schmitt-trigger
input. The polarity of the data strobe is
programmable, but is configured as
active-low (HWR

Port B 12ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

) following reset.

) following

2-20 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-11 Host Interface (Continued)

Host Interface (HI08)

Signal

Name

HCS

HA10

PB13

Type

Input

Input

Input or

Output

State

During

Reset

Input Host Chip SelectÑWhen HI08 is

programmed to interface a non-multiplexed
host bus and the HI function is selected, this
signal is the host chip select (HCS) input. The
polarity of the chip select is programmable,
but is configured active-low (HCS
reset.

Host Address 10ÑWhen HI08 is
programmed to interface a multiplexed host
bus and the HI function is selected, this
signal is line 10 of the host address (HA10)
input bus.

Port B 13ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

Signal Description

) after

MOTOROLA DSP56309UM/D 2-21

Signal/Connection Descriptions

Host Interface (HI08)

Table 2-11 Host Interface (Continued)

Signal

Name

HREQ/
HREQ

HTRQ
HTRQ

State

Type

Output

/

Output

During

Reset

Input Host RequestÑWhen HI08 is programmed

to interface a single host request host bus and
the HI function is selected, this signal is the
host request (HREQ) output. The polarity of
the host request is programmable, but is
configured as active-low (HREQ
reset. The host request can be programmed
as a driven or open-drain output.

Transmit Host RequestÑWhen HI08 is
programmed to interface a double host
request host bus and the HI function is
selected, this signal is the transmit host
request (HTRQ) output. The polarity of the
host request is programmable, but is
configured as active-low (HTRQ
reset. The host request can be programmed
as a driven or open-drain output.

Signal Description

) following

) following

PB14

Input or

Output

Port B 14ÑWhen the HI08 is programmed to
interface a multiplexed host bus and the
signal is configured as GPIO through the
HPCR, this signal is individually
programmed as an input or output through
the HDDR.

2-22 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-11 Host Interface (Continued)

Host Interface (HI08)

Signal

Name

HACK/
HACK

HRRQ
HRRQ

PB15

State

Type

Input

/

Output

Input or

Output

During

Reset

Input Host AcknowledgeÑWhen HI08 is

programmed to interface a single host
request host bus and the HI function is
selected, this signal is the host acknowledge
(HACK) Schmitt-trigger input. The polarity
of the host acknowledge is programmable,
but is configured as active-low (HACK
reset.

Receive Host RequestÑWhen HI08 is
programmed to interface a double host
request host bus and the HI function is
selected, this signal is the receive host request
(HRRQ) output. The polarity of the host
request is programmable, but is configured
as active-low (HRRQ
request can be programmed as a driven or
open-drain output.

Port B 15ÑWhen the HI08 is configured as
GPIO through the HPCR, this signal is
individually programmed as an input or
output through the HDDR.

Signal Description

) after reset. The host

) after

MOTOROLA DSP56309UM/D 2-23

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE

Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals which
implement the Motorola SPI.

2.9.1 ESSI0

The ESSI0 signal descriptions for the DSP56309 are listed in Table 2-12.

Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0)

Signal

Name

SC00

PC0

Type

Input or
Output

State

During

Reset

Input Serial Control 0ÑThe function of SC00 is

determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input).
For synchronous mode, this signal is used
either for Transmitter 1 output or for Serial
I/O Flag 0.

This signal is driven by a weak keeper after
reset.

Port C 0ÑThe default configuration
following reset is GPIO input PC0. When this
port is configured as PC0, signal direction is
controlled through the Port C direction
register (PRR0). The signal can be configured
as ESSI signal SC00 through the Port C
control register (PCR0).

Signal Description

2-24 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

SC01

PC1

SC02

Type

Input/
Output

Input or
Output

Input/
Output

State

During

Reset

Input Serial Control 1ÑThe function of this signal

is determined by the selection of either
synchronous or asynchronous mode. For
Asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous
mode, this signal is used either for
Transmitter 2 output or for Serial I/O Flag 1.

This signal is driven by a weak keeper after
reset.

Port C 1ÑThe default configuration
following reset is GPIO input PC1. When this
port is configured as PC1, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SC01 through
PCR0.

Input Serial Control Signal 2ÑSC02 is used for

frame sync I/O. SC02 is the frame sync for
both the transmitter and receiver in
synchronous mode and for the transmitter
only in asynchronous mode. When
configured as an output, this signal is the
internally generated frame sync signal. When
configured as an input, this signal receives an
external frame sync signal for the transmitter
(and the receiver in synchronous operation).

Signal Description

This signal is driven by a weak keeper after
reset.

PC2

Input or
Output

Port C 2ÑThe default configuration
following reset is GPIO input PC2. When this
port is configured as PC2, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SC02 through
PCR0.

MOTOROLA DSP56309UM/D 2-25

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

SCK0

Type

Input/
Output

State

During

Reset

Input Serial ClockÑSCK0 is a bidirectional

Schmitt-trigger input signal providing the
serial bit rate clock for the ESSI interface. The
SCK0 is a clock input or output used by both
the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous
modes.

Although an external serial clock can be
independent of and asynchronous to the DSP
system clock, it must exceed the minimum
clock cycle time of 6 T (i.e., the system clock
frequency must be at least three times the
external ESSI clock frequency). The ESSI
needs at least three DSP phases inside each
half of the serial clock.

This signal is driven by a weak keeper after
reset.

Signal Description

PC3

SRD0

PC4

Input or
Output

Input/
Output

Input or
Output

Port C 3ÑThe default configuration
following reset is GPIO input PC3. When this
port is configured as PC3, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SCK0 through
PCR0.

Input Serial Receive DataÑSRD0 receives serial

data and transfers the data to the ESSI receive
shift register. SRD0 is an input when data is
being received.

This signal is driven by a weak keeper after
reset.

Port C 4ÑThe default configuration
following reset is GPIO input PC4. When this
port is configured as PC4, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal SRD0 through
PCR0.

2-26 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

STD0

PC5

Input/
Output

Input or
Output

2.9.2 ESSI1

Type

State

During

Reset

Input Serial Transmit DataÑSTD0 is used for

transmitting data from the serial Transmit
shift register. STD0 is an output when data is
being transmitted.

This signal is driven by a weak keeper after
reset.

Port C 5ÑThe default configuration
following reset is GPIO input PC5. When this
port is configured as PC5, signal direction is
controlled through PRR0. The signal can be
configured as an ESSI signal STD0 through
PCR0.

Signal Description

The ESSI1 signal descriptions for the DSP56309 are listed in Table 2-13.

MOTOROLA DSP56309UM/D 2-27

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1)

Signal

Name

SC10

PD0

Type

Input or
Output

State

During

Reset

Input Serial Control 0ÑThe function of SC10 is

determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is used for
the receive clock I/O (Schmitt-trigger input).
For synchronous mode, this signal is used
either for Transmitter 1 output or for Serial
I/O Flag 0.

This signal is driven by a weak keeper after
reset.

Port D 0ÑThe default configuration
following reset is GPIO input PD0. When this
port is configured as PD0, signal direction is
controlled through the Port D direction
register (PRR1). The signal can be configured
as an ESSI signal SC10 through the Port D
control register (PCR1).

Signal Description

SC11

PD1

Input/
Output

Input or
Output

Input Serial Control 1ÑThe function of this signal

is determined by the selection of either
synchronous or asynchronous mode. For
asynchronous mode, this signal is the
receiver frame sync I/O. For synchronous
mode, this signal is used either for
Transmitter 2 output or for Serial I/O Flag 1.

This signal is driven by a weak keeper after
reset.

Port D 1ÑThe default configuration
following reset is GPIO input PD1. When this
port is configured as PD1, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SC11 through
PCR1.

2-28 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

Signal

Name

SC12

PD2

Type

Input/
Output

Input or
Output

State

During

Reset

Input Serial Control Signal 2ÑSC12 is used for

frame sync I/O. SC12 is the frame sync for
both the transmitter and receiver in
synchronous mode and for the transmitter
only in asynchronous mode. When
configured as an output, this signal is the
internally generated frame sync signal. When
configured as an input, this signal receives an
external frame sync signal for the transmitter.
The receiver receives an external frame sync
signal as well when in synchronous
operation).

This signal is driven by a weak keeper after
reset.

Port D 2ÑThe default configuration
following reset is GPIO input PD2. When this
port is configured as PD2, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SC12 through
PCR1.

Signal Description

MOTOROLA DSP56309UM/D 2-29

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

Signal

Name

SCK1

Type

Input/
Output

State

During

Reset

Input Serial ClockÑSCK1 is a bidirectional

Schmitt-trigger input signal providing the
serial bit rate clock for the ESSI interface. The
SCK1 is a clock input or output used by both
the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous
modes.

Although an external serial clock can be
independent of and asynchronous to the DSP
system clock, it must exceed the minimum
clock cycle time of 6T (i.e., the system clock
frequency must be at least three times the
external ESSI clock frequency). The ESSI
needs at least three DSP phases inside each
half of the serial clock.

This signal is driven by a weak keeper after
reset.

Signal Description

PD3

SRD1

PD4

Input or
Output

Input/
Output

Input or
Output

Port D 3ÑThe default configuration
following reset is GPIO input PD3. When this
port is configured as PD3, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SCK1 through
PCR1.

Input Serial Receive DataÑSRD1 receives serial

data and transfers the data to the ESSI receive
shift register. SRD1 is an input when data is
being received.

This signal is driven by a weak keeper after
reset.

Port D 4ÑThe default configuration
following reset is GPIO input PD4. When this
port is configured as PD4, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal SRD1 through
PCR1.

2-30 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Enhanced Synchronous Serial Interface

Table 2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)

Signal

Name

STD1

PD5

Type

Input/
Output

Input or
Output

State

During

Reset

Input Serial Transmit DataÑSTD1 is used for

transmitting data from the serial transmit
shift register. STD1 is an output when data is
being transmitted.

This signal is driven by a weak keeper after
reset.

Port D 5ÑThe default configuration
following reset is GPIO input PD5. When this
port is configured as PD5, signal direction is
controlled through PRR1. The signal can be
configured as an ESSI signal STD1 through
PCR1.

Signal Description

MOTOROLA DSP56309UM/D 2-31

Signal/Connection Descriptions

Serial Communication Interface (SCI)

2.10 SERIAL COMMUNICATION INTERFACE (SCI)

SCI provides a full duplex port for serial communication to other DSPs, microprocessors,
or peripherals such as modems. SCI signal descriptions are listed in Table 2-14.

Table 2-14 Serial Communication Interface (SCI)

Signal

RXD

PE0

TXD

Name

Type

Input

Input or
Output

Output

State

During

Reset

Input Serial Receive DataÑThis input receives

byte oriented serial data and transfers it to
the SCI receive shift register.

This signal is driven by a weak keeper after
reset.

Port E 0ÑThe default configuration
following reset is GPIO input PE0. When this
port is configured as PE0, signal direction is
controlled through the SCI Port E direction
register (PRR). The signal can be configured
as an SCI signal RXD through the SCI Port E
control register (PCR).

Input Serial Transmit DataÑThis signal transmits

data from SCI transmit data register.

This signal is driven by a weak keeper after
reset.

Signal Description

PE1

Input or
Output

Port E 1ÑThe default configuration
following reset is GPIO input PE1. When this
port is configured as PE1, signal direction is
controlled through the SCI PRR. The signal
can be configured as an SCI signal TXD
through the SCI PCR.

2-32 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-14 Serial Communication Interface (SCI) (Continued)

Timers

Signal

Name

SCLK

PE2

Type

Input/
Output

Input or
Output

State

During

Reset

Input Serial ClockÑThis is the bidirectional

Schmitt-trigger input signal providing the
input or output clock used by the transmitter
and/or the receiver.

This signal is driven by a weak keeper after
reset.

Port E 2ÑThe default configuration
following reset is GPIO input PE2. When this
port is configured as PE2, signal direction is
controlled through the SCI PRR. The signal
can be configured as an SCI signal SCLK
through the SCI PCR.

2.11 TIMERS

Signal Description

Three identical and independent timers are implemented in the DSP56309. Each timer
can use internal or external clocking; each timer can interrupt the DSP56309 after a
specified number of events (clocks) or can signal an external device after counting a
specific number of internal events. Triple timer signal descriptions are listed in
Table 2-15.

MOTOROLA DSP56309UM/D 2-33

Signal/Connection Descriptions

Timers

Table 2-15 Triple Timer Signals

Signal

Name

TIO0 Input or

TIO1 Input or

Type

Output

Output

State

During

Reset

Input Timer 0 Schmitt-Trigger Input/OutputÑ

When timer 0 functions as an external event
counter or in measurement mode, TIO0 is
used as input. When timer 0 functions in
watchdog, timer, or pulse modulation mode,
TIO0 is used as output.

This signal is driven by a weak keeper after
reset.

The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 0
control/status register (TCSR0).

Input Timer 1 Schmitt-Trigger Input/OutputÑ

When Timer 1 functions as an external event
counter or in measurement mode, TIO1 is
used as input. When timer 1 functions in
watchdog, timer, or pulse modulation mode,
TIO1 is used as output.

Signal Description

This signal is driven by a weak keeper after
reset.

The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 1
control/status register (TCSR1).

2-34 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-15 Triple Timer Signals (Continued)

OnCE/JTAG Interface

Signal

Name

TIO2 Input or

Type

Output

State

During

Reset

Input Timer 2 Schmitt-Trigger Input/OutputÑ

2.12 OnCE/JTAG INTERFACE

Signal Description

When Timer 2 functions as an external event
counter or in measurement mode, TIO2 is
used as input. When timer 2 functions in
watchdog, timer, or pulse modulation mode,
TIO2 is used as output.

This signal is driven by a weak keeper after
reset.

The default mode after reset is GPIO input.
This can be changed to output or configured
as a timer input/output through the timer 2
control/status register (TCSR2).

OnCE/JTAG interface signal descriptions are listed in Table 2-16.

Table 2-16 OnCE/JTAG Interface

Signal

Name

TCK Input Input Test ClockÑTCK is a test clock input signal

TDI Input Input Test Data InputÑTDI is a test data serial

Type

State

During

Reset

Signal Description

used to synchronize the JTAG test logic. Its
pin has a pull-up resistor.

input signal used for test instructions and
data. TDI is sampled on the rising edge of
TCK and has an internal pull-up resistor.

MOTOROLA DSP56309UM/D 2-35

Signal/Connection Descriptions

OnCE/JTAG Interface

Table 2-16 OnCE/JTAG Interface (Continued)

Signal

Name

TDO Output Tri-stated Test Data OutputÑTDO is a test data serial

TMS Input Input Test Mode SelectÑTMS is an input signal

TRST

Type

Input Input Test ResetÑTRST is an active-low

State

During

Reset

Signal Description

output signal used for test instructions and
data. TDO is tri-statable and is actively
driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of
TCK.

used to sequence the test controllerÕs state
machine. TMS is sampled on the rising edge
of TCK and has an internal pull-up resistor.

Schmitt-trigger input signal used to
asynchronously initialize the test controller.
TRST

has an internal pull-up resistor. TRST

must be asserted after power up.

2-36 DSP56309UM/D MOTOROLA

Signal/Connection Descriptions

Table 2-16 OnCE/JTAG Interface (Continued)

OnCE/JTAG Interface

Signal

Name

DE Input/

Type

Output

State

During

Reset

Input Debug EventÑDE is an open-drain,

bidirectional, active-low signal providing, as
an input, a means of entering debug mode of
operation from an external command
controller, and as an output, a means of
acknowledging that the chip has entered
debug mode. This signal, when asserted as
an input, causes the DSP56300 core to finish
the current instruction being executed, save
the instruction pipeline information, enter
debug mode, and wait for commands to be
entered from the debug serial input line. This
signal is asserted as an output for three clock
cycles when the chip enters debug mode as a
result of a debug request or as a result of
meeting a breakpoint condition. The DE
an internal pull-up resistor.

This is not a standard part of the JTAG TAP
controller. The signal connects directly to the
OnCE module to initiate debug mode
directly or to provide a direct external
indication that the chip has entered debug
mode. All other interfacing with the OnCE
module must occur through the JTAG port.

Signal Description

has

MOTOROLA DSP56309UM/D 2-37

Signal/Connection Descriptions

OnCE/JTAG Interface

2-38 DSP56309UM/D MOTOROLA

SECTION 3

MEMORY CONFIGURATION

MOTOROLA DSP56309UM/D 3-1

Memory Configuration

3.1 MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 RAM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.3 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.4 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.5 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18

3-2 DSP56309UM/D MOTOROLA

Memory Configuration

Memory Spaces

3.1 MEMORY SPACES

The DSP56309 provides three independent memory spaces:

¥ Program

¥ X data

¥ Y data

Each memory space uses 24-bit addressing by default. The program and data word
length is 24 bits. Moreover, this device supports remapping address attribute registers
Òon the fly,Ó thus allowing access to 16 M of memory.

The DSP56309 provides a sixteen-bit compatibility mode that effectively uses 16-bit
addressing for each memory space, allowing access to 64K each of memory. This mode
puts zeroes in the most significant byte of the usual (24-bit) program and data word; it
ignores the zeroed byte, thus effectively using 16-bit program and data words. The
sixteen-bit compatibility mode allows the DSP56309 to use 56000 object code without
change, thus minimizing system cost for applications that use the smaller address space.
See the DSP56300 Family Manual for further information.

3.1.1 Program Memory Space

Program memory space consists of the following:

¥ Internal program memory (Program RAM, 20K by default)

¥ Bootstrap Program ROM (192 x 24-bit)

¥ (Optionally) off-chip memory expansion (as much as 16 M in 24-bit mode and

64K in 16-bit mode)

¥ (Optionally) instruction cache (1K) formed from Program RAM

Program memory space at locations $FF00C0 to $FFFFFF is reserved and should not be
accessed.

3.1.2 Data Memory Spaces

Data memory space is divided into X data memory and Y data memory to match the
natural partitioning of DSP algorithms. The data memory partitioning allows the

MOTOROLA DSP56309UM/D 3-3

Memory Configuration

Memory Spaces

DSP56309 to feed two operands to the Data ALU simultaneously, enabling it to perform
a multiply-accumulate operation in one clock cycle.

X and Y data memory are identical in structure and functionality except for the upper
128 words of each space. The upper 128 words of X data memory are reserved for
internal I/O. We recommend that the programmer reserve the upper 128 words of Y
data memory for external I/O. (For further information, see Section 3.1.2.1 X Data
Memory Space and Section 3.1.2.2 Y Data Memory Space.)

X and Y data memory space each consist of the following:

¥ Internal data memory (X data RAM and Y data RAM, the default size of each is

7K, but they can be switched to 5K each)

¥ (Optionally) Off-chip memory expansion (up to 16 M in the 24-bit address mode

and 64K in the 16-bit address mode)

3.1.2.1 X Data Memory Space

The on-chip peripheral registers and some of the DSP56309 core registers occupy the top
128 locations of X data memory ($FFFF80Ð$FFFFFF in the 24-bit Address mode or
$FF80Ð$FFFF in the 16-bit Address mode). This area is called X-I/O space, and it can be
accessed by MOVE and MOVEP instructions and by bit oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET). For
a listing of the contents of this area, see the programming sheets in
Appendix DÑProgramming Reference.

The X memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.

3.1.2.2 Y Data Memory Space

The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80Ð$FFFFFF in the 24-bit address mode or $FF80Ð$FFFF in the 16-bit
address mode) to take advantage of the move peripheral data (MOVEP) instruction and
the bit oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).

The Y memory space at locations $FF0000 to $FFEFFF is reserved and should not be
accessed by the programmer.

3-4 DSP56309UM/D MOTOROLA

Memory Configuration

RAM Configuration

3.1.3 Memory Space Configuration

Memory space addressing is 24-bit by default. The DSP56309 switches to sixteen-bit
address compatibility mode by setting the sixteen-bit compatibility (SC) bit in the Status
Register (SR).

Table 3-1 Memory Space Configuration Bit Settings for the DSP56309

Bit

Abbreviation

SC Sixteen-bit

Compatibility

Bit Name Bit Location

SR 13 16M word

Cleared = 0

Effect (Default)

address space

(24-bit address)

Set = 1 Effect

64K word

address space

(16-bit address)

Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8.

3.2 RAM CONFIGURATION

The DSP56309 contains 34K of RAM, divided by default into the following:

¥ Program RAM (20K)

¥ X data RAM (7K)

¥ Y data RAM (7K)

RAM configuration depends on two bits: the Cache Enable (CE) of the SR and the
Memory Select (MS) of the Operating Mode Register (OMR).

Table 3-2 RAM Configuration Bit Settings for the DSP56309

Bit

Abbreviation

CE Cache

MS Memory

Bit Name

Enable

Switch

Bit

Location

SR 19 Cache Disabled Cache Enabled

OMR 7 Program RAM 20K

Cleared = 0 Effect

(Default)

X data RAM 7K
Y data RAM 7K

Set = 1 Effect

1K

Program RAM 24K

X data RAM 5K
Y data RAM 5K

MOTOROLA DSP56309UM/D 3-5

Memory Configuration

RAM Configuration

Memory maps for the different configurations are shown in Figure 3-1 through
Figure 3-8.

Note: The MS bit cannot be changed when CE is set. The instruction cache occupies

the top 1K of what would otherwise be Program RAM; if you switch memory
into or out of Program RAM when the cache is enabled, the switch causes
conflicts. To change the MS bit when CE is set, do the following:

1. Clear CE.

2. Change MS.

3. Set CE.

3.2.1 On-Chip Program Memory (Program RAM)

The on-chip Program RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 20K (default), 23K, 24K, or 19K locations in the program memory
space (depending on the settings of the MS and CE bits). The Program RAM default
organization is 80 banks of 256 24-bit words (20K). The upper eight banks of both X data
RAM and Y data RAM can be configured as Program RAM by setting the MS bit. When
the CE is set, the upper 1K of Program RAM is used as an internal Instruction Cache.

CAUTION

While the contents of Program RAM are unaffected by toggling the
MS bit, the location of program data placed in the Program
RAM/Instruction Cache area changes after the MS bit is toggled, since
the cache always occupies the top-most 1K Program RAM addresses.
To preserve program data integrity, do not set or clear the MS bit
when the CE bit is set. See Section 3.2 on page 3-5 for the correct
procedure.

3.2.2 On-Chip X Data Memory (X Data RAM)

The on-chip X data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the X memory space. The size of the
X data RAM depends on the setting of the MS bit (default: MS is cleared). The X data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the X data RAM to the Program RAM by setting the MS bit (leaving 5K
of X data RAM).

3-6 DSP56309UM/D MOTOROLA

Memory Configuration

Memory Configurations

3.2.3 On-Chip Y Data Memory (Y Data RAM)

The on-chip Y data RAM consists of 24-bit wide, high-speed, internal Static RAM
occupying the lowest 7K (default) or 5K locations in the Y memory space. The size of the
Y data RAM is dependent on the setting of the MS bit (default: MS is cleared). The Y data
RAM default organization is 28 banks of 256 (7K) 24-bit words. Eight banks of RAM can
be switched from the Y data RAM to the Program RAM by setting the MS bit (leaving 5K
of Y data RAM).

3.2.4 Bootstrap ROM

The bootstrap code is accessed at addresses $FF0000 to $FFF0BF (192 words) in program
memory space. The bootstrap ROM cannot be accessed in 16-bit address compatibility
mode. See Appendix AÑBootstrap Programs for a complete listing of the bootstrap
code.

3.3 MEMORY CONFIGURATIONS

Memory configuration determines the size and address range for addressable memory,
as well as the amount of memory allocated to Program RAM, data RAM, and the
instruction cache.

3.3.1 Memory Space Configurations

The memory space configurations are listed in Table 3-3.

Table 3-3 Memory Space Configurations for the DSP56309

SC Bit

Setting

0 16M words $000000Ð

1 64K words $0000Ð$FFFF 16

Addressable

Memory Size

Address Range

$FFFFFF

Number of

Address Bits

24

MOTOROLA DSP56309UM/D 3-7

Memory Configuration

Memory Configurations

3.3.2 RAM Configurations

The RAM configurations for the DSP56309 appear in Table 3-4.

Table 3-4 RAM Configurations for the DSP56309

Bit Settings Memory Sizes (in K)

MS CE

0020770

0119771

1024550

1123551

Program

RAM

X data

RAM

Y data

RAM

Cache

The actual memory locations for Program RAM and the instruction cache in the Program
memory space are determined by the MS and CE bits. Their addresses appear in

Table 3-5.

Table 3-5 Memory Locations for Program RAM and Instruction Cache

MS CE

0 0 $0000Ð$4FFF N/A

0 1 $0000Ð$4BFF $4C00Ð$4FFF

Program RAM

Location

Cache Location

1 0 $0000Ð$5FFF N/A

1 1 $0000Ð$5BFF $5C00Ð$5FFF

3-8 DSP56309UM/D MOTOROLA

Memory Configuration

Memory Maps

The actual memory locations for both X and Y data RAM in their own memory space are
determined by the MS bit. Their addresses appear in Table 3-6.

Table 3-6 Memory Locations for Data RAM

MS

0 $0000Ð$1BFF

1 $0000Ð$13FF

Data RAM

Location

3.4 MEMORY MAPS

Figure 3-1 through Figure 3-8 illustrate each of the memory space and RAM
configurations defined by the settings of the SC, MS, and CE bits. The figures show the
configuration, and the accompanying tables show the bit settings, memory sizes, and
memory locations.

MOTOROLA DSP56309UM/D 3-9

Memory Configuration

Memory Maps

Program X Data Y Data

$FFFFFF

$FFF0C0

$FF0000

$005000

$000000

Internal

Reserved

Bootstrap ROM

External

Internal

Program RAM

20K

$FFFFFF
$FFFF80

$FFF000

$FF0000

$001C00

$000000

Internal I/O

External

Internal

Reserved

External

Internal

X data RAM

7K

$FFFFFF

$FFFF80
$FFF000

$FF0000

$001C00

$000000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

X Data RAM Y Data RAM Cache

External I/O

External

Internal

Reserved

External

Internal

Y data RAM

7K

Addressable

Memory Size

000 20K

None 16M

$0000Ð$4FFF7K$0000Ð$1BFF7K$0000Ð$1BFF

AA0557

Figure 3-1 Default Settings (0, 0, 0)

3-10 DSP56309UM/D MOTOROLA

Memory Configuration

Program X Data Y Data

Memory Maps

$FFFFFF

$FFF0C0

$FF0000

$005000

$004C00

$000000

Internal

Reserved

Bootstrap ROM

External

I-Cache

1K

Internal

Program RAM

19K

$FFFFFF

$FFFF80

$FFF000

$FF0000

$001C00

$000000

Internal I/O

External

Internal

Reserved

External

Internal

X data RAM

7K

$FFFFFF

$FFFF80

$FFF000

$FF0000

$001C00

$000000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

X Data

RAM

Y Data

RAM

External I/O

External

Internal

Reserved

External

Internal

Y data RAM

7K

Cache

Addressable

Memory Size

001 19K

$0000Ð

$4BFF

7K

$0000Ð

$1BFF

7K

$0000Ð

$1BFF

1K

$4C00Ð

$4FFF

16 M

AA0561

Figure 3-2 Instruction Cache Enabled (0, 0, 1)

MOTOROLA DSP56309UM/D 3-11

Memory Configuration

Memory Maps

Program X Data Y Data

$FFFFFF

$FFF0C0

$FF0000

$006000

$000000

Internal

Reserved

Bootstrap ROM

External

Internal

Program RAM

24K

$FFFFFF

$FFFF80

$FFF000

$FF0000

$001400

$000000

Internal I/O

External

Internal

Reserved

External

Internal

X data RAM

5K

$FFFFFF

$FFFF80

$FFF000

$FF0000

$001400

$000000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

X Data

RAM

Y Data

RAM

External I/O

External

Internal

Reserved

External

Internal

Y data RAM

5K

Cache

Addressable

Memory Size

010 24K

$0000Ð

$5FFF

5K

$0000Ð

$13FF

5K

$0000Ð

$13FF

None 16 M

AA0559

Figure 3-3 Switched Program RAM (0, 1, 0)

3-12 DSP56309UM/D MOTOROLA

Memory Configuration

Program X Data Y Data

Memory Maps

$FFFFFF

$FFF0C0

$FF0000

$006000

$005C00

$000000

Internal

Reserved

Bootstrap ROM

External

I-Cache

1K

Internal

Program

RAM 23K

$FFFFFF

$FFFF80
$FFF000

$FF0000

$001400

$000000

Internal I/O

External

Internal

Reserved

External

Internal

X data RAM

5K

$FFFFFF

$FFFF80
$FFF000

$FF0000

$001400

$000000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

X Data

RAM

Y Data

RAM

External I/O

External

Internal

Reserved

External

Internal

Y data RAM

5K

Cache

Addressable

Memory Size

011 23K

$0000Ð

$5BFF

5K

$0000Ð

$13FF

5K

$0000Ð

$13FF

1K

$5C00Ð

$5FFF

16 M

AA0563

Figure 3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1)

MOTOROLA DSP56309UM/D 3-13

Memory Configuration

Memory Maps

Program X Data Y Data

$FFFF

$5000

$0000

External

Internal

Program RAM

20K

$FFFF
$FF80

$1C00

$0000

Internal I/O

External

Internal

X data RAM

7K

$FFFF
$FF80

$1C00

$0000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

X Data

RAM

Y Data

RAM

External I/O

External

Internal

Y data RAM

7K

Cache

Addressable

Memory Size

100 20K

$0000Ð

$4FFF

7K

$0000Ð

$1BFF

7K

$0000Ð

$1BFF

None 64K

AA0558

Figure 3-5 16-bit Space with Default RAM (1, 0, 0)

3-14 DSP56309UM/D MOTOROLA

$FFFF

Memory Configuration

Program X Data Y Data

External

$FFFF

$FF80

Internal I/O

External

$FFFF

$FF80

External I/O

External

Memory Maps

$5000

$4C00

$0000

I-Cache

1K

Internal

Program RAM

19K

$1C00

$0000

$1C00

Internal

X data RAM

7K

$0000

Bit Settings Memory Configuration

SC MS CE

Program

RAM

101 19K

$0000Ð

$4BFF

X Data

RAM

7K

$0000Ð

$1BFF

Y Data

RAM

7K

$0000Ð

$1BFF

Internal

Y data RAM

7K

Cache

1K

$4C00Ð

$4FFF

Addressable

Memory Size

64K

AA0562

Figure 3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1)

MOTOROLA DSP56309UM/D 3-15