MITSUBISHI PS21267-P, PS21267-AP Technical data

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21267-P/AP

TRANSFER-MOLD TYPE

TRANSFER-MOLD TYPE

INSULATED TYPE

INSULATED TYPE

PS21267

PS21267-P/AP

INTEGRATED POWER FUNCTIONS

600V/30A low-loss CSTBTTM inverter bridge for three
phase DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.

• For lower-leg IGBT

• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).

•Input interface : 3, 5V line compatible. (High Active)

•UL Approved : Yellow Card No. E80276

S : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).

APPLICATION

AC100V~200V three-phase inverter drive for small power motor control.

Fig. 1 PACKAGE OUTLINES

0.3

±

2.8

1

2 3 4 5 6 7 8 9

Type name , Lot No.

0.2

±

2-φ4.5

0.3

±

±

10

10

(Short-pin type : PS21267-P) Refer Fig. 6 for long-pin type : PS21267-AP.

27×2.8(=75.6)

D

Heat sink side

10 1312 1514 16 17 18 19 20 2111

0.5

±

21.4

0.5

0.5

±

31

0.5

±

11.5

2625242322

0.3

±

0.3

10

±

67

±

79

0.3

±

20

0.3

0.5

CB

0.5

±

0.5

±

12.8

8

(71)

Heat sink side

±

34.9

0.5

±

13.4

OTHERS

0.2

±

1

Irregular solder remains

(2.5)

DETAIL B

(5 pins t = 0.7)

0.5

±

(11.5)(8.5)

28

A

0.2

±

3.8

1

0.7

0.7

C0.2

0.5MAX

C0.2

TERMINAL 22, 26

0.2

±

0.2

±

0.2

±

0.5

±

0.6

NOTE

TERMINAL CODE

1. UP

2. VP1

3. VUFB

4. VUFS

5. VP

6. VP1

7. VVFB

8. VVFS

9. WP

10. VP1

11. VPC

12. VWFB

13. VWFS

0.2

±

0.8

OTHERS

DETAIL C

(21 pins t = 0.7)

Dimensions in mm

14. VN1

15. VNC

16. CIN

17. CFO

18. FO

19. UN

20. VN

21. WN

22. P

23. U

24. V

25. W

26. N

0.2

±

0.8

0.2

±

0.45

0.2

±

0.8

0.2

±

0.45

0.2

±

0.45

0.5

±

0.5MAX

Irregular solder remains

0.6

TERMINAL 1-2, 20-21

0.2

±

0.5

(0 ~ 5°)

DETAIL DDETAIL A

Note: All outer lead terminals are with Pb-free solder plating.

Oct. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBW–

CBV+

CBU–

CBV–

C1 : Tight tolerance, temp-compensated electrolytic type

(Note : The capacitance value depends on the PWM control

scheme used in the applied system.)

C2 : 0.22~2µF R-category ceramic capacitor for noise filtering

Inrush current
limiter circuit

High-side input (PWM)
(3, 5V line) (Note 1, 2)

Input signal
conditioning

Level shifter

Protection

circuit (UV)

Drive circuit

P

Input signal

Input signal

conditioning

conditioning

Level shifter Level shifter

Drive circuit Drive circuit

Protection

circuit (UV)

Protection

circuit (UV)

CBU+

PS21267-P/AP

TRANSFER-MOLD TYPE

INSULATED TYPE

CBW+

C2

(Note 7)

C1

(Note 6)

DIP-IPM

AC line input

(Note 4)

C

Z

Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)

(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment.)

Note1: The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor.
If using external RC filter, pay attention to satisfy the turn-on/off threshold voltage requirement.

2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer

isolation is possible.

3: This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor.
4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high

surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.

5: Fo output pulse width should be decided by putting external capacitor between CFO and V
6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
7: To prevent IC

S

from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals.

Input signal conditioning

Low-side input (PWM)
(3, 5V line) (Note 1, 2)

N1

V

NC

Fo logic

FOCFO

Fault output (5V line)
(Note 3, 5)

N

CIN

Drive circuit

Protection

Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT

DIP-IPM

P

H-side IGBT

A

B

(Note 2)

V

CIN

N

NC

L-side IGBT

External protection circuit

Shunt Resistor

N1

(Note 1)

R

C

C

Note1: In the recommended external protection circuit, please select the RC

time constant in the range 1.5~2.0µs.

2: To prevent erroneous protection operation, the wiring of A, B, C should

be as short as possible.

Drive circuit

S

S

Drive circuit

Protection circuit

Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.

IC (A)

U
V

W

0

circuit

Collector current

waveform

2

H-side IGBT

S

U

V

W

M

AC line output

L-side IGBT

Control supply
Under-Voltage

protection

NC

terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))

SC Protection

Trip Level

S

V

NC

(15V line)

(Note 7)

D

V

w

(µs)

t

Oct. 2005

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21267-P/AP

TRANSFER-MOLD TYPE

INSULATED TYPE

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART

ConditionSymbol Parameter Ratings Unit

CC

V
VCC(surge)
VCES

±IC
±ICP

PC
Tj

Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature

Applied between P-N

Applied between P-N

T

C = 25°C
C = 25°C, less than 1ms

T

C = 25°C, per 1 chip

T

(Note 1)

450
500
600

30
60

55.5

–20~+125

Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C) however, to in-

sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).

CONTROL (PROTECTION) PART

ConditionSymbol Parameter Ratings Unit

VD

VDB

VIN

VFO

IFO
VSC

Control supply voltage

Control supply voltage

Input voltage

Fault output supply voltage
Fault output current
Current sensing input voltage

Applied between V

Applied between VUFB-VUFS, VVFB-VVFS,

Applied between UP, VP, WP-VPC, UN, VN,

Applied between FO-VNC

Sink current at FO terminal
Applied between CIN-V

P1-VPC, VN1-VNC

VWFB-VWFS

WN-VNC

NC

–0.5~V

–0.5~V

–0.5~V

20

20

D+0.5

D+0.5

1

D+0.5

V
V
V
A

A
W
°C

V

V

V

V

mA

V

TOTAL SYSTEM

Symbol Ratings Unit

V

CC(PROT)

TC
Tstg

Viso

Self protection supply voltage limit
(short circuit protection capability)

Module case operation temperature

Storage temperature

Isolation voltage

Parameter

D = 13.5~16.5V, Inverter part

V
Tj = 125°C, non-repetitive, less than 2 µs

60Hz, Sinusoidal, AC 1 minute, connecting
pins to heat-sink plate

Note 2 : TC measurement point

Control terminals

T

C

Power terminals

Condition

Heat sink boundary

(Note 2)

Heat sink

400

–20~+100

–40~+125

2500

T

C

V

°C

°C

rms

V

Oct. 2005