Mitsubishi MH8S72DBFD-8, MH8S72DBFD-7 Datasheet
Preliminary Spec.
DESCRIPTION
APPLICATION
Type name
6ns (CL = 2, 3)
MH8S72DBFD-7
Frequency
100MHz
6ns (CL = 3)
MH8S72DBFD-8
100MHz
[component level]
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
The MH8S72DBFD is 8388608 - word x 72-bit Synchronous
DRAM module. This consist of nine industry standard
8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities memory
are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Max.
CLK
Access Time
MITSUBISHI LSIs
MH8S72DBFD-7,-8
85pin
94pin
95pin
1pin
10pin
11pin
Utilizes industry standard 8M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
Main memory or graphic memory in computer systems
124pin
125pin
168pin
40pin
41pin
84pin
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
1
Preliminary Spec.
/WE
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61 NC
20 DQ15 62
21
22
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
A10
BA1
43
54 VSS
63
64 VSS
69 DQ24
80 NC
81
VSS 85
CB2
CB3
100
101
102
103
NC
CKE1
VSS 110
CK2
WP
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
NC
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
NC
NC
CB6
CB7
NC
REGE
CK3
NC = No Connection
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
D0
R/S0,2
RDQM 0
RDQM 1
RDQM 4
RDQM 3
RDQM 2
RDQM 7
RDQM 5
RDQM 6
D4D6D7
D8D5D2
D3
D1
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Add
CKE0
/S0,2
DQM0-7
/W
/RAS
/CAS
10K
VDD
From PLL
CK0
CK1 - CK3
RCKE0
R/S0
R/S2
REGE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
PLL
Terminated
D0-8
D0-2,5-6
D3-4,7-8
RCKE0
RDQM0-7
D0
D1-2
D3
D4
D5
D6
D7
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
WP
47K
VDD
VSS
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
D0 to D8
D0 to D8
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
CKE0
Register enable:When REGE is low,All control signals and
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PIN FUNCTION
MITSUBISHI LSIs
MH8S72DBFD-7,-8
CK0
/S0,2
/RAS,/CAS,/W
A0-11
Input
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/W defines basic
commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
BA0-1
DQ0-63
CB0-7
DQM0-7
Vdd,Vss
REGE
Input
Input/Output
Input
Power Supply
Input
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is specifies the four bank to which
a command is applied.BA must be set with ACT ,PRE
,READ ,WRITE commands
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted
module.
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
READ command starts burst read from the active bank indicated by BA.First output
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH8S72DBFD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
define basic commands
A10
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
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Preliminary Spec.
& Read
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH8S72DBFD-7,-8
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank PREA H X L L H L X H X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX
Burst Terminate TBST H X L H H L X X X
Mode Register Set MRS H X L L L L L L V*1
ACT H X L L H H V V V
WRITE H X L H L L V L V
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
CKE
CKE
n-1
L H H X X X X X X
L H L H H H X X X
n
/RAS /CAS /WE BA0,1 A10 A0-9
/S
A11
X
X
V
X
X
X
X
X
X
X
X
X
X
X
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0351-0.0
MITSUBISHI
30/Sep. /1999
ELECTRIC
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Preliminary Spec.
Action
Begin Write,Latch CA,
Terminate Burst,Latch CA,
Terminate Burst,Latch CA,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE
Current State /S /RAS /CAS /WE Address Command
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT Bank Active,Latch RA
L L H L BA,A10 PRE/PREA NOP*4
L L L H X REFA Auto-Refresh*5
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
Determine Auto-Precharge
MIT-DS-0351-0.0
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
MRS ILLEGAL
MITSUBISHI
Begin New Read,Determine
Auto-Precharge*3
Begin Write,Determine AutoPrecharge*3
30/Sep. /1999
ELECTRIC
7
Preliminary Spec.
Terminate Burst,Latch CA,
Terminate Burst,Latch CA,
Op-Code,
Op-Code,
Op-Code,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
WRITE
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
READ with
AUTO
PRECHARGE
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
Mode-Add
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
Begin Read,Determine AutoPrecharge*3
Begin Write,Determine AutoPrecharge*3
ILLEGAL
WRITE with
AUTO
PRECHARGE
MIT-DS-0351-0.0
L L L L
H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Mode-Add
Mode-Add
MITSUBISHI
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
ILLEGAL
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ELECTRIC
Preliminary Spec.
Action
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Op-Code,
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
MRS ILLEGAL
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
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Preliminary Spec.
Op-Code,
Op-Code,
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Mode-Add
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Mode-Add
MRS ILLEGAL
MRS ILLEGAL
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0351-0.0
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ELECTRIC
Preliminary Spec.
Action
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
CKE
Current State
SELF - H X X X X X X INVALID
REFRESH*1 L H H X X X X Exit Self-Refresh(Idle after tRC)
CKE
n-1
L H L H H H X Exit Self-Refresh(Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP(Maintain Self-Refresh)
n
/RAS /CAS /WE Add
/S
POWER H X X X X X X INVALID
DOWN L H X X X X X Exit Power Down to Idle
L L X X X X X NOP(Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE*2 H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State = Power Down
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CK0 Suspend at Next Cycle*3
listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3
L L X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
3. Must be legal command.
MIT-DS-0351-0.0
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ELECTRIC
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Preliminary Spec.
POWER ON SEQUENCE
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
MODE REGISTER
LENGTH
BURST
LATENCY
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 WM 0 0
/CAS LATENCY
R
R
2
3
R
R
R
R
LTMODE BT BL
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
0
WRITE
MODE
MIT-DS-0351-0.0
1
BURST
SINGLE BIT
R:Reserved for Future Use
FP: Full Page
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Preliminary Spec.
Write
Burst Type
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CK
Command
Read
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS
Latency
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Burst
Length
Column Addressing
Y
D0 D1
Burst
Length
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0351-0.0
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI
ELECTRIC
30/Sep. /1999
13
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
Parameter
mA
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted)
Parameter
CAPACITANCE
Parameter
f=1MHz
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Symbol
Vdd
VI
VO
IO
Pd
Topr
Tstg
Symbol
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Condition Ratings Unit
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25C
Limits
Min. Typ. Max.
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
12
0 ~ 70
-40 ~ 100
V
V
V
W
C
C
Unit
Vdd
Vss
VIH*1
VIL*2
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
Supply Voltage
Supply Voltage
3.0
0
2.0
-0.3
Test Condition Limits(max.) Unit
VI = Vss
Vi=25mVrms
3.3
0
Vdd+0.3
20
20
20
22
3.6
0
0.8
V
V
V
V
pF
pF
pF
pF
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
14
Preliminary Spec.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
Limits
Unit
IOH=-2mA
Limits
(max)
precharge stanby
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
one bank active (discrete)
Some contents are subject to change without notice.
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1.Icc(max) is specified at the output open condition.
2.Input signal are changed one time during 30ns.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=15ns
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-7,8
655
43
34
205
160
295
250
655
1015
34
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol Parameter Test Condition
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC) IOL=2mA
IOZ Off-stare Output Current Q floating VO=0 ~ Vdd
Ii Input Current VIH=0 ~ Vdd+0.3V -10 10 uA
MIT-DS-0351-0.0
MITSUBISHI
Min. Max.
2.4 V
-10
ELECTRIC
0.4 V
uA
10
30/Sep. /1999
15
Preliminary Spec.
AC TIMING REQUIREMENTS
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
tSRX
Some contents are subject to change without notice.
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
LATCH MODE
Limits
Symbol
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tPDE
tREF
Parameter
CK cycle time
CL=3
CL=4
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
Min.
-7
Max.
10
10
3
3 ns
1
2 ns
1 ns
70
20
50 100000
20
20
20 ns
10
10
10
10
64
Min.
13
10 ns
3
3
1
2
1
70
20
50
20
20
20
10
10
10
MITSUBISHI LSIs
-8
Unit
Max.
ns
ns
10
ns
ns
ns
100000
ns
ns
ns
ns
ns
ns
64
ms
CK
1.4V
Any AC timing is
referenced to the input
signal crossing
Signal
MIT-DS-0351-0.0
1.4V
MITSUBISHI
through 1.4V.
30/Sep. /1999
ELECTRIC
16
Preliminary Spec.
tSRX
Some contents are subject to change without notice.
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tPDE
tREF
Parameter
CK cycle time
CL=2
CL=3
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
MITSUBISHI LSIs
MH8S72DBFD-7,-8
Limits
-7
Min.
10
10
3
3 ns
1
7 ns
0
70
20
50 100000
20
20 ns
20 ns
10
10
10
Max.
10
64
Min.
-8
Max.
13
10 ns
3
3
1
7
0
70
20
50
20
20
20
10
10
10
10
100000
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns
should be added to the parameter.
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
LATCH MODE
Limits
Min.
-7
Max.
6
6
Symbol
tAC
Parameter
Access time from CK
CL=3
CL=4
Output Hold time
tOH
from CK
Delay time, output low
tOLZ
impedance from CK
Delay time, output high
tOHZ
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
impedance from CK
3
0
3
6
Min.
3
0
3
-8
Max.
7
6
6
Unit
ns
ns
ns
ns
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999
17
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