Mitsubishi MH8S72DALD-6, MH8S72DALD-7, MH8S72DALD-8 Datasheet
Preliminary Spec.
DESCRIPTION
for easy interchange or addition of modules.
APPLICATION
4096 refresh cycle /64ms
(Component SDRAM)
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
The MH8S72DALD is 8388608 - word by 72-bit
Synchronous DRAM module. This consists of nine
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
85pin
94pin
1pin
10pin
FEATURES
Frequency
133MHz
-7
-8
Utilizes industry standard 8M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
100MHz
CLK Access Time
5.4ns(CL=3)-6
6.0ns(CL=2)
6.0ns(CL=3)100MHz
95pin
124pin
125pin
11pin
40pin
41pin
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
PC main memory
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168pin
84pin
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Preliminary Spec.
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1
2 DQ0 44 NC
3 DQ1 45 /S2
4 DQ2 46 DQMB2
5 DQ3 47 DQMB3
6 VDD 48 NC
7 DQ4 49 VDD
8 DQ5 50 NC
9 DQ6 51 NC
10 DQ7 52
11 DQ8 53
12
13 DQ9 55 DQ16
14 DQ10 56 DQ17
15 DQ11 57 DQ18
16 DQ12 58 DQ19
17 DQ13 59 VDD
18 VDD 60 DQ20
19 DQ14 61
20 DQ15 62
21
22 64 VSS
23 VSS 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 VDD 68
27
28 DQMB0 70 DQ25
29 DQMB1 71 DQ26
30 /S0 72 DQ27
31 NC 73 VDD
32 VSS 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 VSS
37 A8 79
38
39
40 VDD 82 SDA
41 VDD 83 SCL
42 CK0 84 VDD
VSS
VSS
CB0
CB1
/WE0
A10
BA1
43
54 VSS
63
69 DQ24
80 NC
81
MH8S72DALD -6,-7,-8
VSS 85
86
87
88
89
90
91
92
93
CB2
CB3 95
NC
NC
NC
VSS 110
CK2
WP
94
96
97
98
99
100
101
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
MITSUBISHI LSIs
VSS 127
DQ32 128
DQ33 129
DQ34 130 DQMB6
DQ35 131 DQMB7
VDD 132
DQ36 133 VDD
DQ37 134 NC
DQ38 135 NC
DQ39 136 CB6
DQ40 137
VSS 138 VSS
DQ41 139 DQ48
DQ42 140 DQ49
DQ43 141 DQ50
DQ44 142 DQ51
DQ45 143 VDD
VDD 144 DQ52
DQ46 145 NC
DQ47 146 NC
CB4
CB5
VSS 149 DQ53
NC 150 DQ54
NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56
DQMB4 154 DQ57
DQMB5 155 DQ58
NC
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61
A3 160 DQ62
A5 161 DQ63
A7 162 VSS
A9 163
BA0
A11
VDD 166 SA1
CK1 167 SA2
NC
147 NC
148 VSS
156 DQ59
164 NC
165 SA0
168 VDD
VSS
CKE0
NC
NC
CB7
CK3
NC = No Connection
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Preliminary Spec.
Block Diagram
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
/S0
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D1
D8
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CK0
CK2
CK1
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D5
5SDRAMs
4SDRAMs+3.3pF cap.
CK3
/S2
DQMB2 DQMB6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D3
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM /CS
DQM /CS
CKE0
SCL
WP
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
47K
D6
D7
D0 - D8
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
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Preliminary Spec.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
ECC
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8-8-7
-7
-7,-8
-6
-7,-8
-6
-7,-8
-6
-6
-6
-7,-8
-6
-7,-8-6-7,-8-6-7,-8
-6
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
Byte
0
Defines # bytes written into serial memory at module mfgr
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
26
27
28
29
30
Total # bytes of SPD memory device
# Column Addresses on this assembly
Voltage interface standard of this assembly LVTTL 01
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(2nd highest CAS latency)
Function described
Fundamental memory type
# Row Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
SPD enrty data SPD DATA(hex)
128
256 Bytes
SDRAM
A0-A11 0C
A0-A8 09
1BANK 01
x72 48
0 00
10ns
5.4ns
6ns
self refresh(15.625uS)
x8
x8
1 01
4bank
3
2/3
0
0
N/A
10ns
13ns
N/A
6ns
7ns 70
N/A 00
22.5ns 17
20ns 14
15ns 0F
20ns 14
22.5ns 17
20ns 14
45ns 2D
50ns 32
80
08
04
757.5ns
A0
54
60
02
80
08
08
8F
04
04
06
01
01
00
0E
00
A0
D0
00
60
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Preliminary Spec.
Serial Presence Detect Table II
4D483853373244414C442D36202020202020
-7
-6,-8
-6
-7,-8-6-7,-8-6-7,-8
-6
-7,-8
-6
-7,-8
4D483853373244414C442D37202020202020
4D483853373244414C442D38202020202020
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
31 Density of each bank on module 64MByte 10
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
35
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71
72 Manufacturing location
Superset Information (may be used in future)
Data signal input hold time
Manufactures Jedec ID code per JEP-108E
1.5ns 15
2ns 20
0.8ns 08
1ns 10
2ns
0.8ns 08
1ns 10
option 00
JEDEC2
rev 1.2A 12
Check sum for -6 A4
Check sum for -7 17
Check sum for -8 57
MITSUBISHI 1CFFFFFFFFFFFFFF
Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S72DALD-6
151.5ns
20
02
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125
126 Intetl specification frequency 100MHz 64
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Manufacture Specific Data
MH8S72DALD-7
MH8S72DALD-8
option
00
AFCL=2/3,AP,CK0,2
ADCL=3,AP,CK0,2
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Preliminary Spec.
Power Supply
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
PIN FUNCTION
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
CK
(CK0 ~ CK3)
CKE0 Input
/S
(/S0,2)
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1 Input
DQ0-63
CB0-7
DQMB0-7 Input
Vdd,Vss
SCL
SDA
SA0-3
Input/Output
Input
Output
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge of
CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
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Preliminary Spec.
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MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
BASIC FUNCTIONS
The MH8S72DALD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge, WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
COMMAND
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
MNEMONIC
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
CKE
CKE
n-1
H X L L H L X H X
H X L H L L V L V
n
/S
/RAS
/CAS
/WE BA0,1 A10
A11
X
X
V
X
X
V
V
V
V
A0-9
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
L H L H H H X X X
Burst Terminate TERM
Mode Register Set
MRS
H X L H H L X X X
H X L L L L L L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
X
X
X
X
X
L
V*1
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603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
TBST
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
MIT-DS-0341-0.0
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
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Preliminary Spec.
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MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
Op-Code,
Mode-Add
Command
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
Action
Terminate Burst,Latch CA,
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
ILLEGAL
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Preliminary Spec.
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MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
Command
MRS ILLEGAL
Action
L L L L
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
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Preliminary Spec.
1. All entries assume that CKE was High during the preceding clock cycle and the current
Some contents are subject to change without notice.
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
MITSUBISHI LSIs
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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ELECTRIC
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Preliminary Spec.
Some contents are subject to change without notice.
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
CKE
CKE
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
n
/RAS /CAS /WE Add
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
L X X X X X X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
L L X X X X X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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13
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17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
TBST(for Full Page) TBST(for Full Page)
CKEL
WRITE
CKEH
MRS
CKEH
WRITE
CKEL
WRITEA
WRITE
IDLE
REFA
CKEL
CKEH
ACT
ROW
ACTIVE
READ
READA
READ
POWER
DOWN
READ
AUTO
REFRESH
CKEL
CKEH
READ
SUSPEND
SUSPEND
POWER
APPLIED
MIT-DS-0341-0.0
WRITEA
WRITEA READA
CKEL
CKEH
POWER
ON
WRITEA
WRITEA
PRE PRE
PRE
CHARGE
PRE
PRE
READA
READA
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CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
17.Sep.1999
Preliminary Spec.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
LENGTH
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
WRITE
MODE
MIT-DS-0341-0.0
0
1
BURST
SINGLE BIT
MITSUBISHI
R:Reserved for Future Use
FP: Full Page
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17.Sep.1999
Preliminary Spec.
Some contents are subject to change without notice.
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
CK
Command
Read
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
Write
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Y
D0 D1 D2 D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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17.Sep.1999
Preliminary Spec.
ACT
OPERATION DESCRIPTION
(x8) . 1st output data is available after the /CAS Latency from the READ. The consecutive data
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
tRRD
ACT
Xb
Xb
01
tRCD
READ
Yb
0
01
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
Xa
Xa
00
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
length is defined by the Burst Length. The address sequence of the burst data is defined by
the Burst Type. Minimum delay time of a READ command after an ACT command to the
same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
tRASmin must be met.
MIT-DS-0341-0.0
MITSUBISHI
17.Sep.1999
ELECTRIC
17
( / 55 )
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