Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64QFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-7,-7L
-8,-8L
-10,-10L
100MHz
PC100 Compliant
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)100MHz
8.0ns(CL=3)100MHz
Utilizes industry standard 8M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
PCB Outline
(Front)
(Back)
APPLICATION
main memory or graphic memory in computer systems
1
2
143
144
MIT-DS-0306-0.0
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12.Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
PIN CONFIGURATION
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Some contents are subject to change without notice.
Block Diagram
/S0
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQMB0
DQMB1
DQMB2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
D0
/CS
D1
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
D2
/CS
D3
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CLK0
CKE0
/RAS
/CAS
/WE
BA0,BA1,A<11:0>D0 - D3
Vcc
Vss
10Ω
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
MIT-DS-0306-0.0
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
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3
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CLK1
10Ω
SERIAL PD
A0 A1 A2
10pF
SDA
12.Jan.1999
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
ByteFunction describedSPD enrty dataSPD DATA(hex)
0Defines # bytes written into serial memory at module mfgr12880
1Total # bytes of SPD memory device256 Bytes08
2Fundamental memory typeSDRAM04
3# Row Addresses on this assemblyA0-A110C
4# Column Addresses on this assembly
5# Module Banks on this assembly1BANK01
6Data Width of this assembly...x6440
7... Data Width continuation000
8Voltage interface standard of this assemblyLVTTL01
SDRAM Cycletime at Max. Supported CAS Latency (CL).
9
Cycle time for CL=3
10SDRAM Access from Clock6ns60
tAC for CL=38ns80
11DIMM Configuration type (Non-parity,Parity,ECC)Non-PARITY00
12Refresh Rate/Typeself refresh(15.625uS)80
13SDRAM width,Primary DRAM
14Error Checking SDRAM data widthN/A00
15Minimum Clock Delay,Back to Back Random Column Addresses101
16Burst Lengths Supported
17# Banks on Each SDRAM device4bank04
18CAS# Latency
Some contents are subject to change without notice.
PIN FUNCTION
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK0
CKE0Input
/S0
/RAS,/CAS,/WEInputCombination of /RAS,/CAS,/WE defines basic commands.
A0-11Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1Input
DQ0-63
DQMB0-7Input
Vdd,Vss
SCL
SDA
MIT-DS-0306-0.0
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Data In and Data out are referenced to the rising edge of
CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S64QFC provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/SChip Select : L=select, H=deselect
/RASCommand
/CASCommand
/WE
CKE
A10
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
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COMMAND TRUTH TABLE
COMMANDMNEMONIC
DeselectDESELHXHXXXXXX
No OperationNOPHXLHHHXXX
CKE
n-1
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
n
/S
/RAS
/CAS
/WE BA0,1A10
A11
X
X
A0-9
Row Adress Entry &
Bank Activate
Single Bank PrechargePREHXLLHLVLX
Precharge All Bank
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-RefreshREFAHHLLLHXXX
Self-Refresh EntryREFSHLLLLHXXX
Self-Refresh ExitREFSXLHHXXXXXX
Burst TerminateTERM
Mode Register Set
ACTHXLLHHVVV
PREA
WRITE
WRITEAHXLHLLVHV
READHXLHLHVLV
READAHXLHLHVHV
MRS
HXLLHLXHX
HXLHLLVLV
LHLHHHXXX
HXLHHLXXX
HXLLLLLL
V
X
X
X
X
X
X
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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12.Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Current State/S/RAS /CAS/WEAddress
IDLEHXXXXDESELNOP
LHHHXNOPNOP
LHHL
LHLX
LLHH
LLHL
LLLHXREFA
LLLL
ROW ACTIVEHXXXXDESELNOP
LHHHXNOPNOP
LHHLBATBSTNOP
LHLHBA,CA,A10READ/READA
LHLLBA,CA,A10
LLHHBA,RAACTBank Active/ILLEGAL*2
LLHLBA,A10PRE/PREAPrecharge/Precharge All
LLLHXREFAILLEGAL
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
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12.Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEAREADA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITEREAD
WRITEA
WRITE
WRITEA
READA
READ
READA
REFA
CKEL
CKEH
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
POWER
APPLIED
MIT-DS-0306-0.0
WRITEA
SUSPEND
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PREPRE
PRE
CHARGE
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READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
12.Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9A8A7 A6A5A4 A3A2A1 A0BA1BA0
00
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
00
LTMODEBTBL
BURST
LENGTH
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
CK
/S
/RAS
/CAS
/WE
BT= 0BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
WRITE
MODE
MIT-DS-0306-0.0
BURST
0
SINGLE BIT
1
MITSUBISHI
R:Reserved for Future Use
FP: Full Page
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ELECTRIC
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
ACT
tRCD
X
READ
Y
DQ
CL=2
DQ
Q0Q1Q2Q3
CL=3
Q0Q1Q2Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
X
READ
Y
DQ
DQ
DQ
DQ
DQ
MIT-DS-0306-0.0
Q0
Q0 Q1
Q0 Q1 Q2Q3
Q0 Q1 Q2Q3Q5 Q6Q4Q7
Q0 Q1 Q2Q3Q5 Q6Q4Q7
m=511
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Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
12.Jan.1999
Preliminary Spec.
Some contents are subject to change without notice.
CK
MITSUBISHI LSIs
MH8S64QFC -7,-7L,-8,-8L,-10,-10L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM