Some contents are subject to change without notice.
DESCRIPTION
The MH8S64BMG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-7
-8
-10
Utilizes industry standard 4M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
100MHz
CLK Access Time
(Component SDRAM)
6.0ns(CL=3)
6.0ns(CL=3)100MHz
8.0ns(CL=3)100MHz
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
85pin
94pin
95pin
124pin
125pin
Back side
1pin
10pin
11pin
Front side
40pin
41pin
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Some contents are subject to change without notice.
Block Diagram
/S0
/S1
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
/S2
/S3
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
10Ω
D0
D1
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
D4D6
DQ22
DQ23
D2
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
D5
DQ30
DQ31
D3
D7
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
BA0,BA1,A<11:0>
MIT-DS-0223-0.5
CK0
CK1
CK22SDRAMs+15pF
CK3
/RAS
/CAS
/WE
Vcc
Vss
10Ω
3SDRAMs+10pF
3SDRAMs+10pF
2SDRAMs+15pF
D0 - D9
D0 - D9
D0 - D9
D0 - D9
D0 - D9
D0 - D9
MITSUBISHI
ELECTRIC
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3
CKE1
CKE0
SCL
WP
47K
3.3V
10K
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
D5-D9
D0-D4
SDA
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
PIN FUNCTION
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK
(CK0 ~ CK3)
CKE0Input
/S
(/S0-3)
/RAS,/CAS,/WEInputCombination of /RAS,/CAS,/WE defines basic commands.
A0-11Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1Input
DQ0-63Input/Output
DQMB0-7Input
Vdd,Vss
SCL
SDA
SA0-3
Power Supply Power Supply for the memory mounted module.
Input
Output
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge of
CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
MIT-DS-0223-0.5
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29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S64BMG provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/SChip Select : L=select, H=deselect
/RASCommand
/CASCommand
/WE
CKE
A10
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
Some contents are subject to change without notice.
COMMAND TRUTH TABLE
COMMANDMNEMONIC
DeselectDESELHXHXXXXXX
No OperationNOPHXLHHHXXX
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
n-1
CKE
n
/S
/RAS
/CAS
/WE BA0,1A10
A11
X
X
A0-9
Row Adress Entry &
Bank Activate
Single Bank PrechargePREHXLLHLVLX
Precharge All Bank
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-RefreshREFAHHLLLHXXX
Self-Refresh EntryREFSHLLLLHXXX
Self-Refresh ExitREFSXLHHXXXXXX
Burst TerminateTERM
Mode Register Set
ACTHXLLHHVVV
PREA
WRITE
WRITEAHXLHLLVHV
READHXLHLHVLV
READAHXLHLHVHV
MRS
HXLLHLXHX
HXLHLLVLV
LHLHHHXXX
HXLHHLXXX
HXLLLLLL
V
X
X
X
X
X
X
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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ELECTRIC
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29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Current State/S/RAS /CAS/WEAddress
IDLEHXXXXDESELNOP
LHHHXNOPNOP
LHHL
LHLX
LLHH
LLHL
LLLHXREFA
LLLL
ROW ACTIVEHXXXXDESELNOP
LHHHXNOPNOP
LHHLBA
LHLHBA,CA,A10READ/READA
LHLLBA,CA,A10
LLHHBA,RAACTBank Active/ILLEGAL*2
LLHLBA,A10PRE/PREAPrecharge/Precharge All
LLLHXREFAILLEGAL
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
TBST(for Full Page)TBST(for Full Page)
CKEL
WRITE
CKEH
WRITEAREADA
MRS
CKEH
WRITE
CKEL
WRITEA
WRITE
WRITEA
IDLE
ACT
ROW
ACTIVE
READ
REFA
CKEL
CKEH
READ
READA
READ
READA
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
POWER
APPLIED
MIT-DS-0223-0.5
WRITEA
SUSPEND
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PREPRE
PRE
CHARGE
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READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9A8A7 A6A5A4 A3A2A1 A0BA1BA0
00
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
00
LTMODEBTBL
BURST
LENGTH
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
CK
/S
/RAS
/CAS
/WE
BT= 0BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
WRITE
MODE
MIT-DS-0223-0.5
0
1
BURST
SINGLE BIT
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ELECTRIC
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R:Reserved for Future Use
FP: Full Page
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
ACT
tRCD
X
READ
Y
DQ
CL=2
DQ
Q0Q1Q2Q3
CL=3
Q0Q1Q2Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
Address
ACT
X
READ
Y
DQ
DQ
DQ
DQ
DQ
MIT-DS-0223-0.5
Q0
Q0 Q1
Q0 Q1 Q2Q3
Q0 Q1 Q2Q3Q5 Q6Q4Q7
Q0 Q1 Q2Q3Q5 Q6Q4Q7
m=255
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ELECTRIC
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Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
BL=1
BL=2
BL=4
BL=8
BL=FP
29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
CK
Command
Read
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9
A10
2ACT command/tRCmin
ACT
tRRD
Xa
Xa
ACT
Xb
tRCD
Xb
READ
Y
0
tRCmin
tRAS
PRE
1
ACT
tRP
Xb
Xb
A11
BA0,1
DQ
Xa
00
XbXb
00
01
Qa0Qa1Qa2Qa3
Precharge all
01
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
MIT-DS-0223-0.5
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ELECTRIC
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29. Oct.1998
Preliminary Spec.
Some contents are subject to change without notice.
Multi Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
ACT
tRCD
Xa
MITSUBISHI LSIs
MH8S64BMG -7,-8, -10
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
READ
Y
ACT
Xb
READ
Y
PRE
A10
A11
BA0,1
DQ
Xa
XaXb
00
0
00
/CAS latency
Xb
10
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
0
0
10
00
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CK
BL + tRP
Command
A0-9
A10
A11XaXa
BA0,1
ACT
Xa
Xa
00
READ
tRCDtRP
Y
1
00
BL
ACT
Xa
Xa
00
DQ
CK
Command
CL=3
CL=2
MIT-DS-0223-0.5
Qa0Qa1Qa2Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
ACTREAD
BL
DQQa0Qa1Qa2Qa3
DQQa0Qa1Qa2Qa3
Internal Precharge Start Timing
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