Mitsubishi MH64S72QJA-8, MH64S72QJA-7 Datasheet

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

DESCRIPTION

APPLICATION

FEATURES

Type name

100MHz

6ns

MH64S72QJA-8

MH64S72QJA-7

TSOP package , industry standard Resister in TSSOP package ,

Frequency

(CL = 4)

100MHz

Some of contents are subject to change without notice.

6ns

(CL = 3)

PRELIMINARY

The MH64S72QJA is 67108864 - word x 72-bit Synchronous DRAM stacked structural module. This consist of thirty-six industry standard 32M x 4 Synchronous DRAMs in TSOP. The stacked structure of TSOP on a card edge dual inline package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.

MITSUBISHI LSIs

MH64S72QJA -7,-8

85pin

1pin

Max.

Utilizes industry standard 32M X 4 Synchronous DRAMs in

and industry standard PLL in TSSOP package. Single 3.3V +/- 0.3V power supply LVTTL Interface 4096 refresh cycles every 64ms

CLK Access Time [latch mode]

CLK Access Time [buffer mode]

94pin 95pin

124pin

125pin

10pin 11pin

40pin

41pin

Main memory unit for computers, Microcomputer memory.

MIT-DS-0332-0.0

MITSUBISHI ELECTRIC

168pin

84pin

16/Jun./1999

1

MITSUBISHI LSIs

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME

1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC

9 DQ6 51 NC 10 DQ7 52 11 DQ8 53 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 NC 21 22 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 38 39 40 VDD 82 SDA 41 VDD 83 SCL

42 CK0 84 VDD

VSS

CB0 CB1

/WE

A10 BA1

43

54 VSS

63 64 VSS

69 DQ24

80 NC 81

VSS 85

86 87 88 89 90 91 92 93

CB2 CB3

NC

VSS 110

CK2

WP

94 95 96 97 98

99 100 101 102 103 104 105 106 107 108 109

111 112 113 114 115 116 117 118 119 120 121 122 123 124 125

126

VSS 127 DQ32 128 DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7

VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 DQ40 137

VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD

VDD 144 DQ52 DQ46 145 NC DQ47 146 NC

CB4

CB5

VSS 149 DQ53

NC 150 DQ54 NC 151 DQ55

VDD 152 VSS

/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58

/S1

/RAS 157 VDD

VSS 158 DQ60

A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS

A9 163 BA0 A11

VDD 166 SA1 CK1 167 SA2

NC

147 148 VSS

156 DQ59

164 NC 165 SA0

168 VDD

VSS

CKE0

/S3

NC

CB6 CB7

REGE

CK3

NC = No Connection

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2

Add

D18

D19D0D1

D2

D20D3D21D4D22D5D23

D6

D24D7D25

D8

D26

D9

D27

D10

D28

D11

D29

D12

D30

D13

D31

D14

D32

D15

D33

D16

D34

D17

D35

Vdd

CKE0

/S0-3

DQM0-7

/W

/RAS

/CAS

REGE

MITSUBISHI LSIs

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

RCKE0

R/S0-3

RDQM0-7

DQ0 DQ1

DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

DQ16 DQ17 DQ18

DQ19 DQ20 DQ21 DQ22 DQ23

DQ32 DQ33

DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

DQ48 DQ49 DQ50

DQ51 DQ52 DQ53 DQ54 DQ55

DQ24 DQ25

DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

CB0 CB1 CB2 CB3

From PLL

CK0 CK1 - CK3 Terminated

RCKE0 R/S0 R/S1 R/S2 R/S3

PLL

D0-35 D9-12,D17-21,D26 D0-3,D8,D27-30,D35 D13-16,D22-25 D4-7,D31-34

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RDQM 0 RDQM 1 RDQM 2 RDQM 3 RDQM 4 RDQM 5 RDQM 6 RDQM 7

DQ56 DQ57

DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

CB4 CB5 CB6 CB7

D0-1,D18-19 D2-3,D8,D20-21,D26 D4-5,D22-23 D6-7,D24-25 D9-10,D27-28

D11-12,D17,D29-30,D35 D13-14,D31-32 D15-16,D33-34

MITSUBISHI ELECTRIC

SCL WP

VDD

VSS

SERIAL PD

A0 A1 A2

SA0 SA1 SA2

16/Jun./1999

SDA

D0 to D35

3

MITSUBISHI LSIs

Serial Presence Detect Table I

SDRAM Cycletime at Max. Supported CAS Latency (CL).

ECC

Minimum Clock Delay,Back to Back Random Column Addresses

Burst Lengths Supported

1/2/4/8/Full page

buffered,registered

Precharge All,Auto precharge

Write1/Read Burst

SDRAM Access form Clock(2nd highest CAS latency)

SDRAM Access form Clock(3rd highest CAS latency)

-8-8-7

-7

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Byte Function described SPD enrty data SPD DATA(hex)

0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly 5 # Module Banks on this assembly 6 Data Width of this assembly... 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9

Cycle time for CL=3

10 SDRAM Access from Clock

tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM 14 Error Checking SDRAM data width 15 16 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency

19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes 22 SDRAM Device Attributes:General 23 SDRAM Cycle time(2nd highest CAS latency)

Cycle time for CL=2

A0-A10 0B

2BANK 02

x72 48

10ns

6ns 60

x4 04 x4 04

1 01

2/3 06

10ns

13ns D0

A0

02

8F

1F

0E A0

24

tAC for CL=2

25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 26

27 Precharge to Active Minimum 20ns 14

28 Row Active to Row Active Min. 20ns 14

29 RAS to CAS Delay Min 20ns 14

30 Active to Precharge Min 50ns 32

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6ns 60 7ns 70

N/A 00

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MITSUBISHI LSIs

Serial Presence Detect Table II

4D483634533732514A412D37202020202020

4D483634533732514A412D38202020202020

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

31 Density of each bank on module

32

33 Command and Address signal input hold time

34 Data signal input setup time 2ns

35 Data signal input hold time

36-61

62 SPD Revision 63 Checksum for bytes 0-62

64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF

72 Manufacturing location Miyoshi,Japan 01

73-90 Manufactures Part Number

Command and Address signal input setup time 2ns 20

Superset Information (may be used in future) option 00

256MByte 40

1ns 10

rev 1.2A 12

Check sum for -7

Check sum for -8

Tajima,Japan 02

NC,USA 03

Germany 04

MH64S72QJA-7

20

61

A1

MH64S72QJA-8

91-92 Revision Code PCB revision rrrr 93-94 Manufacturing date year/week code yyww 95-98 Assembly Serial Number serial number ssssssss

99-125 Manufacture Specific Data option 00

126 Intetl specification frequency

127 Intel specification CAS# Latency support

128+ Unused storage locations open 00

100MHz 64

CL=2/3,AP,CK0

8F

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4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

the bank to which a command is applied.BA must be set

Register enable:When REGE is low,All control signals and

PIN FUNCTION

MITSUBISHI LSIs

MH64S72QJA -7,-8

CK0

CKE0

/S0 - 3

/RAS,/CAS,/W

A0-11

Input

Master Clock:All other inputs are referenced to the rising edge of CK

Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.

Chip Select: When /S is high,any command means No Operation.

Combination of /RAS,/CAS,/W defines basic commands.

A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-10.A10 is also used to indicate precharge option.When A10 is high at a read / write

BA0-1

DQ0-63 CB0-7

DQM0-7

Vdd,Vss

REGE

Input

Input/Output

Input

Power Supply

Output

command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA0,1 specifies

with ACT,PRE,READ,WRITE commands Data In and Data out are referenced to the rising edge

of CK Din Mask/Output Disable:When DQMB is high in burst

write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.

Power Supply for the memory mounted module.

address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode)

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MITSUBISHI LSIs

Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In

READ command starts burst read from the active bank indicated by BA.First output

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

BASIC FUNCTIONS

The MH64S72QJA provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh.

addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.

CK

/S /RAS /CAS /WE

CKE A10

Chip Select : L=select, H=deselect Command Command Command

Refresh Option @refresh command Precharge Option @precharge or read/write command

define basic commands

Activate(ACT) [/RAS =L, /CAS = /WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read(READ) [/RAS =H,/CAS =L, /WE =H]

data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).

Write(WRITE) [/RAS =H, /CAS = /WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.

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7

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Precharge All Bank

COMMAND TRUTH TABLE

MITSUBISHI LSIs

MH64S72QJA -7,-8

COMMAND

Deselect

No Operation

Row Adress Entry &

Bank Activate

Single Bank Precharge

Column Address Entry

& Write

Column Address Entry

& Write with Auto-

Precharge

Column Address Entry

& Read

Column Address Entry

& Read with Auto

Precharge

Auto-Refresh

Self-Refresh Entry

Self-Refresh Exit

Mode Register Set MRS H X L L L L L L L

MNEMONIC

DESEL

NOP

ACT

PRE

PREA

WRITE

WRITEA

READ

READA

REFA H H L L L H X X X REFS

REFSX

CKE

n-1

H H

H

H H

H

H L L

CKE

/S

n X

H L

X

L

X

X L L

L

X

L

X

L

X

L

X

L

L H

H L

H

/RAS

X H

L

H

L X

H

/CAS

X H

H

H H

L

L X

H

/WE

X H

H

L L

L

H

H X

H

BA0,1

X X

V

V X

V

X X

X

A11

X X

V

X X

V

X X

X

A10

X X

V

L H

L

H

L

H

X X

X

A0-9

X X

V

X X

V

X X

V*1

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

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4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE

MITSUBISHI LSIs

MH64S72QJA -7,-8

Current State

IDLE

ROW ACTIVE

/S

/RAS

H L

L L

L

L H

L L

L

L L

/CAS

X H H H L L

L L

X H

H H

H

L L

L

/WE

X H

H L

H H

L

L X

H H

L

L H

H L

X H L X H L

H L

X H

L H

L

H L

H

Address

X X

BA BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X

X BA

BA,CA,A10

BA,CA,A10 BA,RA

BA,A10 X

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

Action

NOP NOP

ILLEGAL*2 ILLEGAL*2

Bank Active,Latch RA NOP*4

Auto-Refresh*5 Mode Register Set*5 NOP

NOP NOP Begin Read,Latch CA,

Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge

Bank Active/ILLEGAL*2 Precharge/Precharge All

ILLEGAL

READ

L H

L L

L

L L

L X

H H

H

L L

L

L X

H H

L

H H

L L

Op-Code,

L

Mode-Add X

X H

X BA

L

H

BA,CA,A10

L

H

BA,RA BA,A10

L H

X Op-Code,

L

Mode-Add

MRS

DESEL

NOP

TBST

READ/READA

WRITE/WRITEA

ACT

PRE/PREA

REFA

MRS

ILLEGAL NOP(Continue Burst to END)

NOP(Continue Burst to END) Terminate Burst

Terminate Burst,Latch CA, Begin New Read,Determine

Auto-Precharge*3 Terminate Burst,Latch CA,

Begin Write,Determine AutoPrecharge*3

Bank Active/ILLEGAL*2 Terminate Burst,Precharge

ILLEGAL ILLEGAL

MIT-DS-0332-0.0

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MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State

WRITE

READ with

AUTO

PRECHARGE

WRITE with

AUTO

PRECHARGE L

/S

/RAS

H L

L

L L

H L L

L L

L L L

L H

L

L L L

L L

L

/CAS

X H H

H

L L L

L X

H H H

H L

L L

L X

H H H

H L

L L

L

/WE

X H

H

L

H H

L L

X H H

L L

H H L

L X

H H

L L H

H L

L

X H L

H

L

H L H

L X

H L H

L H

L X

H L H

L H

L

Address X X

BA

BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X X BA BA,CA,A10

BA,CA,A10 BA,RA

BA,A10 X Op-Code,

Mode-Add X X BA

BA,CA,A10 BA,CA,A10 BA,RA

BA,A10 X Op-Code,

Mode-Add

Command

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/READA

WRITE/

WRITEA

ACT

PRE/PREA

REFA

MRS

Action NOP(Continue Burst to END) NOP(Continue Burst to END)

Terminate Burst Terminate Burst,Latch CA, Begin Read,Determine Auto-

Precharge*3 Terminate Burst,Latch CA,

Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge

ILLEGAL ILLEGAL NOP(Continue Burst to END)

NOP(Continue Burst to END) ILLEGAL ILLEGAL

ILLEGAL Bank Active/ILLEGAL*2

ILLEGAL*2 ILLEGAL

ILLEGAL NOP(Continue Burst to END)

NOP(Continue Burst to END) ILLEGAL

ILLEGAL ILLEGAL Bank Active/ILLEGAL*2

ILLEGAL*2 ILLEGAL

ILLEGAL

MIT-DS-0332-0.0

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MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State

PRE -

CHARGING

ROW

ACTIVATING

/S

H L L L L

L L

L H

L L

/RAS

X H

H H

L L

X H H H L

L L

/CAS

X H H L H

H L

L X

H H

L H

H L

/WE

X H

L X

H L

X H L X H

L H

Address X X BA

BA,CA,A10 BA,RA

BA,A10 X

Op-Code, Mode-Add X

X BA

BA,CA,A10 BA,RA

BA,A10 X

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2

ILLEGAL*2 ILLEGAL*2

NOP*4(Idle after tRP) ILLEGAL

ILLEGAL

NOP(Row Active after tRCD NOP(Row Active after tRCD

ILLEGAL*2 ILLEGAL*2

ILLEGAL*2 ILLEGAL*2 ILLEGAL

WRITE RE-

COVERING

L

H L

L L

L

X H

H H

L L

L

X H

H L

H H

L

Op-Code,

L

Mode-Add

X

H

X BA

L X

BA,CA,A10 BA,RA

H L

BA,A10 X

H L

Op-Code,

Mode-Add

MRS

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

ILLEGAL

NOP NOP

ILLEGAL*2 ILLEGAL*2

ILLEGAL

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MH64S72QJA -7,-8

1. All entries assume that CKE was High during the preceding clock cycle and the current

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE(continued)

MITSUBISHI LSIs

Current State

RE-

FRESHING

MODE

REGISTER

SETTING

/S

H L

L L

L

H L L

L L

L

/RAS

X H

H H

L L

L

X H H

H L

L

/CAS

X H

H L

H H

L

X H H

L H

H

/WE

X H

L X

H L

H

L

X H L

X H

L

Address X X

BA BA,CA,A10

BA,RA BA,A10

X Op-Code,

Mode-Add X X BA

BA,CA,A10 BA,RA

BA,A10

Command

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

REFA

MRS

DESEL

NOP

TBST

READ/WRITE

ACT

PRE/PREA

Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL

ILLEGAL ILLEGAL

ILLEGAL

NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL

ILLEGAL ILLEGAL

ILLEGAL

L

H

L

X Op-Code,

Mode-Add

REFA

MRS

ILLEGAL

ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation

NOTES:

clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and / or date-integrity are not guaranteed.

MIT-DS-0332-0.0

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ELECTRIC

12

MH64S72QJA -7,-8

2. Power-Down and Self-Refresh can be entered only form the All banks idle State.

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

FUNCTION TRUTH TABLE for CKE

MITSUBISHI LSIs

Current State

SELF -

REFRESH*1 L

POWER

DOWN L

ALL BANKS

IDLE*2

CKE

n-1

H

L L L L

L H

H H

CKE

n

X H H H H H

L

X H

L H

L

/S

X H

L L L L

X X

X X X

L H

L L

/RAS

X X H H H L

X X

X L

X H

H

/CAS

X X

H H L X

X X

X X X

L X

H H

/WE

X X H L X X

X X

X H

L

Add

X

INVALID Exit Self-Refresh(Idle after tRC)

X

Exit Self-Refresh(Idle after tRC)

X

ILLEGAL

X

ILLEGAL

X

ILLEGAL

X

NOP(Maintain Self-Refresh)

X X

INVALID Exit Power Down to Idle

X

NOP(Maintain Self-Refresh)

X X

Refer to Function Truth Table Enter Self-Refresh

X

Enter Power Down

X

Enter Power Down

X

ILLEGAL

X

Action

ANY STATE

other than H

listed above

H H

L H

L L

L

X H

L H

L

L L

X X

X

H L

X X

X X X

L X

X X

X

X X

X X X

ILLEGAL

X

ILLEGAL

X

Refer to Current State = Power Down

X X

Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3

X X

Exit CK0 Suspend at Next Cycle*3

X

Maintain CK0 Suspend

ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care

NOTES:

1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.

3. Must be legal command.

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13

MITSUBISHI LSIs

POWER ON SEQUENCE

After these sequence, the SDRAM is idle state and ready for normal operation.

LENGTH

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP condition at the inputs.

2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

CK

/S

BA0

LATENCY

MODE

0

BA1

0

CL

0 0 0 0 0 1

0 1 0 0 1 1

1 0 0 1 0 1

1 1 0 1 1 1

A10

A11

0

/CAS LATENCY

A9

WM

A8

0

R R

2

3

R R

A7

0

A6

A5

LTMODE

A4

A3

BT

BURST

TYPE

A2

A1

BL

A0

BA0,1 A11-0

BL

0 0 0 0 0 1

0 1 0 0 1 1

1 0 0 1 0 1

1 1 0 1 1 1

0

1

/RAS /CAS

/WE

BT= 0

1 2

4 8

R R

R

FP

SEQUENTIAL INTERLEAVED

V

BT= 1

1 2

4 8

R R

WRITE MODE

MIT-DS-0332-0.0

0

1

BURST SINGLE BIT

MITSUBISHI

R:Reserved for Future Use FP: Full Page

ELECTRIC

16/Jun./1999

14

CK

MITSUBISHI LSIs

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Command

Address

DQ

CL= 3 BL= 4

Initial Address BL

A2

0 0

1

A1

0 0

1 1

0

A0

0 1

8

0

Read

Y

/CAS Latency

1

0

2

1

3

2

4

3

5

4

Sequential

3

2

4

3

5

4

6

5

7

6

Q0 Q1 Q2 Q3

Burst Length

Column Addressing

5

4

6

5

7

6

0

7

1

0

7

6

0

7

1

0

2

1

3

2

Burst Type

1

0

1

3

2

3

5

4

Write

Y

D0 D1

Burst Length

Interleaved

3

2

3

1

0

1

7

6

D3

D2

5

4

5

7

6

7

1

0

7

6

7

5

4

5

3

2

0

1 1

1

-

1 0

1 1

1 0

0 0

1

4

0

1 1

1 0

2

-

1

6

5

7

6

0

7

1

0

2

1

3

2

0

3

1

0 1

0

7

1

0

2

1

3

2

0

3

1

0 1

2

1

3

2 3

4

3

5

4 5

6

4

5

7

6

7

1

0

1

3

2

3

1

0 1

0

6

7

5

4

5

3

2

3

1

0 1

0

1

3

2 3

2

3

1

0 1

0

MIT-DS-0332-0.0

MITSUBISHI ELECTRIC

16/Jun./1999

15

MITSUBISHI LSIs

ABSOLUTE MAXIMUM RATINGS

mA

RECOMMENDED OPERATING CONDITION

CAPACITANCE

f=1MHz

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Symbol

Vdd

VI

VO

IO

Pd

Topr

Tstg

(Ta=0 ~ 70°C, unless otherwise noted)

Symbol

Operating Temperature

Parameter

Supply Voltage

Input Voltage

Output Voltage Output Current

Power Dissipation

Storage Temperature

Parameter

Condition with respect to Vss with respect to Vss

with respect to Vss

Ta=25°C

Min.

Limits

Typ.

Ratings

-0.5 ~ 4.6

-0.5 ~ 4.6 50

40

0 ~ 70

-45 ~ 100

Max.

Unit

V V

V

W

°C °C

Unit

Vdd Vss VIH

VIL

(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)

Symbol

CI(A) CI(C)

CI(K)

CI/O

High-Level Input Voltage all inputs

Low-Level Input Voltage all inputs

Input Capacitance, address pin

Input Capacitance, control pin

Input Capacitance, CK0 pin

Input Capacitance, I/O pin

Supply Voltage Supply Voltage

Parameter

Test Condition

Vi=25mVrms

3.0 0

2.0

-0.3

VI = Vss

3.3 0

Limits(max.)

Vdd+0.3

20 20

14

22

3.6 0

0.8

V V

V

Unit

pF pF

MIT-DS-0332-0.0

MITSUBISHI ELECTRIC

16/Jun./1999

16

MITSUBISHI LSIs

AVERAGE SUPPLY CURRENT from Vdd

AC OPERATING CONDITIONS AND CHARACTERISTICS

operating current, single bank

tCLK=min,CKE=H,/CS > Vcc-0.2V,VIH > Vcc-0.2V,VIL < 0.2V

CLK=L & CKE=H,/CS > Vcc-0.2V,VIH > Vcc-0.2V,VIL < 0.2V

tCLK=min,CKE=L,/CS > Vcc-0.2V

CLK=L,CKE=L,/CS > Vcc-0.2V

MH64S72QJA -7,-8

4,831,838,208-BIT ( 67,108,864-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Symbol

Icc1

Icc2N

Icc2NS

Icc2P

Icc2PS 82

Icc3N

Icc3NS

Icc3P

Icc3PS CKE=L,CLK=L

Icc4 Icc5

Icc6

Note)

1.Icc(max) is specified at the output open condition.

precharge standby current in Non Power down mode precharge standby current in

Power down mode active standby current in Non

Power down mode active standby current in Power down mode

burst current auto-refresh current

self-refresh current

Parameter

tRC=min.tCLK=min, BL=1, CL=3

all input signals are fixed.

CKE=H,tCLK=min. CKE=H,CLK=L

CKE=L,tCLK=min.

tCLK=min, BL=4, CL=3, all banks active(discrete)

tRC=min, tCLK=min CKE <0.2V

Test Condition

(Note1) (Note1)

(Note1) (Note1) (Note1)

(Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1)

(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)

Limits(max)

-7

3059 1349

333 701

-8

3059 1349

333

701

82

945 809

225

1709

945 809

225

3059 4229

1709

3059 4229

82 82

Unit

mA mA mA mA mA

mA mA

mA mA mA

Symbol

VOH(DC) VOL(DC)

IOZ

Ii

Parameter

High-Level Output Voltage(DC) Low-Level Output Voltage(DC)

Off-stare Output Current Input Current

Test Condition

IOH=-2mA IOL=2mA

Q floating VO=0 ~ Vdd VIH=0 ~ Vdd+0.3V

Limits

Min.

2.4

-10

-20

Max.

0.4 10 20

Unit

V V

uA uA

MIT-DS-0332-0.0

MITSUBISHI ELECTRIC

16/Jun./1999

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